2 * Copyright 2012 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
14 /include/ "skeleton.dtsi"
17 interrupt-parent = <&intc>;
24 compatible = "arm,cortex-a8";
30 reg = <0x40000000 0x20000000>;
39 * This is a dummy clock, to be used as placeholder on
40 * other mux clocks when a specific parent clock is not
41 * yet implemented. It should be dropped when the driver
46 compatible = "fixed-clock";
47 clock-frequency = <0>;
50 osc24M: osc24M@01c20050 {
52 compatible = "allwinner,sun4i-osc-clk";
53 reg = <0x01c20050 0x4>;
54 clock-frequency = <24000000>;
59 compatible = "fixed-clock";
60 clock-frequency = <32768>;
65 compatible = "allwinner,sun4i-pll1-clk";
66 reg = <0x01c20000 0x4>;
73 compatible = "allwinner,sun4i-cpu-clk";
74 reg = <0x01c20054 0x4>;
75 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
80 compatible = "allwinner,sun4i-axi-clk";
81 reg = <0x01c20054 0x4>;
85 axi_gates: axi_gates@01c2005c {
87 compatible = "allwinner,sun4i-axi-gates-clk";
88 reg = <0x01c2005c 0x4>;
90 clock-output-names = "axi_dram";
95 compatible = "allwinner,sun4i-ahb-clk";
96 reg = <0x01c20054 0x4>;
100 ahb_gates: ahb_gates@01c20060 {
102 compatible = "allwinner,sun5i-a13-ahb-gates-clk";
103 reg = <0x01c20060 0x8>;
105 clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
106 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
107 "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
108 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_stimer",
109 "ahb_ve", "ahb_lcd", "ahb_csi", "ahb_de_be",
110 "ahb_de_fe", "ahb_iep", "ahb_mali400";
113 apb0: apb0@01c20054 {
115 compatible = "allwinner,sun4i-apb0-clk";
116 reg = <0x01c20054 0x4>;
120 apb0_gates: apb0_gates@01c20068 {
122 compatible = "allwinner,sun5i-a13-apb0-gates-clk";
123 reg = <0x01c20068 0x4>;
125 clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
129 apb1_mux: apb1_mux@01c20058 {
131 compatible = "allwinner,sun4i-apb1-mux-clk";
132 reg = <0x01c20058 0x4>;
133 clocks = <&osc24M>, <&dummy>, <&osc32k>;
136 apb1: apb1@01c20058 {
138 compatible = "allwinner,sun4i-apb1-clk";
139 reg = <0x01c20058 0x4>;
140 clocks = <&apb1_mux>;
143 apb1_gates: apb1_gates@01c2006c {
145 compatible = "allwinner,sun5i-a13-apb1-gates-clk";
146 reg = <0x01c2006c 0x4>;
148 clock-output-names = "apb1_i2c0", "apb1_i2c1",
149 "apb1_i2c2", "apb1_uart1", "apb1_uart3";
154 compatible = "simple-bus";
155 #address-cells = <1>;
157 reg = <0x01c20000 0x300000>;
160 intc: interrupt-controller@01c20400 {
161 compatible = "allwinner,sun4i-ic";
162 reg = <0x01c20400 0x400>;
163 interrupt-controller;
164 #interrupt-cells = <1>;
167 pio: pinctrl@01c20800 {
168 compatible = "allwinner,sun5i-a13-pinctrl";
169 reg = <0x01c20800 0x400>;
171 clocks = <&apb0_gates 5>;
173 interrupt-controller;
174 #address-cells = <1>;
178 uart1_pins_a: uart1@0 {
179 allwinner,pins = "PE10", "PE11";
180 allwinner,function = "uart1";
181 allwinner,drive = <0>;
182 allwinner,pull = <0>;
185 uart1_pins_b: uart1@1 {
186 allwinner,pins = "PG3", "PG4";
187 allwinner,function = "uart1";
188 allwinner,drive = <0>;
189 allwinner,pull = <0>;
192 i2c0_pins_a: i2c0@0 {
193 allwinner,pins = "PB0", "PB1";
194 allwinner,function = "i2c0";
195 allwinner,drive = <0>;
196 allwinner,pull = <0>;
199 i2c1_pins_a: i2c1@0 {
200 allwinner,pins = "PB15", "PB16";
201 allwinner,function = "i2c1";
202 allwinner,drive = <0>;
203 allwinner,pull = <0>;
206 i2c2_pins_a: i2c2@0 {
207 allwinner,pins = "PB17", "PB18";
208 allwinner,function = "i2c2";
209 allwinner,drive = <0>;
210 allwinner,pull = <0>;
215 compatible = "allwinner,sun4i-timer";
216 reg = <0x01c20c00 0x90>;
221 wdt: watchdog@01c20c90 {
222 compatible = "allwinner,sun4i-wdt";
223 reg = <0x01c20c90 0x10>;
226 uart1: serial@01c28400 {
227 compatible = "snps,dw-apb-uart";
228 reg = <0x01c28400 0x400>;
232 clocks = <&apb1_gates 17>;
236 uart3: serial@01c28c00 {
237 compatible = "snps,dw-apb-uart";
238 reg = <0x01c28c00 0x400>;
242 clocks = <&apb1_gates 19>;
247 compatible = "allwinner,sun4i-i2c";
248 reg = <0x01c2ac00 0x400>;
250 clocks = <&apb1_gates 0>;
251 clock-frequency = <100000>;
256 compatible = "allwinner,sun4i-i2c";
257 reg = <0x01c2b000 0x400>;
259 clocks = <&apb1_gates 1>;
260 clock-frequency = <100000>;
265 compatible = "allwinner,sun4i-i2c";
266 reg = <0x01c2b400 0x400>;
268 clocks = <&apb1_gates 2>;
269 clock-frequency = <100000>;