arch/arm/boot/dts/sun6i-a31.dtsi

   1 /*
   2  * Copyright 2013 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  *     You should have received a copy of the GNU General Public
  22  *     License along with this file; if not, write to the Free
  23  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  24  *     MA 02110-1301 USA
  25  *
  26  * Or, alternatively,
  27  *
  28  *  b) Permission is hereby granted, free of charge, to any person
  29  *     obtaining a copy of this software and associated documentation
  30  *     files (the "Software"), to deal in the Software without
  31  *     restriction, including without limitation the rights to use,
  32  *     copy, modify, merge, publish, distribute, sublicense, and/or
  33  *     sell copies of the Software, and to permit persons to whom the
  34  *     Software is furnished to do so, subject to the following
  35  *     conditions:
  36  *
  37  *     The above copyright notice and this permission notice shall be
  38  *     included in all copies or substantial portions of the Software.
  39  *
  40  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  41  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  42  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  43  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  44  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  45  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  46  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  47  *     OTHER DEALINGS IN THE SOFTWARE.
  48  */
  49
  50 /include/ "skeleton.dtsi"
  51
  52 / {
  53         interrupt-parent = <&gic>;
  54
  55         aliases {
  56                 serial0 = &uart0;
  57                 serial1 = &uart1;
  58                 serial2 = &uart2;
  59                 serial3 = &uart3;
  60                 serial4 = &uart4;
  61                 serial5 = &uart5;
  62                 ethernet0 = &gmac;
  63         };
  64
  65
  66         cpus {
  67                 enable-method = "allwinner,sun6i-a31";
  68                 #address-cells = <1>;
  69                 #size-cells = <0>;
  70
  71                 cpu@0 {
  72                         compatible = "arm,cortex-a7";
  73                         device_type = "cpu";
  74                         reg = <0>;
  75                 };
  76
  77                 cpu@1 {
  78                         compatible = "arm,cortex-a7";
  79                         device_type = "cpu";
  80                         reg = <1>;
  81                 };
  82
  83                 cpu@2 {
  84                         compatible = "arm,cortex-a7";
  85                         device_type = "cpu";
  86                         reg = <2>;
  87                 };
  88
  89                 cpu@3 {
  90                         compatible = "arm,cortex-a7";
  91                         device_type = "cpu";
  92                         reg = <3>;
  93                 };
  94         };
  95
  96         memory {
  97                 reg = <0x40000000 0x80000000>;
  98         };
  99
 100         pmu {
 101                 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
 102                 interrupts = <0 120 4>,
 103                              <0 121 4>,
 104                              <0 122 4>,
 105                              <0 123 4>;
 106         };
 107
 108         clocks {
 109                 #address-cells = <1>;
 110                 #size-cells = <1>;
 111                 ranges;
 112
 113                 osc24M: osc24M {
 114                         #clock-cells = <0>;
 115                         compatible = "fixed-clock";
 116                         clock-frequency = <24000000>;
 117                 };
 118
 119                 osc32k: clk@0 {
 120                         #clock-cells = <0>;
 121                         compatible = "fixed-clock";
 122                         clock-frequency = <32768>;
 123                         clock-output-names = "osc32k";
 124                 };
 125
 126                 pll1: clk@01c20000 {
 127                         #clock-cells = <0>;
 128                         compatible = "allwinner,sun6i-a31-pll1-clk";
 129                         reg = <0x01c20000 0x4>;
 130                         clocks = <&osc24M>;
 131                         clock-output-names = "pll1";
 132                 };
 133
 134                 pll6: clk@01c20028 {
 135                         #clock-cells = <1>;
 136                         compatible = "allwinner,sun6i-a31-pll6-clk";
 137                         reg = <0x01c20028 0x4>;
 138                         clocks = <&osc24M>;
 139                         clock-output-names = "pll6", "pll6x2";
 140                 };
 141
 142                 cpu: cpu@01c20050 {
 143                         #clock-cells = <0>;
 144                         compatible = "allwinner,sun4i-a10-cpu-clk";
 145                         reg = <0x01c20050 0x4>;
 146
 147                         /*
 148                          * PLL1 is listed twice here.
 149                          * While it looks suspicious, it's actually documented
 150                          * that way both in the datasheet and in the code from
 151                          * Allwinner.
 152                          */
 153                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
 154                         clock-output-names = "cpu";
 155                 };
 156
 157                 axi: axi@01c20050 {
 158                         #clock-cells = <0>;
 159                         compatible = "allwinner,sun4i-a10-axi-clk";
 160                         reg = <0x01c20050 0x4>;
 161                         clocks = <&cpu>;
 162                         clock-output-names = "axi";
 163                 };
 164
 165                 ahb1_mux: ahb1_mux@01c20054 {
 166                         #clock-cells = <0>;
 167                         compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
 168                         reg = <0x01c20054 0x4>;
 169                         clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
 170                         clock-output-names = "ahb1_mux";
 171                 };
 172
 173                 ahb1: ahb1@01c20054 {
 174                         #clock-cells = <0>;
 175                         compatible = "allwinner,sun4i-a10-ahb-clk";
 176                         reg = <0x01c20054 0x4>;
 177                         clocks = <&ahb1_mux>;
 178                         clock-output-names = "ahb1";
 179                 };
 180
 181                 ahb1_gates: clk@01c20060 {
 182                         #clock-cells = <1>;
 183                         compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
 184                         reg = <0x01c20060 0x8>;
 185                         clocks = <&ahb1>;
 186                         clock-output-names = "ahb1_mipidsi", "ahb1_ss",
 187                                         "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
 188                                         "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
 189                                         "ahb1_nand0", "ahb1_sdram",
 190                                         "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
 191                                         "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
 192                                         "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
 193                                         "ahb1_ehci1", "ahb1_ohci0",
 194                                         "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
 195                                         "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
 196                                         "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
 197                                         "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
 198                                         "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
 199                                         "ahb1_drc0", "ahb1_drc1";
 200                 };
 201
 202                 apb1: apb1@01c20054 {
 203                         #clock-cells = <0>;
 204                         compatible = "allwinner,sun4i-a10-apb0-clk";
 205                         reg = <0x01c20054 0x4>;
 206                         clocks = <&ahb1>;
 207                         clock-output-names = "apb1";
 208                 };
 209
 210                 apb1_gates: clk@01c20068 {
 211                         #clock-cells = <1>;
 212                         compatible = "allwinner,sun6i-a31-apb1-gates-clk";
 213                         reg = <0x01c20068 0x4>;
 214                         clocks = <&apb1>;
 215                         clock-output-names = "apb1_codec", "apb1_digital_mic",
 216                                         "apb1_pio", "apb1_daudio0",
 217                                         "apb1_daudio1";
 218                 };
 219
 220                 apb2: clk@01c20058 {
 221                         #clock-cells = <0>;
 222                         compatible = "allwinner,sun4i-a10-apb1-clk";
 223                         reg = <0x01c20058 0x4>;
 224                         clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
 225                         clock-output-names = "apb2";
 226                 };
 227
 228                 apb2_gates: clk@01c2006c {
 229                         #clock-cells = <1>;
 230                         compatible = "allwinner,sun6i-a31-apb2-gates-clk";
 231                         reg = <0x01c2006c 0x4>;
 232                         clocks = <&apb2>;
 233                         clock-output-names = "apb2_i2c0", "apb2_i2c1",
 234                                         "apb2_i2c2", "apb2_i2c3", "apb2_uart0",
 235                                         "apb2_uart1", "apb2_uart2", "apb2_uart3",
 236                                         "apb2_uart4", "apb2_uart5";
 237                 };
 238
 239                 mmc0_clk: clk@01c20088 {
 240                         #clock-cells = <0>;
 241                         compatible = "allwinner,sun4i-a10-mod0-clk";
 242                         reg = <0x01c20088 0x4>;
 243                         clocks = <&osc24M>, <&pll6 0>;
 244                         clock-output-names = "mmc0";
 245                 };
 246
 247                 mmc1_clk: clk@01c2008c {
 248                         #clock-cells = <0>;
 249                         compatible = "allwinner,sun4i-a10-mod0-clk";
 250                         reg = <0x01c2008c 0x4>;
 251                         clocks = <&osc24M>, <&pll6 0>;
 252                         clock-output-names = "mmc1";
 253                 };
 254
 255                 mmc2_clk: clk@01c20090 {
 256                         #clock-cells = <0>;
 257                         compatible = "allwinner,sun4i-a10-mod0-clk";
 258                         reg = <0x01c20090 0x4>;
 259                         clocks = <&osc24M>, <&pll6 0>;
 260                         clock-output-names = "mmc2";
 261                 };
 262
 263                 mmc3_clk: clk@01c20094 {
 264                         #clock-cells = <0>;
 265                         compatible = "allwinner,sun4i-a10-mod0-clk";
 266                         reg = <0x01c20094 0x4>;
 267                         clocks = <&osc24M>, <&pll6 0>;
 268                         clock-output-names = "mmc3";
 269                 };
 270
 271                 spi0_clk: clk@01c200a0 {
 272                         #clock-cells = <0>;
 273                         compatible = "allwinner,sun4i-a10-mod0-clk";
 274                         reg = <0x01c200a0 0x4>;
 275                         clocks = <&osc24M>, <&pll6 0>;
 276                         clock-output-names = "spi0";
 277                 };
 278
 279                 spi1_clk: clk@01c200a4 {
 280                         #clock-cells = <0>;
 281                         compatible = "allwinner,sun4i-a10-mod0-clk";
 282                         reg = <0x01c200a4 0x4>;
 283                         clocks = <&osc24M>, <&pll6 0>;
 284                         clock-output-names = "spi1";
 285                 };
 286
 287                 spi2_clk: clk@01c200a8 {
 288                         #clock-cells = <0>;
 289                         compatible = "allwinner,sun4i-a10-mod0-clk";
 290                         reg = <0x01c200a8 0x4>;
 291                         clocks = <&osc24M>, <&pll6 0>;
 292                         clock-output-names = "spi2";
 293                 };
 294
 295                 spi3_clk: clk@01c200ac {
 296                         #clock-cells = <0>;
 297                         compatible = "allwinner,sun4i-a10-mod0-clk";
 298                         reg = <0x01c200ac 0x4>;
 299                         clocks = <&osc24M>, <&pll6 0>;
 300                         clock-output-names = "spi3";
 301                 };
 302
 303                 usb_clk: clk@01c200cc {
 304                         #clock-cells = <1>;
 305                         #reset-cells = <1>;
 306                         compatible = "allwinner,sun6i-a31-usb-clk";
 307                         reg = <0x01c200cc 0x4>;
 308                         clocks = <&osc24M>;
 309                         clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2",
 310                                              "usb_ohci0", "usb_ohci1",
 311                                              "usb_ohci2";
 312                 };
 313
 314                 /*
 315                  * The following two are dummy clocks, placeholders used in the gmac_tx
 316                  * clock. The gmac driver will choose one parent depending on the PHY
 317                  * interface mode, using clk_set_rate auto-reparenting.
 318                  * The actual TX clock rate is not controlled by the gmac_tx clock.
 319                  */
 320                 mii_phy_tx_clk: clk@1 {
 321                         #clock-cells = <0>;
 322                         compatible = "fixed-clock";
 323                         clock-frequency = <25000000>;
 324                         clock-output-names = "mii_phy_tx";
 325                 };
 326
 327                 gmac_int_tx_clk: clk@2 {
 328                         #clock-cells = <0>;
 329                         compatible = "fixed-clock";
 330                         clock-frequency = <125000000>;
 331                         clock-output-names = "gmac_int_tx";
 332                 };
 333
 334                 gmac_tx_clk: clk@01c200d0 {
 335                         #clock-cells = <0>;
 336                         compatible = "allwinner,sun7i-a20-gmac-clk";
 337                         reg = <0x01c200d0 0x4>;
 338                         clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
 339                         clock-output-names = "gmac_tx";
 340                 };
 341         };
 342
 343         soc@01c00000 {
 344                 compatible = "simple-bus";
 345                 #address-cells = <1>;
 346                 #size-cells = <1>;
 347                 ranges;
 348
 349                 dma: dma-controller@01c02000 {
 350                         compatible = "allwinner,sun6i-a31-dma";
 351                         reg = <0x01c02000 0x1000>;
 352                         interrupts = <0 50 4>;
 353                         clocks = <&ahb1_gates 6>;
 354                         resets = <&ahb1_rst 6>;
 355                         #dma-cells = <1>;
 356
 357                         /* DMA controller requires AHB1 clocked from PLL6 */
 358                         assigned-clocks = <&ahb1_mux>;
 359                         assigned-clock-parents = <&pll6 0>;
 360                 };
 361
 362                 mmc0: mmc@01c0f000 {
 363                         compatible = "allwinner,sun5i-a13-mmc";
 364                         reg = <0x01c0f000 0x1000>;
 365                         clocks = <&ahb1_gates 8>, <&mmc0_clk>;
 366                         clock-names = "ahb", "mmc";
 367                         resets = <&ahb1_rst 8>;
 368                         reset-names = "ahb";
 369                         interrupts = <0 60 4>;
 370                         status = "disabled";
 371                 };
 372
 373                 mmc1: mmc@01c10000 {
 374                         compatible = "allwinner,sun5i-a13-mmc";
 375                         reg = <0x01c10000 0x1000>;
 376                         clocks = <&ahb1_gates 9>, <&mmc1_clk>;
 377                         clock-names = "ahb", "mmc";
 378                         resets = <&ahb1_rst 9>;
 379                         reset-names = "ahb";
 380                         interrupts = <0 61 4>;
 381                         status = "disabled";
 382                 };
 383
 384                 mmc2: mmc@01c11000 {
 385                         compatible = "allwinner,sun5i-a13-mmc";
 386                         reg = <0x01c11000 0x1000>;
 387                         clocks = <&ahb1_gates 10>, <&mmc2_clk>;
 388                         clock-names = "ahb", "mmc";
 389                         resets = <&ahb1_rst 10>;
 390                         reset-names = "ahb";
 391                         interrupts = <0 62 4>;
 392                         status = "disabled";
 393                 };
 394
 395                 mmc3: mmc@01c12000 {
 396                         compatible = "allwinner,sun5i-a13-mmc";
 397                         reg = <0x01c12000 0x1000>;
 398                         clocks = <&ahb1_gates 11>, <&mmc3_clk>;
 399                         clock-names = "ahb", "mmc";
 400                         resets = <&ahb1_rst 11>;
 401                         reset-names = "ahb";
 402                         interrupts = <0 63 4>;
 403                         status = "disabled";
 404                 };
 405
 406                 usbphy: phy@01c19400 {
 407                         compatible = "allwinner,sun6i-a31-usb-phy";
 408                         reg = <0x01c19400 0x10>,
 409                               <0x01c1a800 0x4>,
 410                               <0x01c1b800 0x4>;
 411                         reg-names = "phy_ctrl",
 412                                     "pmu1",
 413                                     "pmu2";
 414                         clocks = <&usb_clk 8>,
 415                                  <&usb_clk 9>,
 416                                  <&usb_clk 10>;
 417                         clock-names = "usb0_phy",
 418                                       "usb1_phy",
 419                                       "usb2_phy";
 420                         resets = <&usb_clk 0>,
 421                                  <&usb_clk 1>,
 422                                  <&usb_clk 2>;
 423                         reset-names = "usb0_reset",
 424                                       "usb1_reset",
 425                                       "usb2_reset";
 426                         status = "disabled";
 427                         #phy-cells = <1>;
 428                 };
 429
 430                 ehci0: usb@01c1a000 {
 431                         compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
 432                         reg = <0x01c1a000 0x100>;
 433                         interrupts = <0 72 4>;
 434                         clocks = <&ahb1_gates 26>;
 435                         resets = <&ahb1_rst 26>;
 436                         phys = <&usbphy 1>;
 437                         phy-names = "usb";
 438                         status = "disabled";
 439                 };
 440
 441                 ohci0: usb@01c1a400 {
 442                         compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
 443                         reg = <0x01c1a400 0x100>;
 444                         interrupts = <0 73 4>;
 445                         clocks = <&ahb1_gates 29>, <&usb_clk 16>;
 446                         resets = <&ahb1_rst 29>;
 447                         phys = <&usbphy 1>;
 448                         phy-names = "usb";
 449                         status = "disabled";
 450                 };
 451
 452                 ehci1: usb@01c1b000 {
 453                         compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
 454                         reg = <0x01c1b000 0x100>;
 455                         interrupts = <0 74 4>;
 456                         clocks = <&ahb1_gates 27>;
 457                         resets = <&ahb1_rst 27>;
 458                         phys = <&usbphy 2>;
 459                         phy-names = "usb";
 460                         status = "disabled";
 461                 };
 462
 463                 ohci1: usb@01c1b400 {
 464                         compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
 465                         reg = <0x01c1b400 0x100>;
 466                         interrupts = <0 75 4>;
 467                         clocks = <&ahb1_gates 30>, <&usb_clk 17>;
 468                         resets = <&ahb1_rst 30>;
 469                         phys = <&usbphy 2>;
 470                         phy-names = "usb";
 471                         status = "disabled";
 472                 };
 473
 474                 ohci2: usb@01c1c400 {
 475                         compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
 476                         reg = <0x01c1c400 0x100>;
 477                         interrupts = <0 77 4>;
 478                         clocks = <&ahb1_gates 31>, <&usb_clk 18>;
 479                         resets = <&ahb1_rst 31>;
 480                         status = "disabled";
 481                 };
 482
 483                 pio: pinctrl@01c20800 {
 484                         compatible = "allwinner,sun6i-a31-pinctrl";
 485                         reg = <0x01c20800 0x400>;
 486                         interrupts = <0 11 4>,
 487                                      <0 15 4>,
 488                                      <0 16 4>,
 489                                      <0 17 4>;
 490                         clocks = <&apb1_gates 5>;
 491                         gpio-controller;
 492                         interrupt-controller;
 493                         #interrupt-cells = <2>;
 494                         #size-cells = <0>;
 495                         #gpio-cells = <3>;
 496
 497                         uart0_pins_a: uart0@0 {
 498                                 allwinner,pins = "PH20", "PH21";
 499                                 allwinner,function = "uart0";
 500                                 allwinner,drive = <0>;
 501                                 allwinner,pull = <0>;
 502                         };
 503
 504                         i2c0_pins_a: i2c0@0 {
 505                                 allwinner,pins = "PH14", "PH15";
 506                                 allwinner,function = "i2c0";
 507                                 allwinner,drive = <0>;
 508                                 allwinner,pull = <0>;
 509                         };
 510
 511                         i2c1_pins_a: i2c1@0 {
 512                                 allwinner,pins = "PH16", "PH17";
 513                                 allwinner,function = "i2c1";
 514                                 allwinner,drive = <0>;
 515                                 allwinner,pull = <0>;
 516                         };
 517
 518                         i2c2_pins_a: i2c2@0 {
 519                                 allwinner,pins = "PH18", "PH19";
 520                                 allwinner,function = "i2c2";
 521                                 allwinner,drive = <0>;
 522                                 allwinner,pull = <0>;
 523                         };
 524
 525                         mmc0_pins_a: mmc0@0 {
 526                                 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
 527                                 allwinner,function = "mmc0";
 528                                 allwinner,drive = <2>;
 529                                 allwinner,pull = <0>;
 530                         };
 531
 532                         gmac_pins_mii_a: gmac_mii@0 {
 533                                 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
 534                                                 "PA8", "PA9", "PA11",
 535                                                 "PA12", "PA13", "PA14", "PA19",
 536                                                 "PA20", "PA21", "PA22", "PA23",
 537                                                 "PA24", "PA26", "PA27";
 538                                 allwinner,function = "gmac";
 539                                 allwinner,drive = <0>;
 540                                 allwinner,pull = <0>;
 541                         };
 542
 543                         gmac_pins_gmii_a: gmac_gmii@0 {
 544                                 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
 545                                                 "PA4", "PA5", "PA6", "PA7",
 546                                                 "PA8", "PA9", "PA10", "PA11",
 547                                                 "PA12", "PA13", "PA14", "PA15",
 548                                                 "PA16", "PA17", "PA18", "PA19",
 549                                                 "PA20", "PA21", "PA22", "PA23",
 550                                                 "PA24", "PA25", "PA26", "PA27";
 551                                 allwinner,function = "gmac";
 552                                 /*
 553                                  * data lines in GMII mode run at 125MHz and
 554                                  * might need a higher signal drive strength
 555                                  */
 556                                 allwinner,drive = <2>;
 557                                 allwinner,pull = <0>;
 558                         };
 559
 560                         gmac_pins_rgmii_a: gmac_rgmii@0 {
 561                                 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
 562                                                 "PA9", "PA10", "PA11",
 563                                                 "PA12", "PA13", "PA14", "PA19",
 564                                                 "PA20", "PA25", "PA26", "PA27";
 565                                 allwinner,function = "gmac";
 566                                 /*
 567                                  * data lines in RGMII mode use DDR mode
 568                                  * and need a higher signal drive strength
 569                                  */
 570                                 allwinner,drive = <3>;
 571                                 allwinner,pull = <0>;
 572                         };
 573                 };
 574
 575                 ahb1_rst: reset@01c202c0 {
 576                         #reset-cells = <1>;
 577                         compatible = "allwinner,sun6i-a31-ahb1-reset";
 578                         reg = <0x01c202c0 0xc>;
 579                 };
 580
 581                 apb1_rst: reset@01c202d0 {
 582                         #reset-cells = <1>;
 583                         compatible = "allwinner,sun6i-a31-clock-reset";
 584                         reg = <0x01c202d0 0x4>;
 585                 };
 586
 587                 apb2_rst: reset@01c202d8 {
 588                         #reset-cells = <1>;
 589                         compatible = "allwinner,sun6i-a31-clock-reset";
 590                         reg = <0x01c202d8 0x4>;
 591                 };
 592
 593                 timer@01c20c00 {
 594                         compatible = "allwinner,sun4i-a10-timer";
 595                         reg = <0x01c20c00 0xa0>;
 596                         interrupts = <0 18 4>,
 597                                      <0 19 4>,
 598                                      <0 20 4>,
 599                                      <0 21 4>,
 600                                      <0 22 4>;
 601                         clocks = <&osc24M>;
 602                 };
 603
 604                 wdt1: watchdog@01c20ca0 {
 605                         compatible = "allwinner,sun6i-a31-wdt";
 606                         reg = <0x01c20ca0 0x20>;
 607                 };
 608
 609                 uart0: serial@01c28000 {
 610                         compatible = "snps,dw-apb-uart";
 611                         reg = <0x01c28000 0x400>;
 612                         interrupts = <0 0 4>;
 613                         reg-shift = <2>;
 614                         reg-io-width = <4>;
 615                         clocks = <&apb2_gates 16>;
 616                         resets = <&apb2_rst 16>;
 617                         dmas = <&dma 6>, <&dma 6>;
 618                         dma-names = "rx", "tx";
 619                         status = "disabled";
 620                 };
 621
 622                 uart1: serial@01c28400 {
 623                         compatible = "snps,dw-apb-uart";
 624                         reg = <0x01c28400 0x400>;
 625                         interrupts = <0 1 4>;
 626                         reg-shift = <2>;
 627                         reg-io-width = <4>;
 628                         clocks = <&apb2_gates 17>;
 629                         resets = <&apb2_rst 17>;
 630                         dmas = <&dma 7>, <&dma 7>;
 631                         dma-names = "rx", "tx";
 632                         status = "disabled";
 633                 };
 634
 635                 uart2: serial@01c28800 {
 636                         compatible = "snps,dw-apb-uart";
 637                         reg = <0x01c28800 0x400>;
 638                         interrupts = <0 2 4>;
 639                         reg-shift = <2>;
 640                         reg-io-width = <4>;
 641                         clocks = <&apb2_gates 18>;
 642                         resets = <&apb2_rst 18>;
 643                         dmas = <&dma 8>, <&dma 8>;
 644                         dma-names = "rx", "tx";
 645                         status = "disabled";
 646                 };
 647
 648                 uart3: serial@01c28c00 {
 649                         compatible = "snps,dw-apb-uart";
 650                         reg = <0x01c28c00 0x400>;
 651                         interrupts = <0 3 4>;
 652                         reg-shift = <2>;
 653                         reg-io-width = <4>;
 654                         clocks = <&apb2_gates 19>;
 655                         resets = <&apb2_rst 19>;
 656                         dmas = <&dma 9>, <&dma 9>;
 657                         dma-names = "rx", "tx";
 658                         status = "disabled";
 659                 };
 660
 661                 uart4: serial@01c29000 {
 662                         compatible = "snps,dw-apb-uart";
 663                         reg = <0x01c29000 0x400>;
 664                         interrupts = <0 4 4>;
 665                         reg-shift = <2>;
 666                         reg-io-width = <4>;
 667                         clocks = <&apb2_gates 20>;
 668                         resets = <&apb2_rst 20>;
 669                         dmas = <&dma 10>, <&dma 10>;
 670                         dma-names = "rx", "tx";
 671                         status = "disabled";
 672                 };
 673
 674                 uart5: serial@01c29400 {
 675                         compatible = "snps,dw-apb-uart";
 676                         reg = <0x01c29400 0x400>;
 677                         interrupts = <0 5 4>;
 678                         reg-shift = <2>;
 679                         reg-io-width = <4>;
 680                         clocks = <&apb2_gates 21>;
 681                         resets = <&apb2_rst 21>;
 682                         dmas = <&dma 22>, <&dma 22>;
 683                         dma-names = "rx", "tx";
 684                         status = "disabled";
 685                 };
 686
 687                 i2c0: i2c@01c2ac00 {
 688                         compatible = "allwinner,sun6i-a31-i2c";
 689                         reg = <0x01c2ac00 0x400>;
 690                         interrupts = <0 6 4>;
 691                         clocks = <&apb2_gates 0>;
 692                         resets = <&apb2_rst 0>;
 693                         status = "disabled";
 694                         #address-cells = <1>;
 695                         #size-cells = <0>;
 696                 };
 697
 698                 i2c1: i2c@01c2b000 {
 699                         compatible = "allwinner,sun6i-a31-i2c";
 700                         reg = <0x01c2b000 0x400>;
 701                         interrupts = <0 7 4>;
 702                         clocks = <&apb2_gates 1>;
 703                         resets = <&apb2_rst 1>;
 704                         status = "disabled";
 705                         #address-cells = <1>;
 706                         #size-cells = <0>;
 707                 };
 708
 709                 i2c2: i2c@01c2b400 {
 710                         compatible = "allwinner,sun6i-a31-i2c";
 711                         reg = <0x01c2b400 0x400>;
 712                         interrupts = <0 8 4>;
 713                         clocks = <&apb2_gates 2>;
 714                         resets = <&apb2_rst 2>;
 715                         status = "disabled";
 716                         #address-cells = <1>;
 717                         #size-cells = <0>;
 718                 };
 719
 720                 i2c3: i2c@01c2b800 {
 721                         compatible = "allwinner,sun6i-a31-i2c";
 722                         reg = <0x01c2b800 0x400>;
 723                         interrupts = <0 9 4>;
 724                         clocks = <&apb2_gates 3>;
 725                         resets = <&apb2_rst 3>;
 726                         status = "disabled";
 727                         #address-cells = <1>;
 728                         #size-cells = <0>;
 729                 };
 730
 731                 gmac: ethernet@01c30000 {
 732                         compatible = "allwinner,sun7i-a20-gmac";
 733                         reg = <0x01c30000 0x1054>;
 734                         interrupts = <0 82 4>;
 735                         interrupt-names = "macirq";
 736                         clocks = <&ahb1_gates 17>, <&gmac_tx_clk>;
 737                         clock-names = "stmmaceth", "allwinner_gmac_tx";
 738                         resets = <&ahb1_rst 17>;
 739                         reset-names = "stmmaceth";
 740                         snps,pbl = <2>;
 741                         snps,fixed-burst;
 742                         snps,force_sf_dma_mode;
 743                         status = "disabled";
 744                         #address-cells = <1>;
 745                         #size-cells = <0>;
 746                 };
 747
 748                 timer@01c60000 {
 749                         compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer";
 750                         reg = <0x01c60000 0x1000>;
 751                         interrupts = <0 51 4>,
 752                                      <0 52 4>,
 753                                      <0 53 4>,
 754                                      <0 54 4>;
 755                         clocks = <&ahb1_gates 19>;
 756                         resets = <&ahb1_rst 19>;
 757                 };
 758
 759                 spi0: spi@01c68000 {
 760                         compatible = "allwinner,sun6i-a31-spi";
 761                         reg = <0x01c68000 0x1000>;
 762                         interrupts = <0 65 4>;
 763                         clocks = <&ahb1_gates 20>, <&spi0_clk>;
 764                         clock-names = "ahb", "mod";
 765                         dmas = <&dma 23>, <&dma 23>;
 766                         dma-names = "rx", "tx";
 767                         resets = <&ahb1_rst 20>;
 768                         status = "disabled";
 769                 };
 770
 771                 spi1: spi@01c69000 {
 772                         compatible = "allwinner,sun6i-a31-spi";
 773                         reg = <0x01c69000 0x1000>;
 774                         interrupts = <0 66 4>;
 775                         clocks = <&ahb1_gates 21>, <&spi1_clk>;
 776                         clock-names = "ahb", "mod";
 777                         dmas = <&dma 24>, <&dma 24>;
 778                         dma-names = "rx", "tx";
 779                         resets = <&ahb1_rst 21>;
 780                         status = "disabled";
 781                 };
 782
 783                 spi2: spi@01c6a000 {
 784                         compatible = "allwinner,sun6i-a31-spi";
 785                         reg = <0x01c6a000 0x1000>;
 786                         interrupts = <0 67 4>;
 787                         clocks = <&ahb1_gates 22>, <&spi2_clk>;
 788                         clock-names = "ahb", "mod";
 789                         dmas = <&dma 25>, <&dma 25>;
 790                         dma-names = "rx", "tx";
 791                         resets = <&ahb1_rst 22>;
 792                         status = "disabled";
 793                 };
 794
 795                 spi3: spi@01c6b000 {
 796                         compatible = "allwinner,sun6i-a31-spi";
 797                         reg = <0x01c6b000 0x1000>;
 798                         interrupts = <0 68 4>;
 799                         clocks = <&ahb1_gates 23>, <&spi3_clk>;
 800                         clock-names = "ahb", "mod";
 801                         dmas = <&dma 26>, <&dma 26>;
 802                         dma-names = "rx", "tx";
 803                         resets = <&ahb1_rst 23>;
 804                         status = "disabled";
 805                 };
 806
 807                 gic: interrupt-controller@01c81000 {
 808                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 809                         reg = <0x01c81000 0x1000>,
 810                               <0x01c82000 0x1000>,
 811                               <0x01c84000 0x2000>,
 812                               <0x01c86000 0x2000>;
 813                         interrupt-controller;
 814                         #interrupt-cells = <3>;
 815                         interrupts = <1 9 0xf04>;
 816                 };
 817
 818                 rtc: rtc@01f00000 {
 819                         compatible = "allwinner,sun6i-a31-rtc";
 820                         reg = <0x01f00000 0x54>;
 821                         interrupts = <0 40 4>, <0 41 4>;
 822                 };
 823
 824                 nmi_intc: interrupt-controller@01f00c0c {
 825                         compatible = "allwinner,sun6i-a31-sc-nmi";
 826                         interrupt-controller;
 827                         #interrupt-cells = <2>;
 828                         reg = <0x01f00c0c 0x38>;
 829                         interrupts = <0 32 4>;
 830                 };
 831
 832                 prcm@01f01400 {
 833                         compatible = "allwinner,sun6i-a31-prcm";
 834                         reg = <0x01f01400 0x200>;
 835
 836                         ar100: ar100_clk {
 837                                 compatible = "allwinner,sun6i-a31-ar100-clk";
 838                                 #clock-cells = <0>;
 839                                 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
 840                                 clock-output-names = "ar100";
 841                         };
 842
 843                         ahb0: ahb0_clk {
 844                                 compatible = "fixed-factor-clock";
 845                                 #clock-cells = <0>;
 846                                 clock-div = <1>;
 847                                 clock-mult = <1>;
 848                                 clocks = <&ar100>;
 849                                 clock-output-names = "ahb0";
 850                         };
 851
 852                         apb0: apb0_clk {
 853                                 compatible = "allwinner,sun6i-a31-apb0-clk";
 854                                 #clock-cells = <0>;
 855                                 clocks = <&ahb0>;
 856                                 clock-output-names = "apb0";
 857                         };
 858
 859                         apb0_gates: apb0_gates_clk {
 860                                 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
 861                                 #clock-cells = <1>;
 862                                 clocks = <&apb0>;
 863                                 clock-output-names = "apb0_pio", "apb0_ir",
 864                                                 "apb0_timer", "apb0_p2wi",
 865                                                 "apb0_uart", "apb0_1wire",
 866                                                 "apb0_i2c";
 867                         };
 868
 869                         apb0_rst: apb0_rst {
 870                                 compatible = "allwinner,sun6i-a31-clock-reset";
 871                                 #reset-cells = <1>;
 872                         };
 873                 };
 874
 875                 cpucfg@01f01c00 {
 876                         compatible = "allwinner,sun6i-a31-cpuconfig";
 877                         reg = <0x01f01c00 0x300>;
 878                 };
 879
 880                 r_pio: pinctrl@01f02c00 {
 881                         compatible = "allwinner,sun6i-a31-r-pinctrl";
 882                         reg = <0x01f02c00 0x400>;
 883                         interrupts = <0 45 4>,
 884                                      <0 46 4>;
 885                         clocks = <&apb0_gates 0>;
 886                         resets = <&apb0_rst 0>;
 887                         gpio-controller;
 888                         interrupt-controller;
 889                         #interrupt-cells = <2>;
 890                         #size-cells = <0>;
 891                         #gpio-cells = <3>;
 892                 };
 893         };
 894 };