2 * Copyright 2013 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
14 /include/ "skeleton.dtsi"
17 interrupt-parent = <&gic>;
30 enable-method = "allwinner,sun6i-a31";
35 compatible = "arm,cortex-a7";
41 compatible = "arm,cortex-a7";
47 compatible = "arm,cortex-a7";
53 compatible = "arm,cortex-a7";
60 reg = <0x40000000 0x80000000>;
64 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
65 interrupts = <0 120 4>,
78 compatible = "fixed-clock";
79 clock-frequency = <24000000>;
84 compatible = "fixed-clock";
85 clock-frequency = <32768>;
86 clock-output-names = "osc32k";
91 compatible = "allwinner,sun6i-a31-pll1-clk";
92 reg = <0x01c20000 0x4>;
94 clock-output-names = "pll1";
99 compatible = "allwinner,sun6i-a31-pll6-clk";
100 reg = <0x01c20028 0x4>;
102 clock-output-names = "pll6";
107 compatible = "allwinner,sun4i-a10-cpu-clk";
108 reg = <0x01c20050 0x4>;
111 * PLL1 is listed twice here.
112 * While it looks suspicious, it's actually documented
113 * that way both in the datasheet and in the code from
116 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
117 clock-output-names = "cpu";
122 compatible = "allwinner,sun4i-a10-axi-clk";
123 reg = <0x01c20050 0x4>;
125 clock-output-names = "axi";
128 ahb1_mux: ahb1_mux@01c20054 {
130 compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
131 reg = <0x01c20054 0x4>;
132 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
133 clock-output-names = "ahb1_mux";
136 ahb1: ahb1@01c20054 {
138 compatible = "allwinner,sun4i-a10-ahb-clk";
139 reg = <0x01c20054 0x4>;
140 clocks = <&ahb1_mux>;
141 clock-output-names = "ahb1";
144 ahb1_gates: clk@01c20060 {
146 compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
147 reg = <0x01c20060 0x8>;
149 clock-output-names = "ahb1_mipidsi", "ahb1_ss",
150 "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
151 "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
152 "ahb1_nand0", "ahb1_sdram",
153 "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
154 "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
155 "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
156 "ahb1_ehci1", "ahb1_ohci0",
157 "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
158 "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
159 "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
160 "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
161 "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
162 "ahb1_drc0", "ahb1_drc1";
165 apb1: apb1@01c20054 {
167 compatible = "allwinner,sun4i-a10-apb0-clk";
168 reg = <0x01c20054 0x4>;
170 clock-output-names = "apb1";
173 apb1_gates: clk@01c20068 {
175 compatible = "allwinner,sun6i-a31-apb1-gates-clk";
176 reg = <0x01c20068 0x4>;
178 clock-output-names = "apb1_codec", "apb1_digital_mic",
179 "apb1_pio", "apb1_daudio0",
183 apb2_mux: apb2_mux@01c20058 {
185 compatible = "allwinner,sun4i-a10-apb1-mux-clk";
186 reg = <0x01c20058 0x4>;
187 clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
188 clock-output-names = "apb2_mux";
191 apb2: apb2@01c20058 {
193 compatible = "allwinner,sun6i-a31-apb2-div-clk";
194 reg = <0x01c20058 0x4>;
195 clocks = <&apb2_mux>;
196 clock-output-names = "apb2";
199 apb2_gates: clk@01c2006c {
201 compatible = "allwinner,sun6i-a31-apb2-gates-clk";
202 reg = <0x01c2006c 0x4>;
204 clock-output-names = "apb2_i2c0", "apb2_i2c1",
205 "apb2_i2c2", "apb2_i2c3", "apb2_uart0",
206 "apb2_uart1", "apb2_uart2", "apb2_uart3",
207 "apb2_uart4", "apb2_uart5";
210 mmc0_clk: clk@01c20088 {
212 compatible = "allwinner,sun4i-a10-mod0-clk";
213 reg = <0x01c20088 0x4>;
214 clocks = <&osc24M>, <&pll6>;
215 clock-output-names = "mmc0";
218 mmc1_clk: clk@01c2008c {
220 compatible = "allwinner,sun4i-a10-mod0-clk";
221 reg = <0x01c2008c 0x4>;
222 clocks = <&osc24M>, <&pll6>;
223 clock-output-names = "mmc1";
226 mmc2_clk: clk@01c20090 {
228 compatible = "allwinner,sun4i-a10-mod0-clk";
229 reg = <0x01c20090 0x4>;
230 clocks = <&osc24M>, <&pll6>;
231 clock-output-names = "mmc2";
234 mmc3_clk: clk@01c20094 {
236 compatible = "allwinner,sun4i-a10-mod0-clk";
237 reg = <0x01c20094 0x4>;
238 clocks = <&osc24M>, <&pll6>;
239 clock-output-names = "mmc3";
242 spi0_clk: clk@01c200a0 {
244 compatible = "allwinner,sun4i-a10-mod0-clk";
245 reg = <0x01c200a0 0x4>;
246 clocks = <&osc24M>, <&pll6>;
247 clock-output-names = "spi0";
250 spi1_clk: clk@01c200a4 {
252 compatible = "allwinner,sun4i-a10-mod0-clk";
253 reg = <0x01c200a4 0x4>;
254 clocks = <&osc24M>, <&pll6>;
255 clock-output-names = "spi1";
258 spi2_clk: clk@01c200a8 {
260 compatible = "allwinner,sun4i-a10-mod0-clk";
261 reg = <0x01c200a8 0x4>;
262 clocks = <&osc24M>, <&pll6>;
263 clock-output-names = "spi2";
266 spi3_clk: clk@01c200ac {
268 compatible = "allwinner,sun4i-a10-mod0-clk";
269 reg = <0x01c200ac 0x4>;
270 clocks = <&osc24M>, <&pll6>;
271 clock-output-names = "spi3";
274 usb_clk: clk@01c200cc {
277 compatible = "allwinner,sun6i-a31-usb-clk";
278 reg = <0x01c200cc 0x4>;
280 clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2",
281 "usb_ohci0", "usb_ohci1",
287 compatible = "simple-bus";
288 #address-cells = <1>;
292 dma: dma-controller@01c02000 {
293 compatible = "allwinner,sun6i-a31-dma";
294 reg = <0x01c02000 0x1000>;
295 interrupts = <0 50 4>;
296 clocks = <&ahb1_gates 6>;
297 resets = <&ahb1_rst 6>;
302 compatible = "allwinner,sun5i-a13-mmc";
303 reg = <0x01c0f000 0x1000>;
304 clocks = <&ahb1_gates 8>, <&mmc0_clk>;
305 clock-names = "ahb", "mmc";
306 resets = <&ahb1_rst 8>;
308 interrupts = <0 60 4>;
313 compatible = "allwinner,sun5i-a13-mmc";
314 reg = <0x01c10000 0x1000>;
315 clocks = <&ahb1_gates 9>, <&mmc1_clk>;
316 clock-names = "ahb", "mmc";
317 resets = <&ahb1_rst 9>;
319 interrupts = <0 61 4>;
324 compatible = "allwinner,sun5i-a13-mmc";
325 reg = <0x01c11000 0x1000>;
326 clocks = <&ahb1_gates 10>, <&mmc2_clk>;
327 clock-names = "ahb", "mmc";
328 resets = <&ahb1_rst 10>;
330 interrupts = <0 62 4>;
335 compatible = "allwinner,sun5i-a13-mmc";
336 reg = <0x01c12000 0x1000>;
337 clocks = <&ahb1_gates 11>, <&mmc3_clk>;
338 clock-names = "ahb", "mmc";
339 resets = <&ahb1_rst 11>;
341 interrupts = <0 63 4>;
345 usbphy: phy@01c19400 {
346 compatible = "allwinner,sun6i-a31-usb-phy";
347 reg = <0x01c19400 0x10>,
350 reg-names = "phy_ctrl",
353 clocks = <&usb_clk 8>,
356 clock-names = "usb0_phy",
359 resets = <&usb_clk 0>,
362 reset-names = "usb0_reset",
369 ehci0: usb@01c1a000 {
370 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
371 reg = <0x01c1a000 0x100>;
372 interrupts = <0 72 4>;
373 clocks = <&ahb1_gates 26>;
374 resets = <&ahb1_rst 26>;
380 ohci0: usb@01c1a400 {
381 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
382 reg = <0x01c1a400 0x100>;
383 interrupts = <0 73 4>;
384 clocks = <&ahb1_gates 29>, <&usb_clk 16>;
385 resets = <&ahb1_rst 29>;
391 ehci1: usb@01c1b000 {
392 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
393 reg = <0x01c1b000 0x100>;
394 interrupts = <0 74 4>;
395 clocks = <&ahb1_gates 27>;
396 resets = <&ahb1_rst 27>;
402 ohci1: usb@01c1b400 {
403 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
404 reg = <0x01c1b400 0x100>;
405 interrupts = <0 75 4>;
406 clocks = <&ahb1_gates 30>, <&usb_clk 17>;
407 resets = <&ahb1_rst 30>;
413 ohci2: usb@01c1c400 {
414 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
415 reg = <0x01c1c400 0x100>;
416 interrupts = <0 77 4>;
417 clocks = <&ahb1_gates 31>, <&usb_clk 18>;
418 resets = <&ahb1_rst 31>;
422 pio: pinctrl@01c20800 {
423 compatible = "allwinner,sun6i-a31-pinctrl";
424 reg = <0x01c20800 0x400>;
425 interrupts = <0 11 4>,
429 clocks = <&apb1_gates 5>;
431 interrupt-controller;
432 #address-cells = <1>;
436 uart0_pins_a: uart0@0 {
437 allwinner,pins = "PH20", "PH21";
438 allwinner,function = "uart0";
439 allwinner,drive = <0>;
440 allwinner,pull = <0>;
443 i2c0_pins_a: i2c0@0 {
444 allwinner,pins = "PH14", "PH15";
445 allwinner,function = "i2c0";
446 allwinner,drive = <0>;
447 allwinner,pull = <0>;
450 i2c1_pins_a: i2c1@0 {
451 allwinner,pins = "PH16", "PH17";
452 allwinner,function = "i2c1";
453 allwinner,drive = <0>;
454 allwinner,pull = <0>;
457 i2c2_pins_a: i2c2@0 {
458 allwinner,pins = "PH18", "PH19";
459 allwinner,function = "i2c2";
460 allwinner,drive = <0>;
461 allwinner,pull = <0>;
464 mmc0_pins_a: mmc0@0 {
465 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
466 allwinner,function = "mmc0";
467 allwinner,drive = <2>;
468 allwinner,pull = <0>;
472 ahb1_rst: reset@01c202c0 {
474 compatible = "allwinner,sun6i-a31-ahb1-reset";
475 reg = <0x01c202c0 0xc>;
478 apb1_rst: reset@01c202d0 {
480 compatible = "allwinner,sun6i-a31-clock-reset";
481 reg = <0x01c202d0 0x4>;
484 apb2_rst: reset@01c202d8 {
486 compatible = "allwinner,sun6i-a31-clock-reset";
487 reg = <0x01c202d8 0x4>;
491 compatible = "allwinner,sun4i-a10-timer";
492 reg = <0x01c20c00 0xa0>;
493 interrupts = <0 18 4>,
501 wdt1: watchdog@01c20ca0 {
502 compatible = "allwinner,sun6i-a31-wdt";
503 reg = <0x01c20ca0 0x20>;
506 uart0: serial@01c28000 {
507 compatible = "snps,dw-apb-uart";
508 reg = <0x01c28000 0x400>;
509 interrupts = <0 0 4>;
512 clocks = <&apb2_gates 16>;
513 resets = <&apb2_rst 16>;
514 dmas = <&dma 6>, <&dma 6>;
515 dma-names = "rx", "tx";
519 uart1: serial@01c28400 {
520 compatible = "snps,dw-apb-uart";
521 reg = <0x01c28400 0x400>;
522 interrupts = <0 1 4>;
525 clocks = <&apb2_gates 17>;
526 resets = <&apb2_rst 17>;
527 dmas = <&dma 7>, <&dma 7>;
528 dma-names = "rx", "tx";
532 uart2: serial@01c28800 {
533 compatible = "snps,dw-apb-uart";
534 reg = <0x01c28800 0x400>;
535 interrupts = <0 2 4>;
538 clocks = <&apb2_gates 18>;
539 resets = <&apb2_rst 18>;
540 dmas = <&dma 8>, <&dma 8>;
541 dma-names = "rx", "tx";
545 uart3: serial@01c28c00 {
546 compatible = "snps,dw-apb-uart";
547 reg = <0x01c28c00 0x400>;
548 interrupts = <0 3 4>;
551 clocks = <&apb2_gates 19>;
552 resets = <&apb2_rst 19>;
553 dmas = <&dma 9>, <&dma 9>;
554 dma-names = "rx", "tx";
558 uart4: serial@01c29000 {
559 compatible = "snps,dw-apb-uart";
560 reg = <0x01c29000 0x400>;
561 interrupts = <0 4 4>;
564 clocks = <&apb2_gates 20>;
565 resets = <&apb2_rst 20>;
566 dmas = <&dma 10>, <&dma 10>;
567 dma-names = "rx", "tx";
571 uart5: serial@01c29400 {
572 compatible = "snps,dw-apb-uart";
573 reg = <0x01c29400 0x400>;
574 interrupts = <0 5 4>;
577 clocks = <&apb2_gates 21>;
578 resets = <&apb2_rst 21>;
579 dmas = <&dma 22>, <&dma 22>;
580 dma-names = "rx", "tx";
585 compatible = "allwinner,sun6i-a31-i2c";
586 reg = <0x01c2ac00 0x400>;
587 interrupts = <0 6 4>;
588 clocks = <&apb2_gates 0>;
589 clock-frequency = <100000>;
590 resets = <&apb2_rst 0>;
595 compatible = "allwinner,sun6i-a31-i2c";
596 reg = <0x01c2b000 0x400>;
597 interrupts = <0 7 4>;
598 clocks = <&apb2_gates 1>;
599 clock-frequency = <100000>;
600 resets = <&apb2_rst 1>;
605 compatible = "allwinner,sun6i-a31-i2c";
606 reg = <0x01c2b400 0x400>;
607 interrupts = <0 8 4>;
608 clocks = <&apb2_gates 2>;
609 clock-frequency = <100000>;
610 resets = <&apb2_rst 2>;
615 compatible = "allwinner,sun6i-a31-i2c";
616 reg = <0x01c2b800 0x400>;
617 interrupts = <0 9 4>;
618 clocks = <&apb2_gates 3>;
619 clock-frequency = <100000>;
620 resets = <&apb2_rst 3>;
625 compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer";
626 reg = <0x01c60000 0x1000>;
627 interrupts = <0 51 4>,
631 clocks = <&ahb1_gates 19>;
632 resets = <&ahb1_rst 19>;
636 compatible = "allwinner,sun6i-a31-spi";
637 reg = <0x01c68000 0x1000>;
638 interrupts = <0 65 4>;
639 clocks = <&ahb1_gates 20>, <&spi0_clk>;
640 clock-names = "ahb", "mod";
641 dmas = <&dma 23>, <&dma 23>;
642 dma-names = "rx", "tx";
643 resets = <&ahb1_rst 20>;
648 compatible = "allwinner,sun6i-a31-spi";
649 reg = <0x01c69000 0x1000>;
650 interrupts = <0 66 4>;
651 clocks = <&ahb1_gates 21>, <&spi1_clk>;
652 clock-names = "ahb", "mod";
653 dmas = <&dma 24>, <&dma 24>;
654 dma-names = "rx", "tx";
655 resets = <&ahb1_rst 21>;
660 compatible = "allwinner,sun6i-a31-spi";
661 reg = <0x01c6a000 0x1000>;
662 interrupts = <0 67 4>;
663 clocks = <&ahb1_gates 22>, <&spi2_clk>;
664 clock-names = "ahb", "mod";
665 dmas = <&dma 25>, <&dma 25>;
666 dma-names = "rx", "tx";
667 resets = <&ahb1_rst 22>;
672 compatible = "allwinner,sun6i-a31-spi";
673 reg = <0x01c6b000 0x1000>;
674 interrupts = <0 68 4>;
675 clocks = <&ahb1_gates 23>, <&spi3_clk>;
676 clock-names = "ahb", "mod";
677 dmas = <&dma 26>, <&dma 26>;
678 dma-names = "rx", "tx";
679 resets = <&ahb1_rst 23>;
683 gic: interrupt-controller@01c81000 {
684 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
685 reg = <0x01c81000 0x1000>,
689 interrupt-controller;
690 #interrupt-cells = <3>;
691 interrupts = <1 9 0xf04>;
694 nmi_intc: interrupt-controller@01f00c0c {
695 compatible = "allwinner,sun6i-a31-sc-nmi";
696 interrupt-controller;
697 #interrupt-cells = <2>;
698 reg = <0x01f00c0c 0x38>;
699 interrupts = <0 32 4>;
703 compatible = "allwinner,sun6i-a31-prcm";
704 reg = <0x01f01400 0x200>;
707 compatible = "allwinner,sun6i-a31-ar100-clk";
709 clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
710 clock-output-names = "ar100";
714 compatible = "fixed-factor-clock";
719 clock-output-names = "ahb0";
723 compatible = "allwinner,sun6i-a31-apb0-clk";
726 clock-output-names = "apb0";
729 apb0_gates: apb0_gates_clk {
730 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
733 clock-output-names = "apb0_pio", "apb0_ir",
734 "apb0_timer", "apb0_p2wi",
735 "apb0_uart", "apb0_1wire",
740 compatible = "allwinner,sun6i-a31-clock-reset";
746 compatible = "allwinner,sun6i-a31-cpuconfig";
747 reg = <0x01f01c00 0x300>;
750 r_pio: pinctrl@01f02c00 {
751 compatible = "allwinner,sun6i-a31-r-pinctrl";
752 reg = <0x01f02c00 0x400>;
753 interrupts = <0 45 4>,
755 clocks = <&apb0_gates 0>;
756 resets = <&apb0_rst 0>;
758 interrupt-controller;
759 #address-cells = <1>;