2 * Copyright 2013 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
50 /include/ "skeleton.dtsi"
53 interrupt-parent = <&gic>;
71 compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
72 allwinner,pipeline = "de_be0-lcd0-hdmi";
79 enable-method = "allwinner,sun6i-a31";
84 compatible = "arm,cortex-a7";
90 compatible = "arm,cortex-a7";
96 compatible = "arm,cortex-a7";
102 compatible = "arm,cortex-a7";
109 reg = <0x40000000 0x80000000>;
113 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
114 interrupts = <0 120 4>,
121 #address-cells = <1>;
127 compatible = "fixed-clock";
128 clock-frequency = <24000000>;
133 compatible = "fixed-clock";
134 clock-frequency = <32768>;
135 clock-output-names = "osc32k";
140 compatible = "allwinner,sun6i-a31-pll1-clk";
141 reg = <0x01c20000 0x4>;
143 clock-output-names = "pll1";
148 compatible = "allwinner,sun6i-a31-pll6-clk";
149 reg = <0x01c20028 0x4>;
151 clock-output-names = "pll6", "pll6x2";
156 compatible = "allwinner,sun4i-a10-cpu-clk";
157 reg = <0x01c20050 0x4>;
160 * PLL1 is listed twice here.
161 * While it looks suspicious, it's actually documented
162 * that way both in the datasheet and in the code from
165 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
166 clock-output-names = "cpu";
171 compatible = "allwinner,sun4i-a10-axi-clk";
172 reg = <0x01c20050 0x4>;
174 clock-output-names = "axi";
177 ahb1_mux: ahb1_mux@01c20054 {
179 compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
180 reg = <0x01c20054 0x4>;
181 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
182 clock-output-names = "ahb1_mux";
185 ahb1: ahb1@01c20054 {
187 compatible = "allwinner,sun4i-a10-ahb-clk";
188 reg = <0x01c20054 0x4>;
189 clocks = <&ahb1_mux>;
190 clock-output-names = "ahb1";
193 ahb1_gates: clk@01c20060 {
195 compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
196 reg = <0x01c20060 0x8>;
198 clock-output-names = "ahb1_mipidsi", "ahb1_ss",
199 "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
200 "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
201 "ahb1_nand0", "ahb1_sdram",
202 "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
203 "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
204 "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
205 "ahb1_ehci1", "ahb1_ohci0",
206 "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
207 "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
208 "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
209 "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
210 "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
211 "ahb1_drc0", "ahb1_drc1";
214 apb1: apb1@01c20054 {
216 compatible = "allwinner,sun4i-a10-apb0-clk";
217 reg = <0x01c20054 0x4>;
219 clock-output-names = "apb1";
222 apb1_gates: clk@01c20068 {
224 compatible = "allwinner,sun6i-a31-apb1-gates-clk";
225 reg = <0x01c20068 0x4>;
227 clock-output-names = "apb1_codec", "apb1_digital_mic",
228 "apb1_pio", "apb1_daudio0",
234 compatible = "allwinner,sun4i-a10-apb1-clk";
235 reg = <0x01c20058 0x4>;
236 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
237 clock-output-names = "apb2";
240 apb2_gates: clk@01c2006c {
242 compatible = "allwinner,sun6i-a31-apb2-gates-clk";
243 reg = <0x01c2006c 0x4>;
245 clock-output-names = "apb2_i2c0", "apb2_i2c1",
246 "apb2_i2c2", "apb2_i2c3", "apb2_uart0",
247 "apb2_uart1", "apb2_uart2", "apb2_uart3",
248 "apb2_uart4", "apb2_uart5";
251 mmc0_clk: clk@01c20088 {
253 compatible = "allwinner,sun4i-a10-mod0-clk";
254 reg = <0x01c20088 0x4>;
255 clocks = <&osc24M>, <&pll6 0>;
256 clock-output-names = "mmc0";
259 mmc1_clk: clk@01c2008c {
261 compatible = "allwinner,sun4i-a10-mod0-clk";
262 reg = <0x01c2008c 0x4>;
263 clocks = <&osc24M>, <&pll6 0>;
264 clock-output-names = "mmc1";
267 mmc2_clk: clk@01c20090 {
269 compatible = "allwinner,sun4i-a10-mod0-clk";
270 reg = <0x01c20090 0x4>;
271 clocks = <&osc24M>, <&pll6 0>;
272 clock-output-names = "mmc2";
275 mmc3_clk: clk@01c20094 {
277 compatible = "allwinner,sun4i-a10-mod0-clk";
278 reg = <0x01c20094 0x4>;
279 clocks = <&osc24M>, <&pll6 0>;
280 clock-output-names = "mmc3";
283 spi0_clk: clk@01c200a0 {
285 compatible = "allwinner,sun4i-a10-mod0-clk";
286 reg = <0x01c200a0 0x4>;
287 clocks = <&osc24M>, <&pll6 0>;
288 clock-output-names = "spi0";
291 spi1_clk: clk@01c200a4 {
293 compatible = "allwinner,sun4i-a10-mod0-clk";
294 reg = <0x01c200a4 0x4>;
295 clocks = <&osc24M>, <&pll6 0>;
296 clock-output-names = "spi1";
299 spi2_clk: clk@01c200a8 {
301 compatible = "allwinner,sun4i-a10-mod0-clk";
302 reg = <0x01c200a8 0x4>;
303 clocks = <&osc24M>, <&pll6 0>;
304 clock-output-names = "spi2";
307 spi3_clk: clk@01c200ac {
309 compatible = "allwinner,sun4i-a10-mod0-clk";
310 reg = <0x01c200ac 0x4>;
311 clocks = <&osc24M>, <&pll6 0>;
312 clock-output-names = "spi3";
315 usb_clk: clk@01c200cc {
318 compatible = "allwinner,sun6i-a31-usb-clk";
319 reg = <0x01c200cc 0x4>;
321 clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2",
322 "usb_ohci0", "usb_ohci1",
327 * The following two are dummy clocks, placeholders used in the gmac_tx
328 * clock. The gmac driver will choose one parent depending on the PHY
329 * interface mode, using clk_set_rate auto-reparenting.
330 * The actual TX clock rate is not controlled by the gmac_tx clock.
332 mii_phy_tx_clk: clk@1 {
334 compatible = "fixed-clock";
335 clock-frequency = <25000000>;
336 clock-output-names = "mii_phy_tx";
339 gmac_int_tx_clk: clk@2 {
341 compatible = "fixed-clock";
342 clock-frequency = <125000000>;
343 clock-output-names = "gmac_int_tx";
346 gmac_tx_clk: clk@01c200d0 {
348 compatible = "allwinner,sun7i-a20-gmac-clk";
349 reg = <0x01c200d0 0x4>;
350 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
351 clock-output-names = "gmac_tx";
356 compatible = "simple-bus";
357 #address-cells = <1>;
361 dma: dma-controller@01c02000 {
362 compatible = "allwinner,sun6i-a31-dma";
363 reg = <0x01c02000 0x1000>;
364 interrupts = <0 50 4>;
365 clocks = <&ahb1_gates 6>;
366 resets = <&ahb1_rst 6>;
369 /* DMA controller requires AHB1 clocked from PLL6 */
370 assigned-clocks = <&ahb1_mux>;
371 assigned-clock-parents = <&pll6 0>;
375 compatible = "allwinner,sun5i-a13-mmc";
376 reg = <0x01c0f000 0x1000>;
377 clocks = <&ahb1_gates 8>, <&mmc0_clk>;
378 clock-names = "ahb", "mmc";
379 resets = <&ahb1_rst 8>;
381 interrupts = <0 60 4>;
386 compatible = "allwinner,sun5i-a13-mmc";
387 reg = <0x01c10000 0x1000>;
388 clocks = <&ahb1_gates 9>, <&mmc1_clk>;
389 clock-names = "ahb", "mmc";
390 resets = <&ahb1_rst 9>;
392 interrupts = <0 61 4>;
397 compatible = "allwinner,sun5i-a13-mmc";
398 reg = <0x01c11000 0x1000>;
399 clocks = <&ahb1_gates 10>, <&mmc2_clk>;
400 clock-names = "ahb", "mmc";
401 resets = <&ahb1_rst 10>;
403 interrupts = <0 62 4>;
408 compatible = "allwinner,sun5i-a13-mmc";
409 reg = <0x01c12000 0x1000>;
410 clocks = <&ahb1_gates 11>, <&mmc3_clk>;
411 clock-names = "ahb", "mmc";
412 resets = <&ahb1_rst 11>;
414 interrupts = <0 63 4>;
418 usbphy: phy@01c19400 {
419 compatible = "allwinner,sun6i-a31-usb-phy";
420 reg = <0x01c19400 0x10>,
423 reg-names = "phy_ctrl",
426 clocks = <&usb_clk 8>,
429 clock-names = "usb0_phy",
432 resets = <&usb_clk 0>,
435 reset-names = "usb0_reset",
442 ehci0: usb@01c1a000 {
443 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
444 reg = <0x01c1a000 0x100>;
445 interrupts = <0 72 4>;
446 clocks = <&ahb1_gates 26>;
447 resets = <&ahb1_rst 26>;
453 ohci0: usb@01c1a400 {
454 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
455 reg = <0x01c1a400 0x100>;
456 interrupts = <0 73 4>;
457 clocks = <&ahb1_gates 29>, <&usb_clk 16>;
458 resets = <&ahb1_rst 29>;
464 ehci1: usb@01c1b000 {
465 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
466 reg = <0x01c1b000 0x100>;
467 interrupts = <0 74 4>;
468 clocks = <&ahb1_gates 27>;
469 resets = <&ahb1_rst 27>;
475 ohci1: usb@01c1b400 {
476 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
477 reg = <0x01c1b400 0x100>;
478 interrupts = <0 75 4>;
479 clocks = <&ahb1_gates 30>, <&usb_clk 17>;
480 resets = <&ahb1_rst 30>;
486 ohci2: usb@01c1c400 {
487 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
488 reg = <0x01c1c400 0x100>;
489 interrupts = <0 77 4>;
490 clocks = <&ahb1_gates 31>, <&usb_clk 18>;
491 resets = <&ahb1_rst 31>;
495 pio: pinctrl@01c20800 {
496 compatible = "allwinner,sun6i-a31-pinctrl";
497 reg = <0x01c20800 0x400>;
498 interrupts = <0 11 4>,
502 clocks = <&apb1_gates 5>;
504 interrupt-controller;
505 #interrupt-cells = <2>;
509 uart0_pins_a: uart0@0 {
510 allwinner,pins = "PH20", "PH21";
511 allwinner,function = "uart0";
512 allwinner,drive = <0>;
513 allwinner,pull = <0>;
516 i2c0_pins_a: i2c0@0 {
517 allwinner,pins = "PH14", "PH15";
518 allwinner,function = "i2c0";
519 allwinner,drive = <0>;
520 allwinner,pull = <0>;
523 i2c1_pins_a: i2c1@0 {
524 allwinner,pins = "PH16", "PH17";
525 allwinner,function = "i2c1";
526 allwinner,drive = <0>;
527 allwinner,pull = <0>;
530 i2c2_pins_a: i2c2@0 {
531 allwinner,pins = "PH18", "PH19";
532 allwinner,function = "i2c2";
533 allwinner,drive = <0>;
534 allwinner,pull = <0>;
537 mmc0_pins_a: mmc0@0 {
538 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
539 allwinner,function = "mmc0";
540 allwinner,drive = <2>;
541 allwinner,pull = <0>;
544 gmac_pins_mii_a: gmac_mii@0 {
545 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
546 "PA8", "PA9", "PA11",
547 "PA12", "PA13", "PA14", "PA19",
548 "PA20", "PA21", "PA22", "PA23",
549 "PA24", "PA26", "PA27";
550 allwinner,function = "gmac";
551 allwinner,drive = <0>;
552 allwinner,pull = <0>;
555 gmac_pins_gmii_a: gmac_gmii@0 {
556 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
557 "PA4", "PA5", "PA6", "PA7",
558 "PA8", "PA9", "PA10", "PA11",
559 "PA12", "PA13", "PA14", "PA15",
560 "PA16", "PA17", "PA18", "PA19",
561 "PA20", "PA21", "PA22", "PA23",
562 "PA24", "PA25", "PA26", "PA27";
563 allwinner,function = "gmac";
565 * data lines in GMII mode run at 125MHz and
566 * might need a higher signal drive strength
568 allwinner,drive = <2>;
569 allwinner,pull = <0>;
572 gmac_pins_rgmii_a: gmac_rgmii@0 {
573 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
574 "PA9", "PA10", "PA11",
575 "PA12", "PA13", "PA14", "PA19",
576 "PA20", "PA25", "PA26", "PA27";
577 allwinner,function = "gmac";
579 * data lines in RGMII mode use DDR mode
580 * and need a higher signal drive strength
582 allwinner,drive = <3>;
583 allwinner,pull = <0>;
587 ahb1_rst: reset@01c202c0 {
589 compatible = "allwinner,sun6i-a31-ahb1-reset";
590 reg = <0x01c202c0 0xc>;
593 apb1_rst: reset@01c202d0 {
595 compatible = "allwinner,sun6i-a31-clock-reset";
596 reg = <0x01c202d0 0x4>;
599 apb2_rst: reset@01c202d8 {
601 compatible = "allwinner,sun6i-a31-clock-reset";
602 reg = <0x01c202d8 0x4>;
606 compatible = "allwinner,sun4i-a10-timer";
607 reg = <0x01c20c00 0xa0>;
608 interrupts = <0 18 4>,
616 wdt1: watchdog@01c20ca0 {
617 compatible = "allwinner,sun6i-a31-wdt";
618 reg = <0x01c20ca0 0x20>;
621 uart0: serial@01c28000 {
622 compatible = "snps,dw-apb-uart";
623 reg = <0x01c28000 0x400>;
624 interrupts = <0 0 4>;
627 clocks = <&apb2_gates 16>;
628 resets = <&apb2_rst 16>;
629 dmas = <&dma 6>, <&dma 6>;
630 dma-names = "rx", "tx";
634 uart1: serial@01c28400 {
635 compatible = "snps,dw-apb-uart";
636 reg = <0x01c28400 0x400>;
637 interrupts = <0 1 4>;
640 clocks = <&apb2_gates 17>;
641 resets = <&apb2_rst 17>;
642 dmas = <&dma 7>, <&dma 7>;
643 dma-names = "rx", "tx";
647 uart2: serial@01c28800 {
648 compatible = "snps,dw-apb-uart";
649 reg = <0x01c28800 0x400>;
650 interrupts = <0 2 4>;
653 clocks = <&apb2_gates 18>;
654 resets = <&apb2_rst 18>;
655 dmas = <&dma 8>, <&dma 8>;
656 dma-names = "rx", "tx";
660 uart3: serial@01c28c00 {
661 compatible = "snps,dw-apb-uart";
662 reg = <0x01c28c00 0x400>;
663 interrupts = <0 3 4>;
666 clocks = <&apb2_gates 19>;
667 resets = <&apb2_rst 19>;
668 dmas = <&dma 9>, <&dma 9>;
669 dma-names = "rx", "tx";
673 uart4: serial@01c29000 {
674 compatible = "snps,dw-apb-uart";
675 reg = <0x01c29000 0x400>;
676 interrupts = <0 4 4>;
679 clocks = <&apb2_gates 20>;
680 resets = <&apb2_rst 20>;
681 dmas = <&dma 10>, <&dma 10>;
682 dma-names = "rx", "tx";
686 uart5: serial@01c29400 {
687 compatible = "snps,dw-apb-uart";
688 reg = <0x01c29400 0x400>;
689 interrupts = <0 5 4>;
692 clocks = <&apb2_gates 21>;
693 resets = <&apb2_rst 21>;
694 dmas = <&dma 22>, <&dma 22>;
695 dma-names = "rx", "tx";
700 compatible = "allwinner,sun6i-a31-i2c";
701 reg = <0x01c2ac00 0x400>;
702 interrupts = <0 6 4>;
703 clocks = <&apb2_gates 0>;
704 resets = <&apb2_rst 0>;
706 #address-cells = <1>;
711 compatible = "allwinner,sun6i-a31-i2c";
712 reg = <0x01c2b000 0x400>;
713 interrupts = <0 7 4>;
714 clocks = <&apb2_gates 1>;
715 resets = <&apb2_rst 1>;
717 #address-cells = <1>;
722 compatible = "allwinner,sun6i-a31-i2c";
723 reg = <0x01c2b400 0x400>;
724 interrupts = <0 8 4>;
725 clocks = <&apb2_gates 2>;
726 resets = <&apb2_rst 2>;
728 #address-cells = <1>;
733 compatible = "allwinner,sun6i-a31-i2c";
734 reg = <0x01c2b800 0x400>;
735 interrupts = <0 9 4>;
736 clocks = <&apb2_gates 3>;
737 resets = <&apb2_rst 3>;
739 #address-cells = <1>;
743 gmac: ethernet@01c30000 {
744 compatible = "allwinner,sun7i-a20-gmac";
745 reg = <0x01c30000 0x1054>;
746 interrupts = <0 82 4>;
747 interrupt-names = "macirq";
748 clocks = <&ahb1_gates 17>, <&gmac_tx_clk>;
749 clock-names = "stmmaceth", "allwinner_gmac_tx";
750 resets = <&ahb1_rst 17>;
751 reset-names = "stmmaceth";
754 snps,force_sf_dma_mode;
756 #address-cells = <1>;
761 compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer";
762 reg = <0x01c60000 0x1000>;
763 interrupts = <0 51 4>,
767 clocks = <&ahb1_gates 19>;
768 resets = <&ahb1_rst 19>;
772 compatible = "allwinner,sun6i-a31-spi";
773 reg = <0x01c68000 0x1000>;
774 interrupts = <0 65 4>;
775 clocks = <&ahb1_gates 20>, <&spi0_clk>;
776 clock-names = "ahb", "mod";
777 dmas = <&dma 23>, <&dma 23>;
778 dma-names = "rx", "tx";
779 resets = <&ahb1_rst 20>;
784 compatible = "allwinner,sun6i-a31-spi";
785 reg = <0x01c69000 0x1000>;
786 interrupts = <0 66 4>;
787 clocks = <&ahb1_gates 21>, <&spi1_clk>;
788 clock-names = "ahb", "mod";
789 dmas = <&dma 24>, <&dma 24>;
790 dma-names = "rx", "tx";
791 resets = <&ahb1_rst 21>;
796 compatible = "allwinner,sun6i-a31-spi";
797 reg = <0x01c6a000 0x1000>;
798 interrupts = <0 67 4>;
799 clocks = <&ahb1_gates 22>, <&spi2_clk>;
800 clock-names = "ahb", "mod";
801 dmas = <&dma 25>, <&dma 25>;
802 dma-names = "rx", "tx";
803 resets = <&ahb1_rst 22>;
808 compatible = "allwinner,sun6i-a31-spi";
809 reg = <0x01c6b000 0x1000>;
810 interrupts = <0 68 4>;
811 clocks = <&ahb1_gates 23>, <&spi3_clk>;
812 clock-names = "ahb", "mod";
813 dmas = <&dma 26>, <&dma 26>;
814 dma-names = "rx", "tx";
815 resets = <&ahb1_rst 23>;
819 gic: interrupt-controller@01c81000 {
820 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
821 reg = <0x01c81000 0x1000>,
825 interrupt-controller;
826 #interrupt-cells = <3>;
827 interrupts = <1 9 0xf04>;
831 compatible = "allwinner,sun6i-a31-rtc";
832 reg = <0x01f00000 0x54>;
833 interrupts = <0 40 4>, <0 41 4>;
836 nmi_intc: interrupt-controller@01f00c0c {
837 compatible = "allwinner,sun6i-a31-sc-nmi";
838 interrupt-controller;
839 #interrupt-cells = <2>;
840 reg = <0x01f00c0c 0x38>;
841 interrupts = <0 32 4>;
845 compatible = "allwinner,sun6i-a31-prcm";
846 reg = <0x01f01400 0x200>;
849 compatible = "allwinner,sun6i-a31-ar100-clk";
851 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
852 clock-output-names = "ar100";
856 compatible = "fixed-factor-clock";
861 clock-output-names = "ahb0";
865 compatible = "allwinner,sun6i-a31-apb0-clk";
868 clock-output-names = "apb0";
871 apb0_gates: apb0_gates_clk {
872 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
875 clock-output-names = "apb0_pio", "apb0_ir",
876 "apb0_timer", "apb0_p2wi",
877 "apb0_uart", "apb0_1wire",
882 compatible = "allwinner,sun6i-a31-clock-reset";
888 compatible = "allwinner,sun6i-a31-cpuconfig";
889 reg = <0x01f01c00 0x300>;
892 r_pio: pinctrl@01f02c00 {
893 compatible = "allwinner,sun6i-a31-r-pinctrl";
894 reg = <0x01f02c00 0x400>;
895 interrupts = <0 45 4>,
897 clocks = <&apb0_gates 0>;
898 resets = <&apb0_rst 0>;
900 interrupt-controller;
901 #interrupt-cells = <2>;