arch/arm/boot/dts/sun6i-a31.dtsi

   1 /*
   2  * Copyright 2013 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 /include/ "skeleton.dtsi"
  15
  16 / {
  17         interrupt-parent = <&gic>;
  18
  19         aliases {
  20                 serial0 = &uart0;
  21                 serial1 = &uart1;
  22                 serial2 = &uart2;
  23                 serial3 = &uart3;
  24                 serial4 = &uart4;
  25                 serial5 = &uart5;
  26         };
  27
  28
  29         cpus {
  30                 enable-method = "allwinner,sun6i-a31";
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33
  34                 cpu@0 {
  35                         compatible = "arm,cortex-a7";
  36                         device_type = "cpu";
  37                         reg = <0>;
  38                 };
  39
  40                 cpu@1 {
  41                         compatible = "arm,cortex-a7";
  42                         device_type = "cpu";
  43                         reg = <1>;
  44                 };
  45
  46                 cpu@2 {
  47                         compatible = "arm,cortex-a7";
  48                         device_type = "cpu";
  49                         reg = <2>;
  50                 };
  51
  52                 cpu@3 {
  53                         compatible = "arm,cortex-a7";
  54                         device_type = "cpu";
  55                         reg = <3>;
  56                 };
  57         };
  58
  59         memory {
  60                 reg = <0x40000000 0x80000000>;
  61         };
  62
  63         pmu {
  64                 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
  65                 interrupts = <0 120 4>,
  66                              <0 121 4>,
  67                              <0 122 4>,
  68                              <0 123 4>;
  69         };
  70
  71         clocks {
  72                 #address-cells = <1>;
  73                 #size-cells = <1>;
  74                 ranges;
  75
  76                 osc24M: osc24M {
  77                         #clock-cells = <0>;
  78                         compatible = "fixed-clock";
  79                         clock-frequency = <24000000>;
  80                 };
  81
  82                 osc32k: clk@0 {
  83                         #clock-cells = <0>;
  84                         compatible = "fixed-clock";
  85                         clock-frequency = <32768>;
  86                         clock-output-names = "osc32k";
  87                 };
  88
  89                 pll1: clk@01c20000 {
  90                         #clock-cells = <0>;
  91                         compatible = "allwinner,sun6i-a31-pll1-clk";
  92                         reg = <0x01c20000 0x4>;
  93                         clocks = <&osc24M>;
  94                         clock-output-names = "pll1";
  95                 };
  96
  97                 pll6: clk@01c20028 {
  98                         #clock-cells = <0>;
  99                         compatible = "allwinner,sun6i-a31-pll6-clk";
 100                         reg = <0x01c20028 0x4>;
 101                         clocks = <&osc24M>;
 102                         clock-output-names = "pll6";
 103                 };
 104
 105                 cpu: cpu@01c20050 {
 106                         #clock-cells = <0>;
 107                         compatible = "allwinner,sun4i-a10-cpu-clk";
 108                         reg = <0x01c20050 0x4>;
 109
 110                         /*
 111                          * PLL1 is listed twice here.
 112                          * While it looks suspicious, it's actually documented
 113                          * that way both in the datasheet and in the code from
 114                          * Allwinner.
 115                          */
 116                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
 117                         clock-output-names = "cpu";
 118                 };
 119
 120                 axi: axi@01c20050 {
 121                         #clock-cells = <0>;
 122                         compatible = "allwinner,sun4i-a10-axi-clk";
 123                         reg = <0x01c20050 0x4>;
 124                         clocks = <&cpu>;
 125                         clock-output-names = "axi";
 126                 };
 127
 128                 ahb1_mux: ahb1_mux@01c20054 {
 129                         #clock-cells = <0>;
 130                         compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
 131                         reg = <0x01c20054 0x4>;
 132                         clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
 133                         clock-output-names = "ahb1_mux";
 134                 };
 135
 136                 ahb1: ahb1@01c20054 {
 137                         #clock-cells = <0>;
 138                         compatible = "allwinner,sun4i-a10-ahb-clk";
 139                         reg = <0x01c20054 0x4>;
 140                         clocks = <&ahb1_mux>;
 141                         clock-output-names = "ahb1";
 142                 };
 143
 144                 ahb1_gates: clk@01c20060 {
 145                         #clock-cells = <1>;
 146                         compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
 147                         reg = <0x01c20060 0x8>;
 148                         clocks = <&ahb1>;
 149                         clock-output-names = "ahb1_mipidsi", "ahb1_ss",
 150                                         "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
 151                                         "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
 152                                         "ahb1_nand0", "ahb1_sdram",
 153                                         "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
 154                                         "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
 155                                         "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
 156                                         "ahb1_ehci1", "ahb1_ohci0",
 157                                         "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
 158                                         "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
 159                                         "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
 160                                         "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
 161                                         "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
 162                                         "ahb1_drc0", "ahb1_drc1";
 163                 };
 164
 165                 apb1: apb1@01c20054 {
 166                         #clock-cells = <0>;
 167                         compatible = "allwinner,sun4i-a10-apb0-clk";
 168                         reg = <0x01c20054 0x4>;
 169                         clocks = <&ahb1>;
 170                         clock-output-names = "apb1";
 171                 };
 172
 173                 apb1_gates: clk@01c20068 {
 174                         #clock-cells = <1>;
 175                         compatible = "allwinner,sun6i-a31-apb1-gates-clk";
 176                         reg = <0x01c20068 0x4>;
 177                         clocks = <&apb1>;
 178                         clock-output-names = "apb1_codec", "apb1_digital_mic",
 179                                         "apb1_pio", "apb1_daudio0",
 180                                         "apb1_daudio1";
 181                 };
 182
 183                 apb2_mux: apb2_mux@01c20058 {
 184                         #clock-cells = <0>;
 185                         compatible = "allwinner,sun4i-a10-apb1-mux-clk";
 186                         reg = <0x01c20058 0x4>;
 187                         clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
 188                         clock-output-names = "apb2_mux";
 189                 };
 190
 191                 apb2: apb2@01c20058 {
 192                         #clock-cells = <0>;
 193                         compatible = "allwinner,sun6i-a31-apb2-div-clk";
 194                         reg = <0x01c20058 0x4>;
 195                         clocks = <&apb2_mux>;
 196                         clock-output-names = "apb2";
 197                 };
 198
 199                 apb2_gates: clk@01c2006c {
 200                         #clock-cells = <1>;
 201                         compatible = "allwinner,sun6i-a31-apb2-gates-clk";
 202                         reg = <0x01c2006c 0x4>;
 203                         clocks = <&apb2>;
 204                         clock-output-names = "apb2_i2c0", "apb2_i2c1",
 205                                         "apb2_i2c2", "apb2_i2c3", "apb2_uart0",
 206                                         "apb2_uart1", "apb2_uart2", "apb2_uart3",
 207                                         "apb2_uart4", "apb2_uart5";
 208                 };
 209
 210                 mmc0_clk: clk@01c20088 {
 211                         #clock-cells = <0>;
 212                         compatible = "allwinner,sun4i-a10-mod0-clk";
 213                         reg = <0x01c20088 0x4>;
 214                         clocks = <&osc24M>, <&pll6>;
 215                         clock-output-names = "mmc0";
 216                 };
 217
 218                 mmc1_clk: clk@01c2008c {
 219                         #clock-cells = <0>;
 220                         compatible = "allwinner,sun4i-a10-mod0-clk";
 221                         reg = <0x01c2008c 0x4>;
 222                         clocks = <&osc24M>, <&pll6>;
 223                         clock-output-names = "mmc1";
 224                 };
 225
 226                 mmc2_clk: clk@01c20090 {
 227                         #clock-cells = <0>;
 228                         compatible = "allwinner,sun4i-a10-mod0-clk";
 229                         reg = <0x01c20090 0x4>;
 230                         clocks = <&osc24M>, <&pll6>;
 231                         clock-output-names = "mmc2";
 232                 };
 233
 234                 mmc3_clk: clk@01c20094 {
 235                         #clock-cells = <0>;
 236                         compatible = "allwinner,sun4i-a10-mod0-clk";
 237                         reg = <0x01c20094 0x4>;
 238                         clocks = <&osc24M>, <&pll6>;
 239                         clock-output-names = "mmc3";
 240                 };
 241
 242                 spi0_clk: clk@01c200a0 {
 243                         #clock-cells = <0>;
 244                         compatible = "allwinner,sun4i-a10-mod0-clk";
 245                         reg = <0x01c200a0 0x4>;
 246                         clocks = <&osc24M>, <&pll6>;
 247                         clock-output-names = "spi0";
 248                 };
 249
 250                 spi1_clk: clk@01c200a4 {
 251                         #clock-cells = <0>;
 252                         compatible = "allwinner,sun4i-a10-mod0-clk";
 253                         reg = <0x01c200a4 0x4>;
 254                         clocks = <&osc24M>, <&pll6>;
 255                         clock-output-names = "spi1";
 256                 };
 257
 258                 spi2_clk: clk@01c200a8 {
 259                         #clock-cells = <0>;
 260                         compatible = "allwinner,sun4i-a10-mod0-clk";
 261                         reg = <0x01c200a8 0x4>;
 262                         clocks = <&osc24M>, <&pll6>;
 263                         clock-output-names = "spi2";
 264                 };
 265
 266                 spi3_clk: clk@01c200ac {
 267                         #clock-cells = <0>;
 268                         compatible = "allwinner,sun4i-a10-mod0-clk";
 269                         reg = <0x01c200ac 0x4>;
 270                         clocks = <&osc24M>, <&pll6>;
 271                         clock-output-names = "spi3";
 272                 };
 273
 274                 usb_clk: clk@01c200cc {
 275                         #clock-cells = <1>;
 276                         #reset-cells = <1>;
 277                         compatible = "allwinner,sun6i-a31-usb-clk";
 278                         reg = <0x01c200cc 0x4>;
 279                         clocks = <&osc24M>;
 280                         clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2",
 281                                              "usb_ohci0", "usb_ohci1",
 282                                              "usb_ohci2";
 283                 };
 284
 285                 /*
 286                  * The following two are dummy clocks, placeholders used in the gmac_tx
 287                  * clock. The gmac driver will choose one parent depending on the PHY
 288                  * interface mode, using clk_set_rate auto-reparenting.
 289                  * The actual TX clock rate is not controlled by the gmac_tx clock.
 290                  */
 291                 mii_phy_tx_clk: clk@1 {
 292                         #clock-cells = <0>;
 293                         compatible = "fixed-clock";
 294                         clock-frequency = <25000000>;
 295                         clock-output-names = "mii_phy_tx";
 296                 };
 297
 298                 gmac_int_tx_clk: clk@2 {
 299                         #clock-cells = <0>;
 300                         compatible = "fixed-clock";
 301                         clock-frequency = <125000000>;
 302                         clock-output-names = "gmac_int_tx";
 303                 };
 304
 305                 gmac_tx_clk: clk@01c200d0 {
 306                         #clock-cells = <0>;
 307                         compatible = "allwinner,sun7i-a20-gmac-clk";
 308                         reg = <0x01c200d0 0x4>;
 309                         clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
 310                         clock-output-names = "gmac_tx";
 311                 };
 312         };
 313
 314         soc@01c00000 {
 315                 compatible = "simple-bus";
 316                 #address-cells = <1>;
 317                 #size-cells = <1>;
 318                 ranges;
 319
 320                 dma: dma-controller@01c02000 {
 321                         compatible = "allwinner,sun6i-a31-dma";
 322                         reg = <0x01c02000 0x1000>;
 323                         interrupts = <0 50 4>;
 324                         clocks = <&ahb1_gates 6>;
 325                         resets = <&ahb1_rst 6>;
 326                         #dma-cells = <1>;
 327                 };
 328
 329                 mmc0: mmc@01c0f000 {
 330                         compatible = "allwinner,sun5i-a13-mmc";
 331                         reg = <0x01c0f000 0x1000>;
 332                         clocks = <&ahb1_gates 8>, <&mmc0_clk>;
 333                         clock-names = "ahb", "mmc";
 334                         resets = <&ahb1_rst 8>;
 335                         reset-names = "ahb";
 336                         interrupts = <0 60 4>;
 337                         status = "disabled";
 338                 };
 339
 340                 mmc1: mmc@01c10000 {
 341                         compatible = "allwinner,sun5i-a13-mmc";
 342                         reg = <0x01c10000 0x1000>;
 343                         clocks = <&ahb1_gates 9>, <&mmc1_clk>;
 344                         clock-names = "ahb", "mmc";
 345                         resets = <&ahb1_rst 9>;
 346                         reset-names = "ahb";
 347                         interrupts = <0 61 4>;
 348                         status = "disabled";
 349                 };
 350
 351                 mmc2: mmc@01c11000 {
 352                         compatible = "allwinner,sun5i-a13-mmc";
 353                         reg = <0x01c11000 0x1000>;
 354                         clocks = <&ahb1_gates 10>, <&mmc2_clk>;
 355                         clock-names = "ahb", "mmc";
 356                         resets = <&ahb1_rst 10>;
 357                         reset-names = "ahb";
 358                         interrupts = <0 62 4>;
 359                         status = "disabled";
 360                 };
 361
 362                 mmc3: mmc@01c12000 {
 363                         compatible = "allwinner,sun5i-a13-mmc";
 364                         reg = <0x01c12000 0x1000>;
 365                         clocks = <&ahb1_gates 11>, <&mmc3_clk>;
 366                         clock-names = "ahb", "mmc";
 367                         resets = <&ahb1_rst 11>;
 368                         reset-names = "ahb";
 369                         interrupts = <0 63 4>;
 370                         status = "disabled";
 371                 };
 372
 373                 usbphy: phy@01c19400 {
 374                         compatible = "allwinner,sun6i-a31-usb-phy";
 375                         reg = <0x01c19400 0x10>,
 376                               <0x01c1a800 0x4>,
 377                               <0x01c1b800 0x4>;
 378                         reg-names = "phy_ctrl",
 379                                     "pmu1",
 380                                     "pmu2";
 381                         clocks = <&usb_clk 8>,
 382                                  <&usb_clk 9>,
 383                                  <&usb_clk 10>;
 384                         clock-names = "usb0_phy",
 385                                       "usb1_phy",
 386                                       "usb2_phy";
 387                         resets = <&usb_clk 0>,
 388                                  <&usb_clk 1>,
 389                                  <&usb_clk 2>;
 390                         reset-names = "usb0_reset",
 391                                       "usb1_reset",
 392                                       "usb2_reset";
 393                         status = "disabled";
 394                         #phy-cells = <1>;
 395                 };
 396
 397                 ehci0: usb@01c1a000 {
 398                         compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
 399                         reg = <0x01c1a000 0x100>;
 400                         interrupts = <0 72 4>;
 401                         clocks = <&ahb1_gates 26>;
 402                         resets = <&ahb1_rst 26>;
 403                         phys = <&usbphy 1>;
 404                         phy-names = "usb";
 405                         status = "disabled";
 406                 };
 407
 408                 ohci0: usb@01c1a400 {
 409                         compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
 410                         reg = <0x01c1a400 0x100>;
 411                         interrupts = <0 73 4>;
 412                         clocks = <&ahb1_gates 29>, <&usb_clk 16>;
 413                         resets = <&ahb1_rst 29>;
 414                         phys = <&usbphy 1>;
 415                         phy-names = "usb";
 416                         status = "disabled";
 417                 };
 418
 419                 ehci1: usb@01c1b000 {
 420                         compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
 421                         reg = <0x01c1b000 0x100>;
 422                         interrupts = <0 74 4>;
 423                         clocks = <&ahb1_gates 27>;
 424                         resets = <&ahb1_rst 27>;
 425                         phys = <&usbphy 2>;
 426                         phy-names = "usb";
 427                         status = "disabled";
 428                 };
 429
 430                 ohci1: usb@01c1b400 {
 431                         compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
 432                         reg = <0x01c1b400 0x100>;
 433                         interrupts = <0 75 4>;
 434                         clocks = <&ahb1_gates 30>, <&usb_clk 17>;
 435                         resets = <&ahb1_rst 30>;
 436                         phys = <&usbphy 2>;
 437                         phy-names = "usb";
 438                         status = "disabled";
 439                 };
 440
 441                 ohci2: usb@01c1c400 {
 442                         compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
 443                         reg = <0x01c1c400 0x100>;
 444                         interrupts = <0 77 4>;
 445                         clocks = <&ahb1_gates 31>, <&usb_clk 18>;
 446                         resets = <&ahb1_rst 31>;
 447                         status = "disabled";
 448                 };
 449
 450                 pio: pinctrl@01c20800 {
 451                         compatible = "allwinner,sun6i-a31-pinctrl";
 452                         reg = <0x01c20800 0x400>;
 453                         interrupts = <0 11 4>,
 454                                      <0 15 4>,
 455                                      <0 16 4>,
 456                                      <0 17 4>;
 457                         clocks = <&apb1_gates 5>;
 458                         gpio-controller;
 459                         interrupt-controller;
 460                         #interrupt-cells = <2>;
 461                         #size-cells = <0>;
 462                         #gpio-cells = <3>;
 463
 464                         uart0_pins_a: uart0@0 {
 465                                 allwinner,pins = "PH20", "PH21";
 466                                 allwinner,function = "uart0";
 467                                 allwinner,drive = <0>;
 468                                 allwinner,pull = <0>;
 469                         };
 470
 471                         i2c0_pins_a: i2c0@0 {
 472                                 allwinner,pins = "PH14", "PH15";
 473                                 allwinner,function = "i2c0";
 474                                 allwinner,drive = <0>;
 475                                 allwinner,pull = <0>;
 476                         };
 477
 478                         i2c1_pins_a: i2c1@0 {
 479                                 allwinner,pins = "PH16", "PH17";
 480                                 allwinner,function = "i2c1";
 481                                 allwinner,drive = <0>;
 482                                 allwinner,pull = <0>;
 483                         };
 484
 485                         i2c2_pins_a: i2c2@0 {
 486                                 allwinner,pins = "PH18", "PH19";
 487                                 allwinner,function = "i2c2";
 488                                 allwinner,drive = <0>;
 489                                 allwinner,pull = <0>;
 490                         };
 491
 492                         mmc0_pins_a: mmc0@0 {
 493                                 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
 494                                 allwinner,function = "mmc0";
 495                                 allwinner,drive = <2>;
 496                                 allwinner,pull = <0>;
 497                         };
 498
 499                         gmac_pins_mii_a: gmac_mii@0 {
 500                                 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
 501                                                 "PA8", "PA9", "PA11",
 502                                                 "PA12", "PA13", "PA14", "PA19",
 503                                                 "PA20", "PA21", "PA22", "PA23",
 504                                                 "PA24", "PA26", "PA27";
 505                                 allwinner,function = "gmac";
 506                                 allwinner,drive = <0>;
 507                                 allwinner,pull = <0>;
 508                         };
 509
 510                         gmac_pins_gmii_a: gmac_gmii@0 {
 511                                 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
 512                                                 "PA4", "PA5", "PA6", "PA7",
 513                                                 "PA8", "PA9", "PA10", "PA11",
 514                                                 "PA12", "PA13", "PA14", "PA15",
 515                                                 "PA16", "PA17", "PA18", "PA19",
 516                                                 "PA20", "PA21", "PA22", "PA23",
 517                                                 "PA24", "PA25", "PA26", "PA27";
 518                                 allwinner,function = "gmac";
 519                                 /*
 520                                  * data lines in GMII mode run at 125MHz and
 521                                  * might need a higher signal drive strength
 522                                  */
 523                                 allwinner,drive = <2>;
 524                                 allwinner,pull = <0>;
 525                         };
 526
 527                         gmac_pins_rgmii_a: gmac_rgmii@0 {
 528                                 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
 529                                                 "PA9", "PA10", "PA11",
 530                                                 "PA12", "PA13", "PA14", "PA19",
 531                                                 "PA20", "PA25", "PA26", "PA27";
 532                                 allwinner,function = "gmac";
 533                                 /*
 534                                  * data lines in RGMII mode use DDR mode
 535                                  * and need a higher signal drive strength
 536                                  */
 537                                 allwinner,drive = <3>;
 538                                 allwinner,pull = <0>;
 539                         };
 540                 };
 541
 542                 ahb1_rst: reset@01c202c0 {
 543                         #reset-cells = <1>;
 544                         compatible = "allwinner,sun6i-a31-ahb1-reset";
 545                         reg = <0x01c202c0 0xc>;
 546                 };
 547
 548                 apb1_rst: reset@01c202d0 {
 549                         #reset-cells = <1>;
 550                         compatible = "allwinner,sun6i-a31-clock-reset";
 551                         reg = <0x01c202d0 0x4>;
 552                 };
 553
 554                 apb2_rst: reset@01c202d8 {
 555                         #reset-cells = <1>;
 556                         compatible = "allwinner,sun6i-a31-clock-reset";
 557                         reg = <0x01c202d8 0x4>;
 558                 };
 559
 560                 timer@01c20c00 {
 561                         compatible = "allwinner,sun4i-a10-timer";
 562                         reg = <0x01c20c00 0xa0>;
 563                         interrupts = <0 18 4>,
 564                                      <0 19 4>,
 565                                      <0 20 4>,
 566                                      <0 21 4>,
 567                                      <0 22 4>;
 568                         clocks = <&osc24M>;
 569                 };
 570
 571                 wdt1: watchdog@01c20ca0 {
 572                         compatible = "allwinner,sun6i-a31-wdt";
 573                         reg = <0x01c20ca0 0x20>;
 574                 };
 575
 576                 uart0: serial@01c28000 {
 577                         compatible = "snps,dw-apb-uart";
 578                         reg = <0x01c28000 0x400>;
 579                         interrupts = <0 0 4>;
 580                         reg-shift = <2>;
 581                         reg-io-width = <4>;
 582                         clocks = <&apb2_gates 16>;
 583                         resets = <&apb2_rst 16>;
 584                         dmas = <&dma 6>, <&dma 6>;
 585                         dma-names = "rx", "tx";
 586                         status = "disabled";
 587                 };
 588
 589                 uart1: serial@01c28400 {
 590                         compatible = "snps,dw-apb-uart";
 591                         reg = <0x01c28400 0x400>;
 592                         interrupts = <0 1 4>;
 593                         reg-shift = <2>;
 594                         reg-io-width = <4>;
 595                         clocks = <&apb2_gates 17>;
 596                         resets = <&apb2_rst 17>;
 597                         dmas = <&dma 7>, <&dma 7>;
 598                         dma-names = "rx", "tx";
 599                         status = "disabled";
 600                 };
 601
 602                 uart2: serial@01c28800 {
 603                         compatible = "snps,dw-apb-uart";
 604                         reg = <0x01c28800 0x400>;
 605                         interrupts = <0 2 4>;
 606                         reg-shift = <2>;
 607                         reg-io-width = <4>;
 608                         clocks = <&apb2_gates 18>;
 609                         resets = <&apb2_rst 18>;
 610                         dmas = <&dma 8>, <&dma 8>;
 611                         dma-names = "rx", "tx";
 612                         status = "disabled";
 613                 };
 614
 615                 uart3: serial@01c28c00 {
 616                         compatible = "snps,dw-apb-uart";
 617                         reg = <0x01c28c00 0x400>;
 618                         interrupts = <0 3 4>;
 619                         reg-shift = <2>;
 620                         reg-io-width = <4>;
 621                         clocks = <&apb2_gates 19>;
 622                         resets = <&apb2_rst 19>;
 623                         dmas = <&dma 9>, <&dma 9>;
 624                         dma-names = "rx", "tx";
 625                         status = "disabled";
 626                 };
 627
 628                 uart4: serial@01c29000 {
 629                         compatible = "snps,dw-apb-uart";
 630                         reg = <0x01c29000 0x400>;
 631                         interrupts = <0 4 4>;
 632                         reg-shift = <2>;
 633                         reg-io-width = <4>;
 634                         clocks = <&apb2_gates 20>;
 635                         resets = <&apb2_rst 20>;
 636                         dmas = <&dma 10>, <&dma 10>;
 637                         dma-names = "rx", "tx";
 638                         status = "disabled";
 639                 };
 640
 641                 uart5: serial@01c29400 {
 642                         compatible = "snps,dw-apb-uart";
 643                         reg = <0x01c29400 0x400>;
 644                         interrupts = <0 5 4>;
 645                         reg-shift = <2>;
 646                         reg-io-width = <4>;
 647                         clocks = <&apb2_gates 21>;
 648                         resets = <&apb2_rst 21>;
 649                         dmas = <&dma 22>, <&dma 22>;
 650                         dma-names = "rx", "tx";
 651                         status = "disabled";
 652                 };
 653
 654                 i2c0: i2c@01c2ac00 {
 655                         compatible = "allwinner,sun6i-a31-i2c";
 656                         reg = <0x01c2ac00 0x400>;
 657                         interrupts = <0 6 4>;
 658                         clocks = <&apb2_gates 0>;
 659                         clock-frequency = <100000>;
 660                         resets = <&apb2_rst 0>;
 661                         status = "disabled";
 662                 };
 663
 664                 i2c1: i2c@01c2b000 {
 665                         compatible = "allwinner,sun6i-a31-i2c";
 666                         reg = <0x01c2b000 0x400>;
 667                         interrupts = <0 7 4>;
 668                         clocks = <&apb2_gates 1>;
 669                         clock-frequency = <100000>;
 670                         resets = <&apb2_rst 1>;
 671                         status = "disabled";
 672                 };
 673
 674                 i2c2: i2c@01c2b400 {
 675                         compatible = "allwinner,sun6i-a31-i2c";
 676                         reg = <0x01c2b400 0x400>;
 677                         interrupts = <0 8 4>;
 678                         clocks = <&apb2_gates 2>;
 679                         clock-frequency = <100000>;
 680                         resets = <&apb2_rst 2>;
 681                         status = "disabled";
 682                 };
 683
 684                 i2c3: i2c@01c2b800 {
 685                         compatible = "allwinner,sun6i-a31-i2c";
 686                         reg = <0x01c2b800 0x400>;
 687                         interrupts = <0 9 4>;
 688                         clocks = <&apb2_gates 3>;
 689                         clock-frequency = <100000>;
 690                         resets = <&apb2_rst 3>;
 691                         status = "disabled";
 692                 };
 693
 694                 gmac: ethernet@01c30000 {
 695                         compatible = "allwinner,sun7i-a20-gmac";
 696                         reg = <0x01c30000 0x1054>;
 697                         interrupts = <0 82 4>;
 698                         interrupt-names = "macirq";
 699                         clocks = <&ahb1_gates 17>, <&gmac_tx_clk>;
 700                         clock-names = "stmmaceth", "allwinner_gmac_tx";
 701                         resets = <&ahb1_rst 17>;
 702                         reset-names = "stmmaceth";
 703                         snps,pbl = <2>;
 704                         snps,fixed-burst;
 705                         snps,force_sf_dma_mode;
 706                         status = "disabled";
 707                         #address-cells = <1>;
 708                         #size-cells = <0>;
 709                 };
 710
 711                 timer@01c60000 {
 712                         compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer";
 713                         reg = <0x01c60000 0x1000>;
 714                         interrupts = <0 51 4>,
 715                                      <0 52 4>,
 716                                      <0 53 4>,
 717                                      <0 54 4>;
 718                         clocks = <&ahb1_gates 19>;
 719                         resets = <&ahb1_rst 19>;
 720                 };
 721
 722                 spi0: spi@01c68000 {
 723                         compatible = "allwinner,sun6i-a31-spi";
 724                         reg = <0x01c68000 0x1000>;
 725                         interrupts = <0 65 4>;
 726                         clocks = <&ahb1_gates 20>, <&spi0_clk>;
 727                         clock-names = "ahb", "mod";
 728                         dmas = <&dma 23>, <&dma 23>;
 729                         dma-names = "rx", "tx";
 730                         resets = <&ahb1_rst 20>;
 731                         status = "disabled";
 732                 };
 733
 734                 spi1: spi@01c69000 {
 735                         compatible = "allwinner,sun6i-a31-spi";
 736                         reg = <0x01c69000 0x1000>;
 737                         interrupts = <0 66 4>;
 738                         clocks = <&ahb1_gates 21>, <&spi1_clk>;
 739                         clock-names = "ahb", "mod";
 740                         dmas = <&dma 24>, <&dma 24>;
 741                         dma-names = "rx", "tx";
 742                         resets = <&ahb1_rst 21>;
 743                         status = "disabled";
 744                 };
 745
 746                 spi2: spi@01c6a000 {
 747                         compatible = "allwinner,sun6i-a31-spi";
 748                         reg = <0x01c6a000 0x1000>;
 749                         interrupts = <0 67 4>;
 750                         clocks = <&ahb1_gates 22>, <&spi2_clk>;
 751                         clock-names = "ahb", "mod";
 752                         dmas = <&dma 25>, <&dma 25>;
 753                         dma-names = "rx", "tx";
 754                         resets = <&ahb1_rst 22>;
 755                         status = "disabled";
 756                 };
 757
 758                 spi3: spi@01c6b000 {
 759                         compatible = "allwinner,sun6i-a31-spi";
 760                         reg = <0x01c6b000 0x1000>;
 761                         interrupts = <0 68 4>;
 762                         clocks = <&ahb1_gates 23>, <&spi3_clk>;
 763                         clock-names = "ahb", "mod";
 764                         dmas = <&dma 26>, <&dma 26>;
 765                         dma-names = "rx", "tx";
 766                         resets = <&ahb1_rst 23>;
 767                         status = "disabled";
 768                 };
 769
 770                 gic: interrupt-controller@01c81000 {
 771                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 772                         reg = <0x01c81000 0x1000>,
 773                               <0x01c82000 0x1000>,
 774                               <0x01c84000 0x2000>,
 775                               <0x01c86000 0x2000>;
 776                         interrupt-controller;
 777                         #interrupt-cells = <3>;
 778                         interrupts = <1 9 0xf04>;
 779                 };
 780
 781                 nmi_intc: interrupt-controller@01f00c0c {
 782                         compatible = "allwinner,sun6i-a31-sc-nmi";
 783                         interrupt-controller;
 784                         #interrupt-cells = <2>;
 785                         reg = <0x01f00c0c 0x38>;
 786                         interrupts = <0 32 4>;
 787                 };
 788
 789                 prcm@01f01400 {
 790                         compatible = "allwinner,sun6i-a31-prcm";
 791                         reg = <0x01f01400 0x200>;
 792
 793                         ar100: ar100_clk {
 794                                 compatible = "allwinner,sun6i-a31-ar100-clk";
 795                                 #clock-cells = <0>;
 796                                 clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
 797                                 clock-output-names = "ar100";
 798                         };
 799
 800                         ahb0: ahb0_clk {
 801                                 compatible = "fixed-factor-clock";
 802                                 #clock-cells = <0>;
 803                                 clock-div = <1>;
 804                                 clock-mult = <1>;
 805                                 clocks = <&ar100>;
 806                                 clock-output-names = "ahb0";
 807                         };
 808
 809                         apb0: apb0_clk {
 810                                 compatible = "allwinner,sun6i-a31-apb0-clk";
 811                                 #clock-cells = <0>;
 812                                 clocks = <&ahb0>;
 813                                 clock-output-names = "apb0";
 814                         };
 815
 816                         apb0_gates: apb0_gates_clk {
 817                                 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
 818                                 #clock-cells = <1>;
 819                                 clocks = <&apb0>;
 820                                 clock-output-names = "apb0_pio", "apb0_ir",
 821                                                 "apb0_timer", "apb0_p2wi",
 822                                                 "apb0_uart", "apb0_1wire",
 823                                                 "apb0_i2c";
 824                         };
 825
 826                         apb0_rst: apb0_rst {
 827                                 compatible = "allwinner,sun6i-a31-clock-reset";
 828                                 #reset-cells = <1>;
 829                         };
 830                 };
 831
 832                 cpucfg@01f01c00 {
 833                         compatible = "allwinner,sun6i-a31-cpuconfig";
 834                         reg = <0x01f01c00 0x300>;
 835                 };
 836
 837                 r_pio: pinctrl@01f02c00 {
 838                         compatible = "allwinner,sun6i-a31-r-pinctrl";
 839                         reg = <0x01f02c00 0x400>;
 840                         interrupts = <0 45 4>,
 841                                      <0 46 4>;
 842                         clocks = <&apb0_gates 0>;
 843                         resets = <&apb0_rst 0>;
 844                         gpio-controller;
 845                         interrupt-controller;
 846                         #interrupt-cells = <2>;
 847                         #size-cells = <0>;
 848                         #gpio-cells = <3>;
 849                 };
 850         };
 851 };