arch/arm/boot/dts/sun7i-a20.dtsi

   1 /*
   2  * Copyright 2013 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 /include/ "skeleton.dtsi"
  15
  16 / {
  17         interrupt-parent = <&gic>;
  18
  19         cpus {
  20                 #address-cells = <1>;
  21                 #size-cells = <0>;
  22
  23                 cpu@0 {
  24                         compatible = "arm,cortex-a7";
  25                         device_type = "cpu";
  26                         reg = <0>;
  27                 };
  28
  29                 cpu@1 {
  30                         compatible = "arm,cortex-a7";
  31                         device_type = "cpu";
  32                         reg = <1>;
  33                 };
  34         };
  35
  36         memory {
  37                 reg = <0x40000000 0x80000000>;
  38         };
  39
  40         clocks {
  41                 #address-cells = <1>;
  42                 #size-cells = <1>;
  43                 ranges;
  44
  45                 osc24M: osc24M@01c20050 {
  46                         #clock-cells = <0>;
  47                         compatible = "allwinner,sun4i-osc-clk";
  48                         reg = <0x01c20050 0x4>;
  49                         clock-frequency = <24000000>;
  50                 };
  51
  52                 osc32k: osc32k {
  53                         #clock-cells = <0>;
  54                         compatible = "fixed-clock";
  55                         clock-frequency = <32768>;
  56                 };
  57
  58                 pll1: pll1@01c20000 {
  59                         #clock-cells = <0>;
  60                         compatible = "allwinner,sun4i-pll1-clk";
  61                         reg = <0x01c20000 0x4>;
  62                         clocks = <&osc24M>;
  63                 };
  64
  65                 /*
  66                  * This is a dummy clock, to be used as placeholder on
  67                  * other mux clocks when a specific parent clock is not
  68                  * yet implemented. It should be dropped when the driver
  69                  * is complete.
  70                  */
  71                 pll6: pll6 {
  72                         #clock-cells = <0>;
  73                         compatible = "fixed-clock";
  74                         clock-frequency = <0>;
  75                 };
  76
  77                 cpu: cpu@01c20054 {
  78                         #clock-cells = <0>;
  79                         compatible = "allwinner,sun4i-cpu-clk";
  80                         reg = <0x01c20054 0x4>;
  81                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6>;
  82                 };
  83
  84                 axi: axi@01c20054 {
  85                         #clock-cells = <0>;
  86                         compatible = "allwinner,sun4i-axi-clk";
  87                         reg = <0x01c20054 0x4>;
  88                         clocks = <&cpu>;
  89                 };
  90
  91                 ahb: ahb@01c20054 {
  92                         #clock-cells = <0>;
  93                         compatible = "allwinner,sun4i-ahb-clk";
  94                         reg = <0x01c20054 0x4>;
  95                         clocks = <&axi>;
  96                 };
  97
  98                 ahb_gates: ahb_gates@01c20060 {
  99                         #clock-cells = <1>;
 100                         compatible = "allwinner,sun7i-a20-ahb-gates-clk";
 101                         reg = <0x01c20060 0x8>;
 102                         clocks = <&ahb>;
 103                         clock-output-names = "ahb_usb0", "ahb_ehci0",
 104                                 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
 105                                 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
 106                                 "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
 107                                 "ahb_nand", "ahb_sdram", "ahb_ace",
 108                                 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
 109                                 "ahb_spi2", "ahb_spi3", "ahb_sata",
 110                                 "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
 111                                 "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
 112                                 "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
 113                                 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
 114                                 "ahb_de_fe1", "ahb_gmac", "ahb_mp",
 115                                 "ahb_mali";
 116                 };
 117
 118                 apb0: apb0@01c20054 {
 119                         #clock-cells = <0>;
 120                         compatible = "allwinner,sun4i-apb0-clk";
 121                         reg = <0x01c20054 0x4>;
 122                         clocks = <&ahb>;
 123                 };
 124
 125                 apb0_gates: apb0_gates@01c20068 {
 126                         #clock-cells = <1>;
 127                         compatible = "allwinner,sun7i-a20-apb0-gates-clk";
 128                         reg = <0x01c20068 0x4>;
 129                         clocks = <&apb0>;
 130                         clock-output-names = "apb0_codec", "apb0_spdif",
 131                                 "apb0_ac97", "apb0_iis0", "apb0_iis1",
 132                                 "apb0_pio", "apb0_ir0", "apb0_ir1",
 133                                 "apb0_iis2", "apb0_keypad";
 134                 };
 135
 136                 apb1_mux: apb1_mux@01c20058 {
 137                         #clock-cells = <0>;
 138                         compatible = "allwinner,sun4i-apb1-mux-clk";
 139                         reg = <0x01c20058 0x4>;
 140                         clocks = <&osc24M>, <&pll6>, <&osc32k>;
 141                 };
 142
 143                 apb1: apb1@01c20058 {
 144                         #clock-cells = <0>;
 145                         compatible = "allwinner,sun4i-apb1-clk";
 146                         reg = <0x01c20058 0x4>;
 147                         clocks = <&apb1_mux>;
 148                 };
 149
 150                 apb1_gates: apb1_gates@01c2006c {
 151                         #clock-cells = <1>;
 152                         compatible = "allwinner,sun7i-a20-apb1-gates-clk";
 153                         reg = <0x01c2006c 0x4>;
 154                         clocks = <&apb1>;
 155                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 156                                 "apb1_i2c2", "apb1_i2c3", "apb1_can",
 157                                 "apb1_scr", "apb1_ps20", "apb1_ps21",
 158                                 "apb1_i2c4", "apb1_uart0", "apb1_uart1",
 159                                 "apb1_uart2", "apb1_uart3", "apb1_uart4",
 160                                 "apb1_uart5", "apb1_uart6", "apb1_uart7";
 161                 };
 162         };
 163
 164         soc@01c00000 {
 165                 compatible = "simple-bus";
 166                 #address-cells = <1>;
 167                 #size-cells = <1>;
 168                 ranges;
 169
 170                 pio: pinctrl@01c20800 {
 171                         compatible = "allwinner,sun7i-a20-pinctrl";
 172                         reg = <0x01c20800 0x400>;
 173                         interrupts = <0 28 1>;
 174                         clocks = <&apb0_gates 5>;
 175                         gpio-controller;
 176                         interrupt-controller;
 177                         #address-cells = <1>;
 178                         #size-cells = <0>;
 179                         #gpio-cells = <3>;
 180
 181                         uart0_pins_a: uart0@0 {
 182                                 allwinner,pins = "PB22", "PB23";
 183                                 allwinner,function = "uart0";
 184                                 allwinner,drive = <0>;
 185                                 allwinner,pull = <0>;
 186                         };
 187
 188                         uart6_pins_a: uart6@0 {
 189                                 allwinner,pins = "PI12", "PI13";
 190                                 allwinner,function = "uart6";
 191                                 allwinner,drive = <0>;
 192                                 allwinner,pull = <0>;
 193                         };
 194
 195                         uart7_pins_a: uart7@0 {
 196                                 allwinner,pins = "PI20", "PI21";
 197                                 allwinner,function = "uart7";
 198                                 allwinner,drive = <0>;
 199                                 allwinner,pull = <0>;
 200                         };
 201                 };
 202
 203                 timer@01c20c00 {
 204                         compatible = "allwinner,sun4i-timer";
 205                         reg = <0x01c20c00 0x90>;
 206                         interrupts = <0 22 1>,
 207                                      <0 23 1>,
 208                                      <0 24 1>,
 209                                      <0 25 1>,
 210                                      <0 67 1>,
 211                                      <0 68 1>;
 212                         clocks = <&osc24M>;
 213                 };
 214
 215                 wdt: watchdog@01c20c90 {
 216                         compatible = "allwinner,sun4i-wdt";
 217                         reg = <0x01c20c90 0x10>;
 218                 };
 219
 220                 uart0: serial@01c28000 {
 221                         compatible = "snps,dw-apb-uart";
 222                         reg = <0x01c28000 0x400>;
 223                         interrupts = <0 1 1>;
 224                         reg-shift = <2>;
 225                         reg-io-width = <4>;
 226                         clocks = <&apb1_gates 16>;
 227                         status = "disabled";
 228                 };
 229
 230                 uart1: serial@01c28400 {
 231                         compatible = "snps,dw-apb-uart";
 232                         reg = <0x01c28400 0x400>;
 233                         interrupts = <0 2 1>;
 234                         reg-shift = <2>;
 235                         reg-io-width = <4>;
 236                         clocks = <&apb1_gates 17>;
 237                         status = "disabled";
 238                 };
 239
 240                 uart2: serial@01c28800 {
 241                         compatible = "snps,dw-apb-uart";
 242                         reg = <0x01c28800 0x400>;
 243                         interrupts = <0 3 1>;
 244                         reg-shift = <2>;
 245                         reg-io-width = <4>;
 246                         clocks = <&apb1_gates 18>;
 247                         status = "disabled";
 248                 };
 249
 250                 uart3: serial@01c28c00 {
 251                         compatible = "snps,dw-apb-uart";
 252                         reg = <0x01c28c00 0x400>;
 253                         interrupts = <0 4 1>;
 254                         reg-shift = <2>;
 255                         reg-io-width = <4>;
 256                         clocks = <&apb1_gates 19>;
 257                         status = "disabled";
 258                 };
 259
 260                 uart4: serial@01c29000 {
 261                         compatible = "snps,dw-apb-uart";
 262                         reg = <0x01c29000 0x400>;
 263                         interrupts = <0 17 1>;
 264                         reg-shift = <2>;
 265                         reg-io-width = <4>;
 266                         clocks = <&apb1_gates 20>;
 267                         status = "disabled";
 268                 };
 269
 270                 uart5: serial@01c29400 {
 271                         compatible = "snps,dw-apb-uart";
 272                         reg = <0x01c29400 0x400>;
 273                         interrupts = <0 18 1>;
 274                         reg-shift = <2>;
 275                         reg-io-width = <4>;
 276                         clocks = <&apb1_gates 21>;
 277                         status = "disabled";
 278                 };
 279
 280                 uart6: serial@01c29800 {
 281                         compatible = "snps,dw-apb-uart";
 282                         reg = <0x01c29800 0x400>;
 283                         interrupts = <0 19 1>;
 284                         reg-shift = <2>;
 285                         reg-io-width = <4>;
 286                         clocks = <&apb1_gates 22>;
 287                         status = "disabled";
 288                 };
 289
 290                 uart7: serial@01c29c00 {
 291                         compatible = "snps,dw-apb-uart";
 292                         reg = <0x01c29c00 0x400>;
 293                         interrupts = <0 20 1>;
 294                         reg-shift = <2>;
 295                         reg-io-width = <4>;
 296                         clocks = <&apb1_gates 23>;
 297                         status = "disabled";
 298                 };
 299
 300                 gic: interrupt-controller@01c81000 {
 301                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 302                         reg = <0x01c81000 0x1000>,
 303                               <0x01c82000 0x1000>,
 304                               <0x01c84000 0x2000>,
 305                               <0x01c86000 0x2000>;
 306                         interrupt-controller;
 307                         #interrupt-cells = <3>;
 308                         interrupts = <1 9 0xf04>;
 309                 };
 310         };
 311 };