2 * Copyright 2013 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public
22 * License along with this library; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
50 /include/ "skeleton.dtsi"
53 interrupt-parent = <&gic>;
72 compatible = "arm,cortex-a7";
78 compatible = "arm,cortex-a7";
85 reg = <0x40000000 0x80000000>;
89 compatible = "arm,armv7-timer";
90 interrupts = <1 13 0xf08>,
97 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
98 interrupts = <0 120 4>,
103 #address-cells = <1>;
107 osc24M: clk@01c20050 {
109 compatible = "allwinner,sun4i-a10-osc-clk";
110 reg = <0x01c20050 0x4>;
111 clock-frequency = <24000000>;
112 clock-output-names = "osc24M";
117 compatible = "fixed-clock";
118 clock-frequency = <32768>;
119 clock-output-names = "osc32k";
124 compatible = "allwinner,sun4i-a10-pll1-clk";
125 reg = <0x01c20000 0x4>;
127 clock-output-names = "pll1";
132 compatible = "allwinner,sun7i-a20-pll4-clk";
133 reg = <0x01c20018 0x4>;
135 clock-output-names = "pll4";
140 compatible = "allwinner,sun4i-a10-pll5-clk";
141 reg = <0x01c20020 0x4>;
143 clock-output-names = "pll5_ddr", "pll5_other";
148 compatible = "allwinner,sun4i-a10-pll6-clk";
149 reg = <0x01c20028 0x4>;
151 clock-output-names = "pll6_sata", "pll6_other", "pll6";
156 compatible = "allwinner,sun7i-a20-pll4-clk";
157 reg = <0x01c20040 0x4>;
159 clock-output-names = "pll8";
164 compatible = "allwinner,sun4i-a10-cpu-clk";
165 reg = <0x01c20054 0x4>;
166 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
167 clock-output-names = "cpu";
172 compatible = "allwinner,sun4i-a10-axi-clk";
173 reg = <0x01c20054 0x4>;
175 clock-output-names = "axi";
180 compatible = "allwinner,sun4i-a10-ahb-clk";
181 reg = <0x01c20054 0x4>;
183 clock-output-names = "ahb";
186 ahb_gates: clk@01c20060 {
188 compatible = "allwinner,sun7i-a20-ahb-gates-clk";
189 reg = <0x01c20060 0x8>;
191 clock-output-names = "ahb_usb0", "ahb_ehci0",
192 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
193 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
194 "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
195 "ahb_nand", "ahb_sdram", "ahb_ace",
196 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
197 "ahb_spi2", "ahb_spi3", "ahb_sata",
198 "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
199 "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
200 "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
201 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
202 "ahb_de_fe1", "ahb_gmac", "ahb_mp",
206 apb0: apb0@01c20054 {
208 compatible = "allwinner,sun4i-a10-apb0-clk";
209 reg = <0x01c20054 0x4>;
211 clock-output-names = "apb0";
214 apb0_gates: clk@01c20068 {
216 compatible = "allwinner,sun7i-a20-apb0-gates-clk";
217 reg = <0x01c20068 0x4>;
219 clock-output-names = "apb0_codec", "apb0_spdif",
220 "apb0_ac97", "apb0_iis0", "apb0_iis1",
221 "apb0_pio", "apb0_ir0", "apb0_ir1",
222 "apb0_iis2", "apb0_keypad";
225 apb1_mux: apb1_mux@01c20058 {
227 compatible = "allwinner,sun4i-a10-apb1-mux-clk";
228 reg = <0x01c20058 0x4>;
229 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
230 clock-output-names = "apb1_mux";
233 apb1: apb1@01c20058 {
235 compatible = "allwinner,sun4i-a10-apb1-clk";
236 reg = <0x01c20058 0x4>;
237 clocks = <&apb1_mux>;
238 clock-output-names = "apb1";
241 apb1_gates: clk@01c2006c {
243 compatible = "allwinner,sun7i-a20-apb1-gates-clk";
244 reg = <0x01c2006c 0x4>;
246 clock-output-names = "apb1_i2c0", "apb1_i2c1",
247 "apb1_i2c2", "apb1_i2c3", "apb1_can",
248 "apb1_scr", "apb1_ps20", "apb1_ps21",
249 "apb1_i2c4", "apb1_uart0", "apb1_uart1",
250 "apb1_uart2", "apb1_uart3", "apb1_uart4",
251 "apb1_uart5", "apb1_uart6", "apb1_uart7";
254 nand_clk: clk@01c20080 {
256 compatible = "allwinner,sun4i-a10-mod0-clk";
257 reg = <0x01c20080 0x4>;
258 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
259 clock-output-names = "nand";
262 ms_clk: clk@01c20084 {
264 compatible = "allwinner,sun4i-a10-mod0-clk";
265 reg = <0x01c20084 0x4>;
266 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
267 clock-output-names = "ms";
270 mmc0_clk: clk@01c20088 {
272 compatible = "allwinner,sun4i-a10-mod0-clk";
273 reg = <0x01c20088 0x4>;
274 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
275 clock-output-names = "mmc0";
278 mmc1_clk: clk@01c2008c {
280 compatible = "allwinner,sun4i-a10-mod0-clk";
281 reg = <0x01c2008c 0x4>;
282 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
283 clock-output-names = "mmc1";
286 mmc2_clk: clk@01c20090 {
288 compatible = "allwinner,sun4i-a10-mod0-clk";
289 reg = <0x01c20090 0x4>;
290 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
291 clock-output-names = "mmc2";
294 mmc3_clk: clk@01c20094 {
296 compatible = "allwinner,sun4i-a10-mod0-clk";
297 reg = <0x01c20094 0x4>;
298 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
299 clock-output-names = "mmc3";
302 ts_clk: clk@01c20098 {
304 compatible = "allwinner,sun4i-a10-mod0-clk";
305 reg = <0x01c20098 0x4>;
306 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
307 clock-output-names = "ts";
310 ss_clk: clk@01c2009c {
312 compatible = "allwinner,sun4i-a10-mod0-clk";
313 reg = <0x01c2009c 0x4>;
314 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
315 clock-output-names = "ss";
318 spi0_clk: clk@01c200a0 {
320 compatible = "allwinner,sun4i-a10-mod0-clk";
321 reg = <0x01c200a0 0x4>;
322 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
323 clock-output-names = "spi0";
326 spi1_clk: clk@01c200a4 {
328 compatible = "allwinner,sun4i-a10-mod0-clk";
329 reg = <0x01c200a4 0x4>;
330 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
331 clock-output-names = "spi1";
334 spi2_clk: clk@01c200a8 {
336 compatible = "allwinner,sun4i-a10-mod0-clk";
337 reg = <0x01c200a8 0x4>;
338 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
339 clock-output-names = "spi2";
342 pata_clk: clk@01c200ac {
344 compatible = "allwinner,sun4i-a10-mod0-clk";
345 reg = <0x01c200ac 0x4>;
346 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
347 clock-output-names = "pata";
350 ir0_clk: clk@01c200b0 {
352 compatible = "allwinner,sun4i-a10-mod0-clk";
353 reg = <0x01c200b0 0x4>;
354 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
355 clock-output-names = "ir0";
358 ir1_clk: clk@01c200b4 {
360 compatible = "allwinner,sun4i-a10-mod0-clk";
361 reg = <0x01c200b4 0x4>;
362 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
363 clock-output-names = "ir1";
366 usb_clk: clk@01c200cc {
369 compatible = "allwinner,sun4i-a10-usb-clk";
370 reg = <0x01c200cc 0x4>;
372 clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
375 spi3_clk: clk@01c200d4 {
377 compatible = "allwinner,sun4i-a10-mod0-clk";
378 reg = <0x01c200d4 0x4>;
379 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
380 clock-output-names = "spi3";
383 mbus_clk: clk@01c2015c {
385 compatible = "allwinner,sun5i-a13-mbus-clk";
386 reg = <0x01c2015c 0x4>;
387 clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
388 clock-output-names = "mbus";
392 * The following two are dummy clocks, placeholders used in the gmac_tx
393 * clock. The gmac driver will choose one parent depending on the PHY
394 * interface mode, using clk_set_rate auto-reparenting.
395 * The actual TX clock rate is not controlled by the gmac_tx clock.
397 mii_phy_tx_clk: clk@2 {
399 compatible = "fixed-clock";
400 clock-frequency = <25000000>;
401 clock-output-names = "mii_phy_tx";
404 gmac_int_tx_clk: clk@3 {
406 compatible = "fixed-clock";
407 clock-frequency = <125000000>;
408 clock-output-names = "gmac_int_tx";
411 gmac_tx_clk: clk@01c20164 {
413 compatible = "allwinner,sun7i-a20-gmac-clk";
414 reg = <0x01c20164 0x4>;
415 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
416 clock-output-names = "gmac_tx";
420 * Dummy clock used by output clocks
424 compatible = "fixed-factor-clock";
428 clock-output-names = "osc24M_32k";
431 clk_out_a: clk@01c201f0 {
433 compatible = "allwinner,sun7i-a20-out-clk";
434 reg = <0x01c201f0 0x4>;
435 clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
436 clock-output-names = "clk_out_a";
439 clk_out_b: clk@01c201f4 {
441 compatible = "allwinner,sun7i-a20-out-clk";
442 reg = <0x01c201f4 0x4>;
443 clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
444 clock-output-names = "clk_out_b";
449 compatible = "simple-bus";
450 #address-cells = <1>;
454 nmi_intc: interrupt-controller@01c00030 {
455 compatible = "allwinner,sun7i-a20-sc-nmi";
456 interrupt-controller;
457 #interrupt-cells = <2>;
458 reg = <0x01c00030 0x0c>;
459 interrupts = <0 0 4>;
462 dma: dma-controller@01c02000 {
463 compatible = "allwinner,sun4i-a10-dma";
464 reg = <0x01c02000 0x1000>;
465 interrupts = <0 27 4>;
466 clocks = <&ahb_gates 6>;
471 compatible = "allwinner,sun4i-a10-spi";
472 reg = <0x01c05000 0x1000>;
473 interrupts = <0 10 4>;
474 clocks = <&ahb_gates 20>, <&spi0_clk>;
475 clock-names = "ahb", "mod";
476 dmas = <&dma 1 27>, <&dma 1 26>;
477 dma-names = "rx", "tx";
479 #address-cells = <1>;
484 compatible = "allwinner,sun4i-a10-spi";
485 reg = <0x01c06000 0x1000>;
486 interrupts = <0 11 4>;
487 clocks = <&ahb_gates 21>, <&spi1_clk>;
488 clock-names = "ahb", "mod";
489 dmas = <&dma 1 9>, <&dma 1 8>;
490 dma-names = "rx", "tx";
492 #address-cells = <1>;
496 emac: ethernet@01c0b000 {
497 compatible = "allwinner,sun4i-a10-emac";
498 reg = <0x01c0b000 0x1000>;
499 interrupts = <0 55 4>;
500 clocks = <&ahb_gates 17>;
505 compatible = "allwinner,sun4i-a10-mdio";
506 reg = <0x01c0b080 0x14>;
508 #address-cells = <1>;
513 compatible = "allwinner,sun5i-a13-mmc";
514 reg = <0x01c0f000 0x1000>;
515 clocks = <&ahb_gates 8>, <&mmc0_clk>;
516 clock-names = "ahb", "mmc";
517 interrupts = <0 32 4>;
522 compatible = "allwinner,sun5i-a13-mmc";
523 reg = <0x01c10000 0x1000>;
524 clocks = <&ahb_gates 9>, <&mmc1_clk>;
525 clock-names = "ahb", "mmc";
526 interrupts = <0 33 4>;
531 compatible = "allwinner,sun5i-a13-mmc";
532 reg = <0x01c11000 0x1000>;
533 clocks = <&ahb_gates 10>, <&mmc2_clk>;
534 clock-names = "ahb", "mmc";
535 interrupts = <0 34 4>;
540 compatible = "allwinner,sun5i-a13-mmc";
541 reg = <0x01c12000 0x1000>;
542 clocks = <&ahb_gates 11>, <&mmc3_clk>;
543 clock-names = "ahb", "mmc";
544 interrupts = <0 35 4>;
548 usbphy: phy@01c13400 {
550 compatible = "allwinner,sun7i-a20-usb-phy";
551 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
552 reg-names = "phy_ctrl", "pmu1", "pmu2";
553 clocks = <&usb_clk 8>;
554 clock-names = "usb_phy";
555 resets = <&usb_clk 1>, <&usb_clk 2>;
556 reset-names = "usb1_reset", "usb2_reset";
560 ehci0: usb@01c14000 {
561 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
562 reg = <0x01c14000 0x100>;
563 interrupts = <0 39 4>;
564 clocks = <&ahb_gates 1>;
570 ohci0: usb@01c14400 {
571 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
572 reg = <0x01c14400 0x100>;
573 interrupts = <0 64 4>;
574 clocks = <&usb_clk 6>, <&ahb_gates 2>;
581 compatible = "allwinner,sun4i-a10-spi";
582 reg = <0x01c17000 0x1000>;
583 interrupts = <0 12 4>;
584 clocks = <&ahb_gates 22>, <&spi2_clk>;
585 clock-names = "ahb", "mod";
586 dmas = <&dma 1 29>, <&dma 1 28>;
587 dma-names = "rx", "tx";
589 #address-cells = <1>;
593 ahci: sata@01c18000 {
594 compatible = "allwinner,sun4i-a10-ahci";
595 reg = <0x01c18000 0x1000>;
596 interrupts = <0 56 4>;
597 clocks = <&pll6 0>, <&ahb_gates 25>;
601 ehci1: usb@01c1c000 {
602 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
603 reg = <0x01c1c000 0x100>;
604 interrupts = <0 40 4>;
605 clocks = <&ahb_gates 3>;
611 ohci1: usb@01c1c400 {
612 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
613 reg = <0x01c1c400 0x100>;
614 interrupts = <0 65 4>;
615 clocks = <&usb_clk 7>, <&ahb_gates 4>;
622 compatible = "allwinner,sun4i-a10-spi";
623 reg = <0x01c1f000 0x1000>;
624 interrupts = <0 50 4>;
625 clocks = <&ahb_gates 23>, <&spi3_clk>;
626 clock-names = "ahb", "mod";
627 dmas = <&dma 1 31>, <&dma 1 30>;
628 dma-names = "rx", "tx";
630 #address-cells = <1>;
634 pio: pinctrl@01c20800 {
635 compatible = "allwinner,sun7i-a20-pinctrl";
636 reg = <0x01c20800 0x400>;
637 interrupts = <0 28 4>;
638 clocks = <&apb0_gates 5>;
640 interrupt-controller;
641 #interrupt-cells = <2>;
645 pwm0_pins_a: pwm0@0 {
646 allwinner,pins = "PB2";
647 allwinner,function = "pwm";
648 allwinner,drive = <0>;
649 allwinner,pull = <0>;
652 pwm1_pins_a: pwm1@0 {
653 allwinner,pins = "PI3";
654 allwinner,function = "pwm";
655 allwinner,drive = <0>;
656 allwinner,pull = <0>;
659 uart0_pins_a: uart0@0 {
660 allwinner,pins = "PB22", "PB23";
661 allwinner,function = "uart0";
662 allwinner,drive = <0>;
663 allwinner,pull = <0>;
666 uart2_pins_a: uart2@0 {
667 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
668 allwinner,function = "uart2";
669 allwinner,drive = <0>;
670 allwinner,pull = <0>;
673 uart3_pins_a: uart3@0 {
674 allwinner,pins = "PG6", "PG7", "PG8", "PG9";
675 allwinner,function = "uart3";
676 allwinner,drive = <0>;
677 allwinner,pull = <0>;
680 uart3_pins_b: uart3@1 {
681 allwinner,pins = "PH0", "PH1";
682 allwinner,function = "uart3";
683 allwinner,drive = <0>;
684 allwinner,pull = <0>;
687 uart4_pins_a: uart4@0 {
688 allwinner,pins = "PG10", "PG11";
689 allwinner,function = "uart4";
690 allwinner,drive = <0>;
691 allwinner,pull = <0>;
694 uart5_pins_a: uart5@0 {
695 allwinner,pins = "PI10", "PI11";
696 allwinner,function = "uart5";
697 allwinner,drive = <0>;
698 allwinner,pull = <0>;
701 uart6_pins_a: uart6@0 {
702 allwinner,pins = "PI12", "PI13";
703 allwinner,function = "uart6";
704 allwinner,drive = <0>;
705 allwinner,pull = <0>;
708 uart7_pins_a: uart7@0 {
709 allwinner,pins = "PI20", "PI21";
710 allwinner,function = "uart7";
711 allwinner,drive = <0>;
712 allwinner,pull = <0>;
715 i2c0_pins_a: i2c0@0 {
716 allwinner,pins = "PB0", "PB1";
717 allwinner,function = "i2c0";
718 allwinner,drive = <0>;
719 allwinner,pull = <0>;
722 i2c1_pins_a: i2c1@0 {
723 allwinner,pins = "PB18", "PB19";
724 allwinner,function = "i2c1";
725 allwinner,drive = <0>;
726 allwinner,pull = <0>;
729 i2c2_pins_a: i2c2@0 {
730 allwinner,pins = "PB20", "PB21";
731 allwinner,function = "i2c2";
732 allwinner,drive = <0>;
733 allwinner,pull = <0>;
736 i2c3_pins_a: i2c3@0 {
737 allwinner,pins = "PI0", "PI1";
738 allwinner,function = "i2c3";
739 allwinner,drive = <0>;
740 allwinner,pull = <0>;
743 emac_pins_a: emac0@0 {
744 allwinner,pins = "PA0", "PA1", "PA2",
745 "PA3", "PA4", "PA5", "PA6",
746 "PA7", "PA8", "PA9", "PA10",
747 "PA11", "PA12", "PA13", "PA14",
749 allwinner,function = "emac";
750 allwinner,drive = <0>;
751 allwinner,pull = <0>;
754 clk_out_a_pins_a: clk_out_a@0 {
755 allwinner,pins = "PI12";
756 allwinner,function = "clk_out_a";
757 allwinner,drive = <0>;
758 allwinner,pull = <0>;
761 clk_out_b_pins_a: clk_out_b@0 {
762 allwinner,pins = "PI13";
763 allwinner,function = "clk_out_b";
764 allwinner,drive = <0>;
765 allwinner,pull = <0>;
768 gmac_pins_mii_a: gmac_mii@0 {
769 allwinner,pins = "PA0", "PA1", "PA2",
770 "PA3", "PA4", "PA5", "PA6",
771 "PA7", "PA8", "PA9", "PA10",
772 "PA11", "PA12", "PA13", "PA14",
774 allwinner,function = "gmac";
775 allwinner,drive = <0>;
776 allwinner,pull = <0>;
779 gmac_pins_rgmii_a: gmac_rgmii@0 {
780 allwinner,pins = "PA0", "PA1", "PA2",
781 "PA3", "PA4", "PA5", "PA6",
782 "PA7", "PA8", "PA10",
783 "PA11", "PA12", "PA13",
785 allwinner,function = "gmac";
787 * data lines in RGMII mode use DDR mode
788 * and need a higher signal drive strength
790 allwinner,drive = <3>;
791 allwinner,pull = <0>;
794 spi0_pins_a: spi0@0 {
795 allwinner,pins = "PI10", "PI11", "PI12", "PI13", "PI14";
796 allwinner,function = "spi0";
797 allwinner,drive = <0>;
798 allwinner,pull = <0>;
801 spi1_pins_a: spi1@0 {
802 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
803 allwinner,function = "spi1";
804 allwinner,drive = <0>;
805 allwinner,pull = <0>;
808 spi2_pins_a: spi2@0 {
809 allwinner,pins = "PC19", "PC20", "PC21", "PC22";
810 allwinner,function = "spi2";
811 allwinner,drive = <0>;
812 allwinner,pull = <0>;
815 spi2_pins_b: spi2@1 {
816 allwinner,pins = "PB14", "PB15", "PB16", "PB17";
817 allwinner,function = "spi2";
818 allwinner,drive = <0>;
819 allwinner,pull = <0>;
822 mmc0_pins_a: mmc0@0 {
823 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
824 allwinner,function = "mmc0";
825 allwinner,drive = <2>;
826 allwinner,pull = <0>;
829 mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
830 allwinner,pins = "PH1";
831 allwinner,function = "gpio_in";
832 allwinner,drive = <0>;
833 allwinner,pull = <1>;
836 mmc2_pins_a: mmc2@0 {
837 allwinner,pins = "PC6","PC7","PC8","PC9","PC10","PC11";
838 allwinner,function = "mmc2";
839 allwinner,drive = <2>;
840 allwinner,pull = <1>;
843 mmc3_pins_a: mmc3@0 {
844 allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9";
845 allwinner,function = "mmc3";
846 allwinner,drive = <2>;
847 allwinner,pull = <0>;
851 allwinner,pins = "PB3","PB4";
852 allwinner,function = "ir0";
853 allwinner,drive = <0>;
854 allwinner,pull = <0>;
858 allwinner,pins = "PB22","PB23";
859 allwinner,function = "ir1";
860 allwinner,drive = <0>;
861 allwinner,pull = <0>;
866 compatible = "allwinner,sun4i-a10-timer";
867 reg = <0x01c20c00 0x90>;
868 interrupts = <0 22 4>,
877 wdt: watchdog@01c20c90 {
878 compatible = "allwinner,sun4i-a10-wdt";
879 reg = <0x01c20c90 0x10>;
883 compatible = "allwinner,sun7i-a20-rtc";
884 reg = <0x01c20d00 0x20>;
885 interrupts = <0 24 4>;
889 compatible = "allwinner,sun7i-a20-pwm";
890 reg = <0x01c20e00 0xc>;
897 compatible = "allwinner,sun4i-a10-ir";
898 clocks = <&apb0_gates 6>, <&ir0_clk>;
899 clock-names = "apb", "ir";
900 interrupts = <0 5 4>;
901 reg = <0x01c21800 0x40>;
906 compatible = "allwinner,sun4i-a10-ir";
907 clocks = <&apb0_gates 7>, <&ir1_clk>;
908 clock-names = "apb", "ir";
909 interrupts = <0 6 4>;
910 reg = <0x01c21c00 0x40>;
914 sid: eeprom@01c23800 {
915 compatible = "allwinner,sun7i-a20-sid";
916 reg = <0x01c23800 0x200>;
920 compatible = "allwinner,sun4i-a10-ts";
921 reg = <0x01c25000 0x100>;
922 interrupts = <0 29 4>;
925 uart0: serial@01c28000 {
926 compatible = "snps,dw-apb-uart";
927 reg = <0x01c28000 0x400>;
928 interrupts = <0 1 4>;
931 clocks = <&apb1_gates 16>;
935 uart1: serial@01c28400 {
936 compatible = "snps,dw-apb-uart";
937 reg = <0x01c28400 0x400>;
938 interrupts = <0 2 4>;
941 clocks = <&apb1_gates 17>;
945 uart2: serial@01c28800 {
946 compatible = "snps,dw-apb-uart";
947 reg = <0x01c28800 0x400>;
948 interrupts = <0 3 4>;
951 clocks = <&apb1_gates 18>;
955 uart3: serial@01c28c00 {
956 compatible = "snps,dw-apb-uart";
957 reg = <0x01c28c00 0x400>;
958 interrupts = <0 4 4>;
961 clocks = <&apb1_gates 19>;
965 uart4: serial@01c29000 {
966 compatible = "snps,dw-apb-uart";
967 reg = <0x01c29000 0x400>;
968 interrupts = <0 17 4>;
971 clocks = <&apb1_gates 20>;
975 uart5: serial@01c29400 {
976 compatible = "snps,dw-apb-uart";
977 reg = <0x01c29400 0x400>;
978 interrupts = <0 18 4>;
981 clocks = <&apb1_gates 21>;
985 uart6: serial@01c29800 {
986 compatible = "snps,dw-apb-uart";
987 reg = <0x01c29800 0x400>;
988 interrupts = <0 19 4>;
991 clocks = <&apb1_gates 22>;
995 uart7: serial@01c29c00 {
996 compatible = "snps,dw-apb-uart";
997 reg = <0x01c29c00 0x400>;
998 interrupts = <0 20 4>;
1001 clocks = <&apb1_gates 23>;
1002 status = "disabled";
1005 i2c0: i2c@01c2ac00 {
1006 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
1007 reg = <0x01c2ac00 0x400>;
1008 interrupts = <0 7 4>;
1009 clocks = <&apb1_gates 0>;
1010 status = "disabled";
1011 #address-cells = <1>;
1015 i2c1: i2c@01c2b000 {
1016 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
1017 reg = <0x01c2b000 0x400>;
1018 interrupts = <0 8 4>;
1019 clocks = <&apb1_gates 1>;
1020 status = "disabled";
1021 #address-cells = <1>;
1025 i2c2: i2c@01c2b400 {
1026 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
1027 reg = <0x01c2b400 0x400>;
1028 interrupts = <0 9 4>;
1029 clocks = <&apb1_gates 2>;
1030 status = "disabled";
1031 #address-cells = <1>;
1035 i2c3: i2c@01c2b800 {
1036 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
1037 reg = <0x01c2b800 0x400>;
1038 interrupts = <0 88 4>;
1039 clocks = <&apb1_gates 3>;
1040 status = "disabled";
1041 #address-cells = <1>;
1045 i2c4: i2c@01c2c000 {
1046 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
1047 reg = <0x01c2c000 0x400>;
1048 interrupts = <0 89 4>;
1049 clocks = <&apb1_gates 15>;
1050 status = "disabled";
1051 #address-cells = <1>;
1055 gmac: ethernet@01c50000 {
1056 compatible = "allwinner,sun7i-a20-gmac";
1057 reg = <0x01c50000 0x10000>;
1058 interrupts = <0 85 4>;
1059 interrupt-names = "macirq";
1060 clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
1061 clock-names = "stmmaceth", "allwinner_gmac_tx";
1064 snps,force_sf_dma_mode;
1065 status = "disabled";
1066 #address-cells = <1>;
1071 compatible = "allwinner,sun7i-a20-hstimer";
1072 reg = <0x01c60000 0x1000>;
1073 interrupts = <0 81 4>,
1077 clocks = <&ahb_gates 28>;
1080 gic: interrupt-controller@01c81000 {
1081 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
1082 reg = <0x01c81000 0x1000>,
1083 <0x01c82000 0x1000>,
1084 <0x01c84000 0x2000>,
1085 <0x01c86000 0x2000>;
1086 interrupt-controller;
1087 #interrupt-cells = <3>;
1088 interrupts = <1 9 0xf04>;