2 * Copyright 2013 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
50 /include/ "skeleton.dtsi"
53 interrupt-parent = <&gic>;
73 compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
74 allwinner,pipeline = "de_be0-lcd0-hdmi";
75 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
86 compatible = "arm,cortex-a7";
92 compatible = "arm,cortex-a7";
99 reg = <0x40000000 0x80000000>;
103 compatible = "arm,armv7-timer";
104 interrupts = <1 13 0xf08>,
111 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
112 interrupts = <0 120 4>,
117 #address-cells = <1>;
121 osc24M: clk@01c20050 {
123 compatible = "allwinner,sun4i-a10-osc-clk";
124 reg = <0x01c20050 0x4>;
125 clock-frequency = <24000000>;
126 clock-output-names = "osc24M";
131 compatible = "fixed-clock";
132 clock-frequency = <32768>;
133 clock-output-names = "osc32k";
138 compatible = "allwinner,sun4i-a10-pll1-clk";
139 reg = <0x01c20000 0x4>;
141 clock-output-names = "pll1";
146 compatible = "allwinner,sun7i-a20-pll4-clk";
147 reg = <0x01c20018 0x4>;
149 clock-output-names = "pll4";
154 compatible = "allwinner,sun4i-a10-pll5-clk";
155 reg = <0x01c20020 0x4>;
157 clock-output-names = "pll5_ddr", "pll5_other";
162 compatible = "allwinner,sun4i-a10-pll6-clk";
163 reg = <0x01c20028 0x4>;
165 clock-output-names = "pll6_sata", "pll6_other", "pll6";
170 compatible = "allwinner,sun7i-a20-pll4-clk";
171 reg = <0x01c20040 0x4>;
173 clock-output-names = "pll8";
178 compatible = "allwinner,sun4i-a10-cpu-clk";
179 reg = <0x01c20054 0x4>;
180 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
181 clock-output-names = "cpu";
186 compatible = "allwinner,sun4i-a10-axi-clk";
187 reg = <0x01c20054 0x4>;
189 clock-output-names = "axi";
194 compatible = "allwinner,sun4i-a10-ahb-clk";
195 reg = <0x01c20054 0x4>;
197 clock-output-names = "ahb";
200 ahb_gates: clk@01c20060 {
202 compatible = "allwinner,sun7i-a20-ahb-gates-clk";
203 reg = <0x01c20060 0x8>;
205 clock-output-names = "ahb_usb0", "ahb_ehci0",
206 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
207 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
208 "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
209 "ahb_nand", "ahb_sdram", "ahb_ace",
210 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
211 "ahb_spi2", "ahb_spi3", "ahb_sata",
212 "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
213 "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
214 "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
215 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
216 "ahb_de_fe1", "ahb_gmac", "ahb_mp",
220 apb0: apb0@01c20054 {
222 compatible = "allwinner,sun4i-a10-apb0-clk";
223 reg = <0x01c20054 0x4>;
225 clock-output-names = "apb0";
228 apb0_gates: clk@01c20068 {
230 compatible = "allwinner,sun7i-a20-apb0-gates-clk";
231 reg = <0x01c20068 0x4>;
233 clock-output-names = "apb0_codec", "apb0_spdif",
234 "apb0_ac97", "apb0_iis0", "apb0_iis1",
235 "apb0_pio", "apb0_ir0", "apb0_ir1",
236 "apb0_iis2", "apb0_keypad";
239 apb1_mux: apb1_mux@01c20058 {
241 compatible = "allwinner,sun4i-a10-apb1-mux-clk";
242 reg = <0x01c20058 0x4>;
243 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
244 clock-output-names = "apb1_mux";
247 apb1: apb1@01c20058 {
249 compatible = "allwinner,sun4i-a10-apb1-clk";
250 reg = <0x01c20058 0x4>;
251 clocks = <&apb1_mux>;
252 clock-output-names = "apb1";
255 apb1_gates: clk@01c2006c {
257 compatible = "allwinner,sun7i-a20-apb1-gates-clk";
258 reg = <0x01c2006c 0x4>;
260 clock-output-names = "apb1_i2c0", "apb1_i2c1",
261 "apb1_i2c2", "apb1_i2c3", "apb1_can",
262 "apb1_scr", "apb1_ps20", "apb1_ps21",
263 "apb1_i2c4", "apb1_uart0", "apb1_uart1",
264 "apb1_uart2", "apb1_uart3", "apb1_uart4",
265 "apb1_uart5", "apb1_uart6", "apb1_uart7";
268 nand_clk: clk@01c20080 {
270 compatible = "allwinner,sun4i-a10-mod0-clk";
271 reg = <0x01c20080 0x4>;
272 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
273 clock-output-names = "nand";
276 ms_clk: clk@01c20084 {
278 compatible = "allwinner,sun4i-a10-mod0-clk";
279 reg = <0x01c20084 0x4>;
280 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
281 clock-output-names = "ms";
284 mmc0_clk: clk@01c20088 {
286 compatible = "allwinner,sun4i-a10-mod0-clk";
287 reg = <0x01c20088 0x4>;
288 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
289 clock-output-names = "mmc0";
292 mmc1_clk: clk@01c2008c {
294 compatible = "allwinner,sun4i-a10-mod0-clk";
295 reg = <0x01c2008c 0x4>;
296 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
297 clock-output-names = "mmc1";
300 mmc2_clk: clk@01c20090 {
302 compatible = "allwinner,sun4i-a10-mod0-clk";
303 reg = <0x01c20090 0x4>;
304 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
305 clock-output-names = "mmc2";
308 mmc3_clk: clk@01c20094 {
310 compatible = "allwinner,sun4i-a10-mod0-clk";
311 reg = <0x01c20094 0x4>;
312 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
313 clock-output-names = "mmc3";
316 ts_clk: clk@01c20098 {
318 compatible = "allwinner,sun4i-a10-mod0-clk";
319 reg = <0x01c20098 0x4>;
320 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
321 clock-output-names = "ts";
324 ss_clk: clk@01c2009c {
326 compatible = "allwinner,sun4i-a10-mod0-clk";
327 reg = <0x01c2009c 0x4>;
328 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
329 clock-output-names = "ss";
332 spi0_clk: clk@01c200a0 {
334 compatible = "allwinner,sun4i-a10-mod0-clk";
335 reg = <0x01c200a0 0x4>;
336 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
337 clock-output-names = "spi0";
340 spi1_clk: clk@01c200a4 {
342 compatible = "allwinner,sun4i-a10-mod0-clk";
343 reg = <0x01c200a4 0x4>;
344 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
345 clock-output-names = "spi1";
348 spi2_clk: clk@01c200a8 {
350 compatible = "allwinner,sun4i-a10-mod0-clk";
351 reg = <0x01c200a8 0x4>;
352 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
353 clock-output-names = "spi2";
356 pata_clk: clk@01c200ac {
358 compatible = "allwinner,sun4i-a10-mod0-clk";
359 reg = <0x01c200ac 0x4>;
360 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
361 clock-output-names = "pata";
364 ir0_clk: clk@01c200b0 {
366 compatible = "allwinner,sun4i-a10-mod0-clk";
367 reg = <0x01c200b0 0x4>;
368 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
369 clock-output-names = "ir0";
372 ir1_clk: clk@01c200b4 {
374 compatible = "allwinner,sun4i-a10-mod0-clk";
375 reg = <0x01c200b4 0x4>;
376 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
377 clock-output-names = "ir1";
380 usb_clk: clk@01c200cc {
383 compatible = "allwinner,sun4i-a10-usb-clk";
384 reg = <0x01c200cc 0x4>;
386 clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
389 spi3_clk: clk@01c200d4 {
391 compatible = "allwinner,sun4i-a10-mod0-clk";
392 reg = <0x01c200d4 0x4>;
393 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
394 clock-output-names = "spi3";
397 mbus_clk: clk@01c2015c {
399 compatible = "allwinner,sun5i-a13-mbus-clk";
400 reg = <0x01c2015c 0x4>;
401 clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
402 clock-output-names = "mbus";
406 * The following two are dummy clocks, placeholders used in the gmac_tx
407 * clock. The gmac driver will choose one parent depending on the PHY
408 * interface mode, using clk_set_rate auto-reparenting.
409 * The actual TX clock rate is not controlled by the gmac_tx clock.
411 mii_phy_tx_clk: clk@2 {
413 compatible = "fixed-clock";
414 clock-frequency = <25000000>;
415 clock-output-names = "mii_phy_tx";
418 gmac_int_tx_clk: clk@3 {
420 compatible = "fixed-clock";
421 clock-frequency = <125000000>;
422 clock-output-names = "gmac_int_tx";
425 gmac_tx_clk: clk@01c20164 {
427 compatible = "allwinner,sun7i-a20-gmac-clk";
428 reg = <0x01c20164 0x4>;
429 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
430 clock-output-names = "gmac_tx";
434 * Dummy clock used by output clocks
438 compatible = "fixed-factor-clock";
442 clock-output-names = "osc24M_32k";
445 clk_out_a: clk@01c201f0 {
447 compatible = "allwinner,sun7i-a20-out-clk";
448 reg = <0x01c201f0 0x4>;
449 clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
450 clock-output-names = "clk_out_a";
453 clk_out_b: clk@01c201f4 {
455 compatible = "allwinner,sun7i-a20-out-clk";
456 reg = <0x01c201f4 0x4>;
457 clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
458 clock-output-names = "clk_out_b";
463 compatible = "simple-bus";
464 #address-cells = <1>;
468 nmi_intc: interrupt-controller@01c00030 {
469 compatible = "allwinner,sun7i-a20-sc-nmi";
470 interrupt-controller;
471 #interrupt-cells = <2>;
472 reg = <0x01c00030 0x0c>;
473 interrupts = <0 0 4>;
476 dma: dma-controller@01c02000 {
477 compatible = "allwinner,sun4i-a10-dma";
478 reg = <0x01c02000 0x1000>;
479 interrupts = <0 27 4>;
480 clocks = <&ahb_gates 6>;
485 compatible = "allwinner,sun4i-a10-spi";
486 reg = <0x01c05000 0x1000>;
487 interrupts = <0 10 4>;
488 clocks = <&ahb_gates 20>, <&spi0_clk>;
489 clock-names = "ahb", "mod";
490 dmas = <&dma 1 27>, <&dma 1 26>;
491 dma-names = "rx", "tx";
493 #address-cells = <1>;
498 compatible = "allwinner,sun4i-a10-spi";
499 reg = <0x01c06000 0x1000>;
500 interrupts = <0 11 4>;
501 clocks = <&ahb_gates 21>, <&spi1_clk>;
502 clock-names = "ahb", "mod";
503 dmas = <&dma 1 9>, <&dma 1 8>;
504 dma-names = "rx", "tx";
506 #address-cells = <1>;
510 emac: ethernet@01c0b000 {
511 compatible = "allwinner,sun4i-a10-emac";
512 reg = <0x01c0b000 0x1000>;
513 interrupts = <0 55 4>;
514 clocks = <&ahb_gates 17>;
519 compatible = "allwinner,sun4i-a10-mdio";
520 reg = <0x01c0b080 0x14>;
522 #address-cells = <1>;
527 compatible = "allwinner,sun5i-a13-mmc";
528 reg = <0x01c0f000 0x1000>;
529 clocks = <&ahb_gates 8>, <&mmc0_clk>;
530 clock-names = "ahb", "mmc";
531 interrupts = <0 32 4>;
536 compatible = "allwinner,sun5i-a13-mmc";
537 reg = <0x01c10000 0x1000>;
538 clocks = <&ahb_gates 9>, <&mmc1_clk>;
539 clock-names = "ahb", "mmc";
540 interrupts = <0 33 4>;
545 compatible = "allwinner,sun5i-a13-mmc";
546 reg = <0x01c11000 0x1000>;
547 clocks = <&ahb_gates 10>, <&mmc2_clk>;
548 clock-names = "ahb", "mmc";
549 interrupts = <0 34 4>;
554 compatible = "allwinner,sun5i-a13-mmc";
555 reg = <0x01c12000 0x1000>;
556 clocks = <&ahb_gates 11>, <&mmc3_clk>;
557 clock-names = "ahb", "mmc";
558 interrupts = <0 35 4>;
562 usbphy: phy@01c13400 {
564 compatible = "allwinner,sun7i-a20-usb-phy";
565 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
566 reg-names = "phy_ctrl", "pmu1", "pmu2";
567 clocks = <&usb_clk 8>;
568 clock-names = "usb_phy";
569 resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
570 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
574 ehci0: usb@01c14000 {
575 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
576 reg = <0x01c14000 0x100>;
577 interrupts = <0 39 4>;
578 clocks = <&ahb_gates 1>;
584 ohci0: usb@01c14400 {
585 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
586 reg = <0x01c14400 0x100>;
587 interrupts = <0 64 4>;
588 clocks = <&usb_clk 6>, <&ahb_gates 2>;
595 compatible = "allwinner,sun4i-a10-spi";
596 reg = <0x01c17000 0x1000>;
597 interrupts = <0 12 4>;
598 clocks = <&ahb_gates 22>, <&spi2_clk>;
599 clock-names = "ahb", "mod";
600 dmas = <&dma 1 29>, <&dma 1 28>;
601 dma-names = "rx", "tx";
603 #address-cells = <1>;
607 ahci: sata@01c18000 {
608 compatible = "allwinner,sun4i-a10-ahci";
609 reg = <0x01c18000 0x1000>;
610 interrupts = <0 56 4>;
611 clocks = <&pll6 0>, <&ahb_gates 25>;
615 ehci1: usb@01c1c000 {
616 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
617 reg = <0x01c1c000 0x100>;
618 interrupts = <0 40 4>;
619 clocks = <&ahb_gates 3>;
625 ohci1: usb@01c1c400 {
626 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
627 reg = <0x01c1c400 0x100>;
628 interrupts = <0 65 4>;
629 clocks = <&usb_clk 7>, <&ahb_gates 4>;
636 compatible = "allwinner,sun4i-a10-spi";
637 reg = <0x01c1f000 0x1000>;
638 interrupts = <0 50 4>;
639 clocks = <&ahb_gates 23>, <&spi3_clk>;
640 clock-names = "ahb", "mod";
641 dmas = <&dma 1 31>, <&dma 1 30>;
642 dma-names = "rx", "tx";
644 #address-cells = <1>;
648 pio: pinctrl@01c20800 {
649 compatible = "allwinner,sun7i-a20-pinctrl";
650 reg = <0x01c20800 0x400>;
651 interrupts = <0 28 4>;
652 clocks = <&apb0_gates 5>;
654 interrupt-controller;
655 #interrupt-cells = <2>;
659 pwm0_pins_a: pwm0@0 {
660 allwinner,pins = "PB2";
661 allwinner,function = "pwm";
662 allwinner,drive = <0>;
663 allwinner,pull = <0>;
666 pwm1_pins_a: pwm1@0 {
667 allwinner,pins = "PI3";
668 allwinner,function = "pwm";
669 allwinner,drive = <0>;
670 allwinner,pull = <0>;
673 uart0_pins_a: uart0@0 {
674 allwinner,pins = "PB22", "PB23";
675 allwinner,function = "uart0";
676 allwinner,drive = <0>;
677 allwinner,pull = <0>;
680 uart2_pins_a: uart2@0 {
681 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
682 allwinner,function = "uart2";
683 allwinner,drive = <0>;
684 allwinner,pull = <0>;
687 uart3_pins_a: uart3@0 {
688 allwinner,pins = "PG6", "PG7", "PG8", "PG9";
689 allwinner,function = "uart3";
690 allwinner,drive = <0>;
691 allwinner,pull = <0>;
694 uart3_pins_b: uart3@1 {
695 allwinner,pins = "PH0", "PH1";
696 allwinner,function = "uart3";
697 allwinner,drive = <0>;
698 allwinner,pull = <0>;
701 uart4_pins_a: uart4@0 {
702 allwinner,pins = "PG10", "PG11";
703 allwinner,function = "uart4";
704 allwinner,drive = <0>;
705 allwinner,pull = <0>;
708 uart5_pins_a: uart5@0 {
709 allwinner,pins = "PI10", "PI11";
710 allwinner,function = "uart5";
711 allwinner,drive = <0>;
712 allwinner,pull = <0>;
715 uart6_pins_a: uart6@0 {
716 allwinner,pins = "PI12", "PI13";
717 allwinner,function = "uart6";
718 allwinner,drive = <0>;
719 allwinner,pull = <0>;
722 uart7_pins_a: uart7@0 {
723 allwinner,pins = "PI20", "PI21";
724 allwinner,function = "uart7";
725 allwinner,drive = <0>;
726 allwinner,pull = <0>;
729 i2c0_pins_a: i2c0@0 {
730 allwinner,pins = "PB0", "PB1";
731 allwinner,function = "i2c0";
732 allwinner,drive = <0>;
733 allwinner,pull = <0>;
736 i2c1_pins_a: i2c1@0 {
737 allwinner,pins = "PB18", "PB19";
738 allwinner,function = "i2c1";
739 allwinner,drive = <0>;
740 allwinner,pull = <0>;
743 i2c2_pins_a: i2c2@0 {
744 allwinner,pins = "PB20", "PB21";
745 allwinner,function = "i2c2";
746 allwinner,drive = <0>;
747 allwinner,pull = <0>;
750 i2c3_pins_a: i2c3@0 {
751 allwinner,pins = "PI0", "PI1";
752 allwinner,function = "i2c3";
753 allwinner,drive = <0>;
754 allwinner,pull = <0>;
757 emac_pins_a: emac0@0 {
758 allwinner,pins = "PA0", "PA1", "PA2",
759 "PA3", "PA4", "PA5", "PA6",
760 "PA7", "PA8", "PA9", "PA10",
761 "PA11", "PA12", "PA13", "PA14",
763 allwinner,function = "emac";
764 allwinner,drive = <0>;
765 allwinner,pull = <0>;
768 clk_out_a_pins_a: clk_out_a@0 {
769 allwinner,pins = "PI12";
770 allwinner,function = "clk_out_a";
771 allwinner,drive = <0>;
772 allwinner,pull = <0>;
775 clk_out_b_pins_a: clk_out_b@0 {
776 allwinner,pins = "PI13";
777 allwinner,function = "clk_out_b";
778 allwinner,drive = <0>;
779 allwinner,pull = <0>;
782 gmac_pins_mii_a: gmac_mii@0 {
783 allwinner,pins = "PA0", "PA1", "PA2",
784 "PA3", "PA4", "PA5", "PA6",
785 "PA7", "PA8", "PA9", "PA10",
786 "PA11", "PA12", "PA13", "PA14",
788 allwinner,function = "gmac";
789 allwinner,drive = <0>;
790 allwinner,pull = <0>;
793 gmac_pins_rgmii_a: gmac_rgmii@0 {
794 allwinner,pins = "PA0", "PA1", "PA2",
795 "PA3", "PA4", "PA5", "PA6",
796 "PA7", "PA8", "PA10",
797 "PA11", "PA12", "PA13",
799 allwinner,function = "gmac";
801 * data lines in RGMII mode use DDR mode
802 * and need a higher signal drive strength
804 allwinner,drive = <3>;
805 allwinner,pull = <0>;
808 spi0_pins_a: spi0@0 {
809 allwinner,pins = "PI10", "PI11", "PI12", "PI13", "PI14";
810 allwinner,function = "spi0";
811 allwinner,drive = <0>;
812 allwinner,pull = <0>;
815 spi1_pins_a: spi1@0 {
816 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
817 allwinner,function = "spi1";
818 allwinner,drive = <0>;
819 allwinner,pull = <0>;
822 spi2_pins_a: spi2@0 {
823 allwinner,pins = "PC19", "PC20", "PC21", "PC22";
824 allwinner,function = "spi2";
825 allwinner,drive = <0>;
826 allwinner,pull = <0>;
829 spi2_pins_b: spi2@1 {
830 allwinner,pins = "PB14", "PB15", "PB16", "PB17";
831 allwinner,function = "spi2";
832 allwinner,drive = <0>;
833 allwinner,pull = <0>;
836 mmc0_pins_a: mmc0@0 {
837 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
838 allwinner,function = "mmc0";
839 allwinner,drive = <2>;
840 allwinner,pull = <0>;
843 mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
844 allwinner,pins = "PH1";
845 allwinner,function = "gpio_in";
846 allwinner,drive = <0>;
847 allwinner,pull = <1>;
850 mmc2_pins_a: mmc2@0 {
851 allwinner,pins = "PC6","PC7","PC8","PC9","PC10","PC11";
852 allwinner,function = "mmc2";
853 allwinner,drive = <2>;
854 allwinner,pull = <1>;
857 mmc3_pins_a: mmc3@0 {
858 allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9";
859 allwinner,function = "mmc3";
860 allwinner,drive = <2>;
861 allwinner,pull = <0>;
865 allwinner,pins = "PB3","PB4";
866 allwinner,function = "ir0";
867 allwinner,drive = <0>;
868 allwinner,pull = <0>;
872 allwinner,pins = "PB22","PB23";
873 allwinner,function = "ir1";
874 allwinner,drive = <0>;
875 allwinner,pull = <0>;
880 compatible = "allwinner,sun4i-a10-timer";
881 reg = <0x01c20c00 0x90>;
882 interrupts = <0 22 4>,
891 wdt: watchdog@01c20c90 {
892 compatible = "allwinner,sun4i-a10-wdt";
893 reg = <0x01c20c90 0x10>;
897 compatible = "allwinner,sun7i-a20-rtc";
898 reg = <0x01c20d00 0x20>;
899 interrupts = <0 24 4>;
903 compatible = "allwinner,sun7i-a20-pwm";
904 reg = <0x01c20e00 0xc>;
911 compatible = "allwinner,sun4i-a10-ir";
912 clocks = <&apb0_gates 6>, <&ir0_clk>;
913 clock-names = "apb", "ir";
914 interrupts = <0 5 4>;
915 reg = <0x01c21800 0x40>;
920 compatible = "allwinner,sun4i-a10-ir";
921 clocks = <&apb0_gates 7>, <&ir1_clk>;
922 clock-names = "apb", "ir";
923 interrupts = <0 6 4>;
924 reg = <0x01c21c00 0x40>;
928 sid: eeprom@01c23800 {
929 compatible = "allwinner,sun7i-a20-sid";
930 reg = <0x01c23800 0x200>;
934 compatible = "allwinner,sun4i-a10-ts";
935 reg = <0x01c25000 0x100>;
936 interrupts = <0 29 4>;
939 uart0: serial@01c28000 {
940 compatible = "snps,dw-apb-uart";
941 reg = <0x01c28000 0x400>;
942 interrupts = <0 1 4>;
945 clocks = <&apb1_gates 16>;
949 uart1: serial@01c28400 {
950 compatible = "snps,dw-apb-uart";
951 reg = <0x01c28400 0x400>;
952 interrupts = <0 2 4>;
955 clocks = <&apb1_gates 17>;
959 uart2: serial@01c28800 {
960 compatible = "snps,dw-apb-uart";
961 reg = <0x01c28800 0x400>;
962 interrupts = <0 3 4>;
965 clocks = <&apb1_gates 18>;
969 uart3: serial@01c28c00 {
970 compatible = "snps,dw-apb-uart";
971 reg = <0x01c28c00 0x400>;
972 interrupts = <0 4 4>;
975 clocks = <&apb1_gates 19>;
979 uart4: serial@01c29000 {
980 compatible = "snps,dw-apb-uart";
981 reg = <0x01c29000 0x400>;
982 interrupts = <0 17 4>;
985 clocks = <&apb1_gates 20>;
989 uart5: serial@01c29400 {
990 compatible = "snps,dw-apb-uart";
991 reg = <0x01c29400 0x400>;
992 interrupts = <0 18 4>;
995 clocks = <&apb1_gates 21>;
999 uart6: serial@01c29800 {
1000 compatible = "snps,dw-apb-uart";
1001 reg = <0x01c29800 0x400>;
1002 interrupts = <0 19 4>;
1005 clocks = <&apb1_gates 22>;
1006 status = "disabled";
1009 uart7: serial@01c29c00 {
1010 compatible = "snps,dw-apb-uart";
1011 reg = <0x01c29c00 0x400>;
1012 interrupts = <0 20 4>;
1015 clocks = <&apb1_gates 23>;
1016 status = "disabled";
1019 i2c0: i2c@01c2ac00 {
1020 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
1021 reg = <0x01c2ac00 0x400>;
1022 interrupts = <0 7 4>;
1023 clocks = <&apb1_gates 0>;
1024 status = "disabled";
1025 #address-cells = <1>;
1029 i2c1: i2c@01c2b000 {
1030 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
1031 reg = <0x01c2b000 0x400>;
1032 interrupts = <0 8 4>;
1033 clocks = <&apb1_gates 1>;
1034 status = "disabled";
1035 #address-cells = <1>;
1039 i2c2: i2c@01c2b400 {
1040 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
1041 reg = <0x01c2b400 0x400>;
1042 interrupts = <0 9 4>;
1043 clocks = <&apb1_gates 2>;
1044 status = "disabled";
1045 #address-cells = <1>;
1049 i2c3: i2c@01c2b800 {
1050 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
1051 reg = <0x01c2b800 0x400>;
1052 interrupts = <0 88 4>;
1053 clocks = <&apb1_gates 3>;
1054 status = "disabled";
1055 #address-cells = <1>;
1059 i2c4: i2c@01c2c000 {
1060 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
1061 reg = <0x01c2c000 0x400>;
1062 interrupts = <0 89 4>;
1063 clocks = <&apb1_gates 15>;
1064 status = "disabled";
1065 #address-cells = <1>;
1069 gmac: ethernet@01c50000 {
1070 compatible = "allwinner,sun7i-a20-gmac";
1071 reg = <0x01c50000 0x10000>;
1072 interrupts = <0 85 4>;
1073 interrupt-names = "macirq";
1074 clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
1075 clock-names = "stmmaceth", "allwinner_gmac_tx";
1078 snps,force_sf_dma_mode;
1079 status = "disabled";
1080 #address-cells = <1>;
1085 compatible = "allwinner,sun7i-a20-hstimer";
1086 reg = <0x01c60000 0x1000>;
1087 interrupts = <0 81 4>,
1091 clocks = <&ahb_gates 28>;
1094 gic: interrupt-controller@01c81000 {
1095 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
1096 reg = <0x01c81000 0x1000>,
1097 <0x01c82000 0x1000>,
1098 <0x01c84000 0x2000>,
1099 <0x01c86000 0x2000>;
1100 interrupt-controller;
1101 #interrupt-cells = <3>;
1102 interrupts = <1 9 0xf04>;