2 * Copyright 2013 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include "skeleton.dtsi"
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include <dt-bindings/thermal/thermal.h>
50 #include <dt-bindings/dma/sun4i-a10.h>
51 #include <dt-bindings/pinctrl/sun4i-a10.h>
54 interrupt-parent = <&gic>;
66 compatible = "allwinner,simple-framebuffer",
68 allwinner,pipeline = "de_be0-lcd0-hdmi";
69 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
75 compatible = "allwinner,simple-framebuffer",
77 allwinner,pipeline = "de_be0-lcd0";
78 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
83 compatible = "allwinner,simple-framebuffer",
85 allwinner,pipeline = "de_be0-lcd0-tve0";
86 clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
97 compatible = "arm,cortex-a7";
101 clock-latency = <244144>; /* 8 32k periods */
112 #cooling-cells = <2>;
113 cooling-min-level = <0>;
114 cooling-max-level = <6>;
118 compatible = "arm,cortex-a7";
127 polling-delay-passive = <250>;
128 polling-delay = <1000>;
129 thermal-sensors = <&rtp>;
133 trip = <&cpu_alert0>;
134 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
139 cpu_alert0: cpu_alert0 {
141 temperature = <75000>;
148 temperature = <100000>;
157 reg = <0x40000000 0x80000000>;
161 compatible = "arm,armv7-timer";
162 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
163 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
164 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
165 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
169 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
170 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
171 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
175 #address-cells = <1>;
179 osc24M: clk@01c20050 {
181 compatible = "allwinner,sun4i-a10-osc-clk";
182 reg = <0x01c20050 0x4>;
183 clock-frequency = <24000000>;
184 clock-output-names = "osc24M";
189 compatible = "fixed-clock";
190 clock-frequency = <32768>;
191 clock-output-names = "osc32k";
196 compatible = "allwinner,sun4i-a10-pll1-clk";
197 reg = <0x01c20000 0x4>;
199 clock-output-names = "pll1";
204 compatible = "allwinner,sun7i-a20-pll4-clk";
205 reg = <0x01c20018 0x4>;
207 clock-output-names = "pll4";
212 compatible = "allwinner,sun4i-a10-pll5-clk";
213 reg = <0x01c20020 0x4>;
215 clock-output-names = "pll5_ddr", "pll5_other";
220 compatible = "allwinner,sun4i-a10-pll6-clk";
221 reg = <0x01c20028 0x4>;
223 clock-output-names = "pll6_sata", "pll6_other", "pll6",
229 compatible = "allwinner,sun7i-a20-pll4-clk";
230 reg = <0x01c20040 0x4>;
232 clock-output-names = "pll8";
237 compatible = "allwinner,sun4i-a10-cpu-clk";
238 reg = <0x01c20054 0x4>;
239 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
240 clock-output-names = "cpu";
245 compatible = "allwinner,sun4i-a10-axi-clk";
246 reg = <0x01c20054 0x4>;
248 clock-output-names = "axi";
253 compatible = "allwinner,sun5i-a13-ahb-clk";
254 reg = <0x01c20054 0x4>;
255 clocks = <&axi>, <&pll6 3>, <&pll6 1>;
256 clock-output-names = "ahb";
258 * Use PLL6 as parent, instead of CPU/AXI
259 * which has rate changes due to cpufreq
261 assigned-clocks = <&ahb>;
262 assigned-clock-parents = <&pll6 3>;
265 ahb_gates: clk@01c20060 {
267 compatible = "allwinner,sun7i-a20-ahb-gates-clk";
268 reg = <0x01c20060 0x8>;
270 clock-indices = <0>, <1>,
273 <9>, <10>, <11>, <12>,
275 <17>, <18>, <20>, <21>,
277 <28>, <32>, <33>, <34>,
278 <35>, <36>, <37>, <40>,
283 clock-output-names = "ahb_usb0", "ahb_ehci0",
284 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
285 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
286 "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
287 "ahb_nand", "ahb_sdram", "ahb_ace",
288 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
289 "ahb_spi2", "ahb_spi3", "ahb_sata",
290 "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
291 "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
292 "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
293 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
294 "ahb_de_fe1", "ahb_gmac", "ahb_mp",
298 apb0: apb0@01c20054 {
300 compatible = "allwinner,sun4i-a10-apb0-clk";
301 reg = <0x01c20054 0x4>;
303 clock-output-names = "apb0";
306 apb0_gates: clk@01c20068 {
308 compatible = "allwinner,sun7i-a20-apb0-gates-clk";
309 reg = <0x01c20068 0x4>;
311 clock-indices = <0>, <1>,
315 clock-output-names = "apb0_codec", "apb0_spdif",
316 "apb0_ac97", "apb0_iis0", "apb0_iis1",
317 "apb0_pio", "apb0_ir0", "apb0_ir1",
318 "apb0_iis2", "apb0_keypad";
323 compatible = "allwinner,sun4i-a10-apb1-clk";
324 reg = <0x01c20058 0x4>;
325 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
326 clock-output-names = "apb1";
329 apb1_gates: clk@01c2006c {
331 compatible = "allwinner,sun7i-a20-apb1-gates-clk";
332 reg = <0x01c2006c 0x4>;
334 clock-indices = <0>, <1>,
340 clock-output-names = "apb1_i2c0", "apb1_i2c1",
341 "apb1_i2c2", "apb1_i2c3", "apb1_can",
342 "apb1_scr", "apb1_ps20", "apb1_ps21",
343 "apb1_i2c4", "apb1_uart0", "apb1_uart1",
344 "apb1_uart2", "apb1_uart3", "apb1_uart4",
345 "apb1_uart5", "apb1_uart6", "apb1_uart7";
348 nand_clk: clk@01c20080 {
350 compatible = "allwinner,sun4i-a10-mod0-clk";
351 reg = <0x01c20080 0x4>;
352 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
353 clock-output-names = "nand";
356 ms_clk: clk@01c20084 {
358 compatible = "allwinner,sun4i-a10-mod0-clk";
359 reg = <0x01c20084 0x4>;
360 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
361 clock-output-names = "ms";
364 mmc0_clk: clk@01c20088 {
366 compatible = "allwinner,sun4i-a10-mmc-clk";
367 reg = <0x01c20088 0x4>;
368 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
369 clock-output-names = "mmc0",
374 mmc1_clk: clk@01c2008c {
376 compatible = "allwinner,sun4i-a10-mmc-clk";
377 reg = <0x01c2008c 0x4>;
378 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
379 clock-output-names = "mmc1",
384 mmc2_clk: clk@01c20090 {
386 compatible = "allwinner,sun4i-a10-mmc-clk";
387 reg = <0x01c20090 0x4>;
388 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
389 clock-output-names = "mmc2",
394 mmc3_clk: clk@01c20094 {
396 compatible = "allwinner,sun4i-a10-mmc-clk";
397 reg = <0x01c20094 0x4>;
398 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
399 clock-output-names = "mmc3",
404 ts_clk: clk@01c20098 {
406 compatible = "allwinner,sun4i-a10-mod0-clk";
407 reg = <0x01c20098 0x4>;
408 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
409 clock-output-names = "ts";
412 ss_clk: clk@01c2009c {
414 compatible = "allwinner,sun4i-a10-mod0-clk";
415 reg = <0x01c2009c 0x4>;
416 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
417 clock-output-names = "ss";
420 spi0_clk: clk@01c200a0 {
422 compatible = "allwinner,sun4i-a10-mod0-clk";
423 reg = <0x01c200a0 0x4>;
424 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
425 clock-output-names = "spi0";
428 spi1_clk: clk@01c200a4 {
430 compatible = "allwinner,sun4i-a10-mod0-clk";
431 reg = <0x01c200a4 0x4>;
432 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
433 clock-output-names = "spi1";
436 spi2_clk: clk@01c200a8 {
438 compatible = "allwinner,sun4i-a10-mod0-clk";
439 reg = <0x01c200a8 0x4>;
440 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
441 clock-output-names = "spi2";
444 pata_clk: clk@01c200ac {
446 compatible = "allwinner,sun4i-a10-mod0-clk";
447 reg = <0x01c200ac 0x4>;
448 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
449 clock-output-names = "pata";
452 ir0_clk: clk@01c200b0 {
454 compatible = "allwinner,sun4i-a10-mod0-clk";
455 reg = <0x01c200b0 0x4>;
456 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
457 clock-output-names = "ir0";
460 ir1_clk: clk@01c200b4 {
462 compatible = "allwinner,sun4i-a10-mod0-clk";
463 reg = <0x01c200b4 0x4>;
464 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
465 clock-output-names = "ir1";
468 keypad_clk: clk@01c200c4 {
470 compatible = "allwinner,sun4i-a10-mod0-clk";
471 reg = <0x01c200c4 0x4>;
473 clock-output-names = "keypad";
476 usb_clk: clk@01c200cc {
479 compatible = "allwinner,sun4i-a10-usb-clk";
480 reg = <0x01c200cc 0x4>;
482 clock-output-names = "usb_ohci0", "usb_ohci1",
486 spi3_clk: clk@01c200d4 {
488 compatible = "allwinner,sun4i-a10-mod0-clk";
489 reg = <0x01c200d4 0x4>;
490 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
491 clock-output-names = "spi3";
494 mbus_clk: clk@01c2015c {
496 compatible = "allwinner,sun5i-a13-mbus-clk";
497 reg = <0x01c2015c 0x4>;
498 clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
499 clock-output-names = "mbus";
503 * The following two are dummy clocks, placeholders
504 * used in the gmac_tx clock. The gmac driver will
505 * choose one parent depending on the PHY interface
506 * mode, using clk_set_rate auto-reparenting.
508 * The actual TX clock rate is not controlled by the
511 mii_phy_tx_clk: clk@2 {
513 compatible = "fixed-clock";
514 clock-frequency = <25000000>;
515 clock-output-names = "mii_phy_tx";
518 gmac_int_tx_clk: clk@3 {
520 compatible = "fixed-clock";
521 clock-frequency = <125000000>;
522 clock-output-names = "gmac_int_tx";
525 gmac_tx_clk: clk@01c20164 {
527 compatible = "allwinner,sun7i-a20-gmac-clk";
528 reg = <0x01c20164 0x4>;
529 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
530 clock-output-names = "gmac_tx";
534 * Dummy clock used by output clocks
538 compatible = "fixed-factor-clock";
542 clock-output-names = "osc24M_32k";
545 clk_out_a: clk@01c201f0 {
547 compatible = "allwinner,sun7i-a20-out-clk";
548 reg = <0x01c201f0 0x4>;
549 clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
550 clock-output-names = "clk_out_a";
553 clk_out_b: clk@01c201f4 {
555 compatible = "allwinner,sun7i-a20-out-clk";
556 reg = <0x01c201f4 0x4>;
557 clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
558 clock-output-names = "clk_out_b";
563 compatible = "simple-bus";
564 #address-cells = <1>;
568 sram-controller@01c00000 {
569 compatible = "allwinner,sun4i-a10-sram-controller";
570 reg = <0x01c00000 0x30>;
571 #address-cells = <1>;
575 sram_a: sram@00000000 {
576 compatible = "mmio-sram";
577 reg = <0x00000000 0xc000>;
578 #address-cells = <1>;
580 ranges = <0 0x00000000 0xc000>;
582 emac_sram: sram-section@8000 {
583 compatible = "allwinner,sun4i-a10-sram-a3-a4";
584 reg = <0x8000 0x4000>;
589 sram_d: sram@00010000 {
590 compatible = "mmio-sram";
591 reg = <0x00010000 0x1000>;
592 #address-cells = <1>;
594 ranges = <0 0x00010000 0x1000>;
596 otg_sram: sram-section@0000 {
597 compatible = "allwinner,sun4i-a10-sram-d";
598 reg = <0x0000 0x1000>;
604 nmi_intc: interrupt-controller@01c00030 {
605 compatible = "allwinner,sun7i-a20-sc-nmi";
606 interrupt-controller;
607 #interrupt-cells = <2>;
608 reg = <0x01c00030 0x0c>;
609 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
612 dma: dma-controller@01c02000 {
613 compatible = "allwinner,sun4i-a10-dma";
614 reg = <0x01c02000 0x1000>;
615 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
616 clocks = <&ahb_gates 6>;
621 compatible = "allwinner,sun4i-a10-spi";
622 reg = <0x01c05000 0x1000>;
623 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
624 clocks = <&ahb_gates 20>, <&spi0_clk>;
625 clock-names = "ahb", "mod";
626 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
627 <&dma SUN4I_DMA_DEDICATED 26>;
628 dma-names = "rx", "tx";
630 #address-cells = <1>;
635 compatible = "allwinner,sun4i-a10-spi";
636 reg = <0x01c06000 0x1000>;
637 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
638 clocks = <&ahb_gates 21>, <&spi1_clk>;
639 clock-names = "ahb", "mod";
640 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
641 <&dma SUN4I_DMA_DEDICATED 8>;
642 dma-names = "rx", "tx";
644 #address-cells = <1>;
648 emac: ethernet@01c0b000 {
649 compatible = "allwinner,sun4i-a10-emac";
650 reg = <0x01c0b000 0x1000>;
651 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
652 clocks = <&ahb_gates 17>;
653 allwinner,sram = <&emac_sram 1>;
657 mdio: mdio@01c0b080 {
658 compatible = "allwinner,sun4i-a10-mdio";
659 reg = <0x01c0b080 0x14>;
661 #address-cells = <1>;
666 compatible = "allwinner,sun5i-a13-mmc";
667 reg = <0x01c0f000 0x1000>;
668 clocks = <&ahb_gates 8>,
676 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
678 #address-cells = <1>;
683 compatible = "allwinner,sun5i-a13-mmc";
684 reg = <0x01c10000 0x1000>;
685 clocks = <&ahb_gates 9>,
693 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
695 #address-cells = <1>;
700 compatible = "allwinner,sun5i-a13-mmc";
701 reg = <0x01c11000 0x1000>;
702 clocks = <&ahb_gates 10>,
710 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
712 #address-cells = <1>;
717 compatible = "allwinner,sun5i-a13-mmc";
718 reg = <0x01c12000 0x1000>;
719 clocks = <&ahb_gates 11>,
727 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
729 #address-cells = <1>;
733 usb_otg: usb@01c13000 {
734 compatible = "allwinner,sun4i-a10-musb";
735 reg = <0x01c13000 0x0400>;
736 clocks = <&ahb_gates 0>;
737 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
738 interrupt-names = "mc";
741 extcon = <&usbphy 0>;
742 allwinner,sram = <&otg_sram 1>;
746 usbphy: phy@01c13400 {
748 compatible = "allwinner,sun7i-a20-usb-phy";
749 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
750 reg-names = "phy_ctrl", "pmu1", "pmu2";
751 clocks = <&usb_clk 8>;
752 clock-names = "usb_phy";
753 resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
754 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
758 ehci0: usb@01c14000 {
759 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
760 reg = <0x01c14000 0x100>;
761 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
762 clocks = <&ahb_gates 1>;
768 ohci0: usb@01c14400 {
769 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
770 reg = <0x01c14400 0x100>;
771 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
772 clocks = <&usb_clk 6>, <&ahb_gates 2>;
778 crypto: crypto-engine@01c15000 {
779 compatible = "allwinner,sun4i-a10-crypto";
780 reg = <0x01c15000 0x1000>;
781 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
782 clocks = <&ahb_gates 5>, <&ss_clk>;
783 clock-names = "ahb", "mod";
787 compatible = "allwinner,sun4i-a10-spi";
788 reg = <0x01c17000 0x1000>;
789 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
790 clocks = <&ahb_gates 22>, <&spi2_clk>;
791 clock-names = "ahb", "mod";
792 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
793 <&dma SUN4I_DMA_DEDICATED 28>;
794 dma-names = "rx", "tx";
796 #address-cells = <1>;
800 ahci: sata@01c18000 {
801 compatible = "allwinner,sun4i-a10-ahci";
802 reg = <0x01c18000 0x1000>;
803 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
804 clocks = <&pll6 0>, <&ahb_gates 25>;
808 ehci1: usb@01c1c000 {
809 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
810 reg = <0x01c1c000 0x100>;
811 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
812 clocks = <&ahb_gates 3>;
818 ohci1: usb@01c1c400 {
819 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
820 reg = <0x01c1c400 0x100>;
821 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
822 clocks = <&usb_clk 7>, <&ahb_gates 4>;
829 compatible = "allwinner,sun4i-a10-spi";
830 reg = <0x01c1f000 0x1000>;
831 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
832 clocks = <&ahb_gates 23>, <&spi3_clk>;
833 clock-names = "ahb", "mod";
834 dmas = <&dma SUN4I_DMA_DEDICATED 31>,
835 <&dma SUN4I_DMA_DEDICATED 30>;
836 dma-names = "rx", "tx";
838 #address-cells = <1>;
842 pio: pinctrl@01c20800 {
843 compatible = "allwinner,sun7i-a20-pinctrl";
844 reg = <0x01c20800 0x400>;
845 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
846 clocks = <&apb0_gates 5>;
848 interrupt-controller;
849 #interrupt-cells = <3>;
852 pwm0_pins_a: pwm0@0 {
853 allwinner,pins = "PB2";
854 allwinner,function = "pwm";
855 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
856 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
859 pwm1_pins_a: pwm1@0 {
860 allwinner,pins = "PI3";
861 allwinner,function = "pwm";
862 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
863 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
866 uart0_pins_a: uart0@0 {
867 allwinner,pins = "PB22", "PB23";
868 allwinner,function = "uart0";
869 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
870 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
873 uart2_pins_a: uart2@0 {
874 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
875 allwinner,function = "uart2";
876 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
877 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
880 uart3_pins_a: uart3@0 {
881 allwinner,pins = "PG6", "PG7", "PG8", "PG9";
882 allwinner,function = "uart3";
883 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
884 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
887 uart3_pins_b: uart3@1 {
888 allwinner,pins = "PH0", "PH1";
889 allwinner,function = "uart3";
890 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
891 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
894 uart4_pins_a: uart4@0 {
895 allwinner,pins = "PG10", "PG11";
896 allwinner,function = "uart4";
897 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
898 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
901 uart4_pins_b: uart4@1 {
902 allwinner,pins = "PH4", "PH5";
903 allwinner,function = "uart4";
904 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
905 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
908 uart5_pins_a: uart5@0 {
909 allwinner,pins = "PI10", "PI11";
910 allwinner,function = "uart5";
911 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
912 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
915 uart6_pins_a: uart6@0 {
916 allwinner,pins = "PI12", "PI13";
917 allwinner,function = "uart6";
918 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
919 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
922 uart7_pins_a: uart7@0 {
923 allwinner,pins = "PI20", "PI21";
924 allwinner,function = "uart7";
925 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
926 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
929 i2c0_pins_a: i2c0@0 {
930 allwinner,pins = "PB0", "PB1";
931 allwinner,function = "i2c0";
932 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
933 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
936 i2c1_pins_a: i2c1@0 {
937 allwinner,pins = "PB18", "PB19";
938 allwinner,function = "i2c1";
939 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
940 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
943 i2c2_pins_a: i2c2@0 {
944 allwinner,pins = "PB20", "PB21";
945 allwinner,function = "i2c2";
946 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
947 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
950 i2c3_pins_a: i2c3@0 {
951 allwinner,pins = "PI0", "PI1";
952 allwinner,function = "i2c3";
953 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
954 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
957 emac_pins_a: emac0@0 {
958 allwinner,pins = "PA0", "PA1", "PA2",
959 "PA3", "PA4", "PA5", "PA6",
960 "PA7", "PA8", "PA9", "PA10",
961 "PA11", "PA12", "PA13", "PA14",
963 allwinner,function = "emac";
964 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
965 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
968 clk_out_a_pins_a: clk_out_a@0 {
969 allwinner,pins = "PI12";
970 allwinner,function = "clk_out_a";
971 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
972 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
975 clk_out_b_pins_a: clk_out_b@0 {
976 allwinner,pins = "PI13";
977 allwinner,function = "clk_out_b";
978 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
979 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
982 gmac_pins_mii_a: gmac_mii@0 {
983 allwinner,pins = "PA0", "PA1", "PA2",
984 "PA3", "PA4", "PA5", "PA6",
985 "PA7", "PA8", "PA9", "PA10",
986 "PA11", "PA12", "PA13", "PA14",
988 allwinner,function = "gmac";
989 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
990 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
993 gmac_pins_rgmii_a: gmac_rgmii@0 {
994 allwinner,pins = "PA0", "PA1", "PA2",
995 "PA3", "PA4", "PA5", "PA6",
996 "PA7", "PA8", "PA10",
997 "PA11", "PA12", "PA13",
999 allwinner,function = "gmac";
1001 * data lines in RGMII mode use DDR mode
1002 * and need a higher signal drive strength
1004 allwinner,drive = <SUN4I_PINCTRL_40_MA>;
1005 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1008 spi0_pins_a: spi0@0 {
1009 allwinner,pins = "PI11", "PI12", "PI13";
1010 allwinner,function = "spi0";
1011 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1012 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1015 spi0_cs0_pins_a: spi0_cs0@0 {
1016 allwinner,pins = "PI10";
1017 allwinner,function = "spi0";
1018 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1019 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1022 spi0_cs1_pins_a: spi0_cs1@0 {
1023 allwinner,pins = "PI14";
1024 allwinner,function = "spi0";
1025 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1026 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1029 spi1_pins_a: spi1@0 {
1030 allwinner,pins = "PI17", "PI18", "PI19";
1031 allwinner,function = "spi1";
1032 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1033 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1036 spi1_cs0_pins_a: spi1_cs0@0 {
1037 allwinner,pins = "PI16";
1038 allwinner,function = "spi1";
1039 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1040 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1043 spi2_pins_a: spi2@0 {
1044 allwinner,pins = "PC20", "PC21", "PC22";
1045 allwinner,function = "spi2";
1046 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1047 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1050 spi2_pins_b: spi2@1 {
1051 allwinner,pins = "PB15", "PB16", "PB17";
1052 allwinner,function = "spi2";
1053 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1054 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1057 spi2_cs0_pins_a: spi2_cs0@0 {
1058 allwinner,pins = "PC19";
1059 allwinner,function = "spi2";
1060 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1061 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1064 spi2_cs0_pins_b: spi2_cs0@1 {
1065 allwinner,pins = "PB14";
1066 allwinner,function = "spi2";
1067 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1068 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1071 mmc0_pins_a: mmc0@0 {
1072 allwinner,pins = "PF0", "PF1", "PF2",
1073 "PF3", "PF4", "PF5";
1074 allwinner,function = "mmc0";
1075 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
1076 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1079 mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
1080 allwinner,pins = "PH1";
1081 allwinner,function = "gpio_in";
1082 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1083 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
1086 mmc2_pins_a: mmc2@0 {
1087 allwinner,pins = "PC6", "PC7", "PC8",
1088 "PC9", "PC10", "PC11";
1089 allwinner,function = "mmc2";
1090 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
1091 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
1094 mmc3_pins_a: mmc3@0 {
1095 allwinner,pins = "PI4", "PI5", "PI6",
1096 "PI7", "PI8", "PI9";
1097 allwinner,function = "mmc3";
1098 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
1099 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1102 ir0_rx_pins_a: ir0@0 {
1103 allwinner,pins = "PB4";
1104 allwinner,function = "ir0";
1105 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1106 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1109 ir0_tx_pins_a: ir0@1 {
1110 allwinner,pins = "PB3";
1111 allwinner,function = "ir0";
1112 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1113 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1116 ir1_rx_pins_a: ir1@0 {
1117 allwinner,pins = "PB23";
1118 allwinner,function = "ir1";
1119 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1120 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1123 ir1_tx_pins_a: ir1@1 {
1124 allwinner,pins = "PB22";
1125 allwinner,function = "ir1";
1126 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1127 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1130 ps20_pins_a: ps20@0 {
1131 allwinner,pins = "PI20", "PI21";
1132 allwinner,function = "ps2";
1133 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1134 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1137 ps21_pins_a: ps21@0 {
1138 allwinner,pins = "PH12", "PH13";
1139 allwinner,function = "ps2";
1140 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1141 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1146 compatible = "allwinner,sun4i-a10-timer";
1147 reg = <0x01c20c00 0x90>;
1148 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
1149 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
1150 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
1151 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
1152 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
1153 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1157 wdt: watchdog@01c20c90 {
1158 compatible = "allwinner,sun4i-a10-wdt";
1159 reg = <0x01c20c90 0x10>;
1163 compatible = "allwinner,sun7i-a20-rtc";
1164 reg = <0x01c20d00 0x20>;
1165 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1169 compatible = "allwinner,sun7i-a20-pwm";
1170 reg = <0x01c20e00 0xc>;
1173 status = "disabled";
1177 compatible = "allwinner,sun4i-a10-ir";
1178 clocks = <&apb0_gates 6>, <&ir0_clk>;
1179 clock-names = "apb", "ir";
1180 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1181 reg = <0x01c21800 0x40>;
1182 status = "disabled";
1186 compatible = "allwinner,sun4i-a10-ir";
1187 clocks = <&apb0_gates 7>, <&ir1_clk>;
1188 clock-names = "apb", "ir";
1189 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1190 reg = <0x01c21c00 0x40>;
1191 status = "disabled";
1194 lradc: lradc@01c22800 {
1195 compatible = "allwinner,sun4i-a10-lradc-keys";
1196 reg = <0x01c22800 0x100>;
1197 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1198 status = "disabled";
1201 sid: eeprom@01c23800 {
1202 compatible = "allwinner,sun7i-a20-sid";
1203 reg = <0x01c23800 0x200>;
1207 compatible = "allwinner,sun5i-a13-ts";
1208 reg = <0x01c25000 0x100>;
1209 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1210 #thermal-sensor-cells = <0>;
1213 uart0: serial@01c28000 {
1214 compatible = "snps,dw-apb-uart";
1215 reg = <0x01c28000 0x400>;
1216 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1219 clocks = <&apb1_gates 16>;
1220 status = "disabled";
1223 uart1: serial@01c28400 {
1224 compatible = "snps,dw-apb-uart";
1225 reg = <0x01c28400 0x400>;
1226 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1229 clocks = <&apb1_gates 17>;
1230 status = "disabled";
1233 uart2: serial@01c28800 {
1234 compatible = "snps,dw-apb-uart";
1235 reg = <0x01c28800 0x400>;
1236 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1239 clocks = <&apb1_gates 18>;
1240 status = "disabled";
1243 uart3: serial@01c28c00 {
1244 compatible = "snps,dw-apb-uart";
1245 reg = <0x01c28c00 0x400>;
1246 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1249 clocks = <&apb1_gates 19>;
1250 status = "disabled";
1253 uart4: serial@01c29000 {
1254 compatible = "snps,dw-apb-uart";
1255 reg = <0x01c29000 0x400>;
1256 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1259 clocks = <&apb1_gates 20>;
1260 status = "disabled";
1263 uart5: serial@01c29400 {
1264 compatible = "snps,dw-apb-uart";
1265 reg = <0x01c29400 0x400>;
1266 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1269 clocks = <&apb1_gates 21>;
1270 status = "disabled";
1273 uart6: serial@01c29800 {
1274 compatible = "snps,dw-apb-uart";
1275 reg = <0x01c29800 0x400>;
1276 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1279 clocks = <&apb1_gates 22>;
1280 status = "disabled";
1283 uart7: serial@01c29c00 {
1284 compatible = "snps,dw-apb-uart";
1285 reg = <0x01c29c00 0x400>;
1286 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1289 clocks = <&apb1_gates 23>;
1290 status = "disabled";
1293 i2c0: i2c@01c2ac00 {
1294 compatible = "allwinner,sun7i-a20-i2c",
1295 "allwinner,sun4i-a10-i2c";
1296 reg = <0x01c2ac00 0x400>;
1297 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1298 clocks = <&apb1_gates 0>;
1299 status = "disabled";
1300 #address-cells = <1>;
1304 i2c1: i2c@01c2b000 {
1305 compatible = "allwinner,sun7i-a20-i2c",
1306 "allwinner,sun4i-a10-i2c";
1307 reg = <0x01c2b000 0x400>;
1308 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1309 clocks = <&apb1_gates 1>;
1310 status = "disabled";
1311 #address-cells = <1>;
1315 i2c2: i2c@01c2b400 {
1316 compatible = "allwinner,sun7i-a20-i2c",
1317 "allwinner,sun4i-a10-i2c";
1318 reg = <0x01c2b400 0x400>;
1319 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1320 clocks = <&apb1_gates 2>;
1321 status = "disabled";
1322 #address-cells = <1>;
1326 i2c3: i2c@01c2b800 {
1327 compatible = "allwinner,sun7i-a20-i2c",
1328 "allwinner,sun4i-a10-i2c";
1329 reg = <0x01c2b800 0x400>;
1330 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1331 clocks = <&apb1_gates 3>;
1332 status = "disabled";
1333 #address-cells = <1>;
1337 i2c4: i2c@01c2c000 {
1338 compatible = "allwinner,sun7i-a20-i2c",
1339 "allwinner,sun4i-a10-i2c";
1340 reg = <0x01c2c000 0x400>;
1341 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1342 clocks = <&apb1_gates 15>;
1343 status = "disabled";
1344 #address-cells = <1>;
1348 gmac: ethernet@01c50000 {
1349 compatible = "allwinner,sun7i-a20-gmac";
1350 reg = <0x01c50000 0x10000>;
1351 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1352 interrupt-names = "macirq";
1353 clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
1354 clock-names = "stmmaceth", "allwinner_gmac_tx";
1357 snps,force_sf_dma_mode;
1358 status = "disabled";
1359 #address-cells = <1>;
1364 compatible = "allwinner,sun7i-a20-hstimer";
1365 reg = <0x01c60000 0x1000>;
1366 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
1367 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
1368 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
1369 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1370 clocks = <&ahb_gates 28>;
1373 gic: interrupt-controller@01c81000 {
1374 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
1375 reg = <0x01c81000 0x1000>,
1376 <0x01c82000 0x1000>,
1377 <0x01c84000 0x2000>,
1378 <0x01c86000 0x2000>;
1379 interrupt-controller;
1380 #interrupt-cells = <3>;
1381 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1384 ps20: ps2@01c2a000 {
1385 compatible = "allwinner,sun4i-a10-ps2";
1386 reg = <0x01c2a000 0x400>;
1387 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1388 clocks = <&apb1_gates 6>;
1389 status = "disabled";
1392 ps21: ps2@01c2a400 {
1393 compatible = "allwinner,sun4i-a10-ps2";
1394 reg = <0x01c2a400 0x400>;
1395 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1396 clocks = <&apb1_gates 7>;
1397 status = "disabled";