2 * Copyright 2013 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
14 /include/ "skeleton.dtsi"
17 interrupt-parent = <&gic>;
24 compatible = "arm,cortex-a7";
30 compatible = "arm,cortex-a7";
37 reg = <0x40000000 0x80000000>;
45 osc24M: osc24M@01c20050 {
47 compatible = "allwinner,sun4i-osc-clk";
48 reg = <0x01c20050 0x4>;
49 clock-frequency = <24000000>;
54 compatible = "fixed-clock";
55 clock-frequency = <32768>;
60 compatible = "allwinner,sun4i-pll1-clk";
61 reg = <0x01c20000 0x4>;
66 * This is a dummy clock, to be used as placeholder on
67 * other mux clocks when a specific parent clock is not
68 * yet implemented. It should be dropped when the driver
73 compatible = "fixed-clock";
74 clock-frequency = <0>;
79 compatible = "allwinner,sun4i-cpu-clk";
80 reg = <0x01c20054 0x4>;
81 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6>;
86 compatible = "allwinner,sun4i-axi-clk";
87 reg = <0x01c20054 0x4>;
93 compatible = "allwinner,sun4i-ahb-clk";
94 reg = <0x01c20054 0x4>;
98 ahb_gates: ahb_gates@01c20060 {
100 compatible = "allwinner,sun7i-a20-ahb-gates-clk";
101 reg = <0x01c20060 0x8>;
103 clock-output-names = "ahb_usb0", "ahb_ehci0",
104 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
105 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
106 "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
107 "ahb_nand", "ahb_sdram", "ahb_ace",
108 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
109 "ahb_spi2", "ahb_spi3", "ahb_sata",
110 "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
111 "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
112 "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
113 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
114 "ahb_de_fe1", "ahb_gmac", "ahb_mp",
118 apb0: apb0@01c20054 {
120 compatible = "allwinner,sun4i-apb0-clk";
121 reg = <0x01c20054 0x4>;
125 apb0_gates: apb0_gates@01c20068 {
127 compatible = "allwinner,sun7i-a20-apb0-gates-clk";
128 reg = <0x01c20068 0x4>;
130 clock-output-names = "apb0_codec", "apb0_spdif",
131 "apb0_ac97", "apb0_iis0", "apb0_iis1",
132 "apb0_pio", "apb0_ir0", "apb0_ir1",
133 "apb0_iis2", "apb0_keypad";
136 apb1_mux: apb1_mux@01c20058 {
138 compatible = "allwinner,sun4i-apb1-mux-clk";
139 reg = <0x01c20058 0x4>;
140 clocks = <&osc24M>, <&pll6>, <&osc32k>;
143 apb1: apb1@01c20058 {
145 compatible = "allwinner,sun4i-apb1-clk";
146 reg = <0x01c20058 0x4>;
147 clocks = <&apb1_mux>;
150 apb1_gates: apb1_gates@01c2006c {
152 compatible = "allwinner,sun7i-a20-apb1-gates-clk";
153 reg = <0x01c2006c 0x4>;
155 clock-output-names = "apb1_i2c0", "apb1_i2c1",
156 "apb1_i2c2", "apb1_i2c3", "apb1_can",
157 "apb1_scr", "apb1_ps20", "apb1_ps21",
158 "apb1_i2c4", "apb1_uart0", "apb1_uart1",
159 "apb1_uart2", "apb1_uart3", "apb1_uart4",
160 "apb1_uart5", "apb1_uart6", "apb1_uart7";
165 compatible = "simple-bus";
166 #address-cells = <1>;
170 pio: pinctrl@01c20800 {
171 compatible = "allwinner,sun7i-a20-pinctrl";
172 reg = <0x01c20800 0x400>;
173 interrupts = <0 28 1>;
174 clocks = <&apb0_gates 5>;
176 interrupt-controller;
177 #address-cells = <1>;
181 uart0_pins_a: uart0@0 {
182 allwinner,pins = "PB22", "PB23";
183 allwinner,function = "uart0";
184 allwinner,drive = <0>;
185 allwinner,pull = <0>;
188 uart6_pins_a: uart6@0 {
189 allwinner,pins = "PI12", "PI13";
190 allwinner,function = "uart6";
191 allwinner,drive = <0>;
192 allwinner,pull = <0>;
195 uart7_pins_a: uart7@0 {
196 allwinner,pins = "PI20", "PI21";
197 allwinner,function = "uart7";
198 allwinner,drive = <0>;
199 allwinner,pull = <0>;
204 compatible = "allwinner,sun4i-timer";
205 reg = <0x01c20c00 0x90>;
206 interrupts = <0 22 1>,
215 wdt: watchdog@01c20c90 {
216 compatible = "allwinner,sun4i-wdt";
217 reg = <0x01c20c90 0x10>;
220 uart0: serial@01c28000 {
221 compatible = "snps,dw-apb-uart";
222 reg = <0x01c28000 0x400>;
223 interrupts = <0 1 1>;
226 clocks = <&apb1_gates 16>;
230 uart1: serial@01c28400 {
231 compatible = "snps,dw-apb-uart";
232 reg = <0x01c28400 0x400>;
233 interrupts = <0 2 1>;
236 clocks = <&apb1_gates 17>;
240 uart2: serial@01c28800 {
241 compatible = "snps,dw-apb-uart";
242 reg = <0x01c28800 0x400>;
243 interrupts = <0 3 1>;
246 clocks = <&apb1_gates 18>;
250 uart3: serial@01c28c00 {
251 compatible = "snps,dw-apb-uart";
252 reg = <0x01c28c00 0x400>;
253 interrupts = <0 4 1>;
256 clocks = <&apb1_gates 19>;
260 uart4: serial@01c29000 {
261 compatible = "snps,dw-apb-uart";
262 reg = <0x01c29000 0x400>;
263 interrupts = <0 17 1>;
266 clocks = <&apb1_gates 20>;
270 uart5: serial@01c29400 {
271 compatible = "snps,dw-apb-uart";
272 reg = <0x01c29400 0x400>;
273 interrupts = <0 18 1>;
276 clocks = <&apb1_gates 21>;
280 uart6: serial@01c29800 {
281 compatible = "snps,dw-apb-uart";
282 reg = <0x01c29800 0x400>;
283 interrupts = <0 19 1>;
286 clocks = <&apb1_gates 22>;
290 uart7: serial@01c29c00 {
291 compatible = "snps,dw-apb-uart";
292 reg = <0x01c29c00 0x400>;
293 interrupts = <0 20 1>;
296 clocks = <&apb1_gates 23>;
300 gic: interrupt-controller@01c81000 {
301 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
302 reg = <0x01c81000 0x1000>,
306 interrupt-controller;
307 #interrupt-cells = <3>;
308 interrupts = <1 9 0xf04>;