2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
50 /include/ "skeleton.dtsi"
53 interrupt-parent = <&gic>;
69 compatible = "arm,cortex-a7";
75 compatible = "arm,cortex-a7";
82 reg = <0x40000000 0x40000000>;
92 compatible = "fixed-clock";
93 clock-frequency = <24000000>;
94 clock-output-names = "osc24M";
99 compatible = "fixed-clock";
100 clock-frequency = <32768>;
101 clock-output-names = "osc32k";
106 compatible = "allwinner,sun8i-a23-pll1-clk";
107 reg = <0x01c20000 0x4>;
109 clock-output-names = "pll1";
112 /* dummy clock until actually implemented */
115 compatible = "fixed-clock";
116 clock-frequency = <600000000>;
117 clock-output-names = "pll6";
120 cpu: cpu_clk@01c20050 {
122 compatible = "allwinner,sun4i-a10-cpu-clk";
123 reg = <0x01c20050 0x4>;
126 * PLL1 is listed twice here.
127 * While it looks suspicious, it's actually documented
128 * that way both in the datasheet and in the code from
131 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
132 clock-output-names = "cpu";
135 axi: axi_clk@01c20050 {
137 compatible = "allwinner,sun8i-a23-axi-clk";
138 reg = <0x01c20050 0x4>;
140 clock-output-names = "axi";
143 ahb1: ahb1_clk@01c20054 {
145 compatible = "allwinner,sun6i-a31-ahb1-clk";
146 reg = <0x01c20054 0x4>;
147 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
148 clock-output-names = "ahb1";
151 apb1: apb1_clk@01c20054 {
153 compatible = "allwinner,sun4i-a10-apb0-clk";
154 reg = <0x01c20054 0x4>;
156 clock-output-names = "apb1";
159 ahb1_gates: clk@01c20060 {
161 compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
162 reg = <0x01c20060 0x8>;
164 clock-output-names = "ahb1_mipidsi", "ahb1_dma",
165 "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
166 "ahb1_nand", "ahb1_sdram",
167 "ahb1_hstimer", "ahb1_spi0",
168 "ahb1_spi1", "ahb1_otg", "ahb1_ehci",
169 "ahb1_ohci", "ahb1_ve", "ahb1_lcd",
170 "ahb1_csi", "ahb1_be", "ahb1_fe",
171 "ahb1_gpu", "ahb1_spinlock",
175 apb1_gates: clk@01c20068 {
177 compatible = "allwinner,sun8i-a23-apb1-gates-clk";
178 reg = <0x01c20068 0x4>;
180 clock-output-names = "apb1_codec", "apb1_pio",
181 "apb1_daudio0", "apb1_daudio1";
186 compatible = "allwinner,sun4i-a10-apb1-clk";
187 reg = <0x01c20058 0x4>;
188 clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
189 clock-output-names = "apb2";
192 apb2_gates: clk@01c2006c {
194 compatible = "allwinner,sun8i-a23-apb2-gates-clk";
195 reg = <0x01c2006c 0x4>;
197 clock-output-names = "apb2_i2c0", "apb2_i2c1",
198 "apb2_i2c2", "apb2_uart0",
199 "apb2_uart1", "apb2_uart2",
200 "apb2_uart3", "apb2_uart4";
203 mmc0_clk: clk@01c20088 {
205 compatible = "allwinner,sun4i-a10-mod0-clk";
206 reg = <0x01c20088 0x4>;
207 clocks = <&osc24M>, <&pll6>;
208 clock-output-names = "mmc0";
211 mmc1_clk: clk@01c2008c {
213 compatible = "allwinner,sun4i-a10-mod0-clk";
214 reg = <0x01c2008c 0x4>;
215 clocks = <&osc24M>, <&pll6>;
216 clock-output-names = "mmc1";
219 mmc2_clk: clk@01c20090 {
221 compatible = "allwinner,sun4i-a10-mod0-clk";
222 reg = <0x01c20090 0x4>;
223 clocks = <&osc24M>, <&pll6>;
224 clock-output-names = "mmc2";
229 compatible = "simple-bus";
230 #address-cells = <1>;
234 dma: dma-controller@01c02000 {
235 compatible = "allwinner,sun8i-a23-dma";
236 reg = <0x01c02000 0x1000>;
237 interrupts = <0 50 4>;
238 clocks = <&ahb1_gates 6>;
239 resets = <&ahb1_rst 6>;
244 compatible = "allwinner,sun5i-a13-mmc";
245 reg = <0x01c0f000 0x1000>;
246 clocks = <&ahb1_gates 8>, <&mmc0_clk>;
247 clock-names = "ahb", "mmc";
248 resets = <&ahb1_rst 8>;
250 interrupts = <0 60 4>;
255 compatible = "allwinner,sun5i-a13-mmc";
256 reg = <0x01c10000 0x1000>;
257 clocks = <&ahb1_gates 9>, <&mmc1_clk>;
258 clock-names = "ahb", "mmc";
259 resets = <&ahb1_rst 9>;
261 interrupts = <0 61 4>;
266 compatible = "allwinner,sun5i-a13-mmc";
267 reg = <0x01c11000 0x1000>;
268 clocks = <&ahb1_gates 10>, <&mmc2_clk>;
269 clock-names = "ahb", "mmc";
270 resets = <&ahb1_rst 10>;
272 interrupts = <0 62 4>;
276 pio: pinctrl@01c20800 {
277 compatible = "allwinner,sun8i-a23-pinctrl";
278 reg = <0x01c20800 0x400>;
279 interrupts = <0 11 4>,
282 clocks = <&apb1_gates 5>;
284 interrupt-controller;
285 #address-cells = <1>;
289 uart0_pins_a: uart0@0 {
290 allwinner,pins = "PF2", "PF4";
291 allwinner,function = "uart0";
292 allwinner,drive = <0>;
293 allwinner,pull = <0>;
296 mmc0_pins_a: mmc0@0 {
297 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
298 allwinner,function = "mmc0";
299 allwinner,drive = <2>;
300 allwinner,pull = <0>;
303 mmc1_pins_a: mmc1@0 {
304 allwinner,pins = "PG0","PG1","PG2","PG3","PG4","PG5";
305 allwinner,function = "mmc1";
306 allwinner,drive = <2>;
307 allwinner,pull = <0>;
310 i2c0_pins_a: i2c0@0 {
311 allwinner,pins = "PH2", "PH3";
312 allwinner,function = "i2c0";
313 allwinner,drive = <0>;
314 allwinner,pull = <0>;
317 i2c1_pins_a: i2c1@0 {
318 allwinner,pins = "PH4", "PH5";
319 allwinner,function = "i2c1";
320 allwinner,drive = <0>;
321 allwinner,pull = <0>;
324 i2c2_pins_a: i2c2@0 {
325 allwinner,pins = "PE12", "PE13";
326 allwinner,function = "i2c2";
327 allwinner,drive = <0>;
328 allwinner,pull = <0>;
332 ahb1_rst: reset@01c202c0 {
334 compatible = "allwinner,sun6i-a31-clock-reset";
335 reg = <0x01c202c0 0xc>;
338 apb1_rst: reset@01c202d0 {
340 compatible = "allwinner,sun6i-a31-clock-reset";
341 reg = <0x01c202d0 0x4>;
344 apb2_rst: reset@01c202d8 {
346 compatible = "allwinner,sun6i-a31-clock-reset";
347 reg = <0x01c202d8 0x4>;
351 compatible = "allwinner,sun4i-a10-timer";
352 reg = <0x01c20c00 0xa0>;
353 interrupts = <0 18 4>,
358 wdt0: watchdog@01c20ca0 {
359 compatible = "allwinner,sun6i-a31-wdt";
360 reg = <0x01c20ca0 0x20>;
361 interrupts = <0 25 4>;
364 uart0: serial@01c28000 {
365 compatible = "snps,dw-apb-uart";
366 reg = <0x01c28000 0x400>;
367 interrupts = <0 0 4>;
370 clocks = <&apb2_gates 16>;
371 resets = <&apb2_rst 16>;
372 dmas = <&dma 6>, <&dma 6>;
373 dma-names = "rx", "tx";
377 uart1: serial@01c28400 {
378 compatible = "snps,dw-apb-uart";
379 reg = <0x01c28400 0x400>;
380 interrupts = <0 1 4>;
383 clocks = <&apb2_gates 17>;
384 resets = <&apb2_rst 17>;
385 dmas = <&dma 7>, <&dma 7>;
386 dma-names = "rx", "tx";
390 uart2: serial@01c28800 {
391 compatible = "snps,dw-apb-uart";
392 reg = <0x01c28800 0x400>;
393 interrupts = <0 2 4>;
396 clocks = <&apb2_gates 18>;
397 resets = <&apb2_rst 18>;
398 dmas = <&dma 8>, <&dma 8>;
399 dma-names = "rx", "tx";
403 uart3: serial@01c28c00 {
404 compatible = "snps,dw-apb-uart";
405 reg = <0x01c28c00 0x400>;
406 interrupts = <0 3 4>;
409 clocks = <&apb2_gates 19>;
410 resets = <&apb2_rst 19>;
411 dmas = <&dma 9>, <&dma 9>;
412 dma-names = "rx", "tx";
416 uart4: serial@01c29000 {
417 compatible = "snps,dw-apb-uart";
418 reg = <0x01c29000 0x400>;
419 interrupts = <0 4 4>;
422 clocks = <&apb2_gates 20>;
423 resets = <&apb2_rst 20>;
424 dmas = <&dma 10>, <&dma 10>;
425 dma-names = "rx", "tx";
430 compatible = "allwinner,sun6i-a31-i2c";
431 reg = <0x01c2ac00 0x400>;
432 interrupts = <0 6 4>;
433 clocks = <&apb2_gates 0>;
434 resets = <&apb2_rst 0>;
436 #address-cells = <1>;
441 compatible = "allwinner,sun6i-a31-i2c";
442 reg = <0x01c2b000 0x400>;
443 interrupts = <0 7 4>;
444 clocks = <&apb2_gates 1>;
445 resets = <&apb2_rst 1>;
447 #address-cells = <1>;
452 compatible = "allwinner,sun6i-a31-i2c";
453 reg = <0x01c2b400 0x400>;
454 interrupts = <0 8 4>;
455 clocks = <&apb2_gates 2>;
456 resets = <&apb2_rst 2>;
458 #address-cells = <1>;
462 gic: interrupt-controller@01c81000 {
463 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
464 reg = <0x01c81000 0x1000>,
468 interrupt-controller;
469 #interrupt-cells = <3>;
470 interrupts = <1 9 0xf04>;
474 compatible = "allwinner,sun6i-a31-rtc";
475 reg = <0x01f00000 0x54>;
476 interrupts = <0 40 4>, <0 41 4>;
480 compatible = "allwinner,sun8i-a23-prcm";
481 reg = <0x01f01400 0x200>;
484 compatible = "fixed-factor-clock";
489 clock-output-names = "ar100";
493 compatible = "fixed-factor-clock";
498 clock-output-names = "ahb0";
502 compatible = "allwinner,sun8i-a23-apb0-clk";
505 clock-output-names = "apb0";
508 apb0_gates: apb0_gates_clk {
509 compatible = "allwinner,sun8i-a23-apb0-gates-clk";
512 clock-output-names = "apb0_pio", "apb0_timer",
513 "apb0_rsb", "apb0_uart",
518 compatible = "allwinner,sun6i-a31-clock-reset";
523 r_uart: serial@01f02800 {
524 compatible = "snps,dw-apb-uart";
525 reg = <0x01f02800 0x400>;
526 interrupts = <0 38 4>;
529 clocks = <&apb0_gates 4>;
530 resets = <&apb0_rst 4>;
534 r_pio: pinctrl@01f02c00 {
535 compatible = "allwinner,sun8i-a23-r-pinctrl";
536 reg = <0x01f02c00 0x400>;
537 interrupts = <0 45 4>;
538 clocks = <&apb0_gates 0>;
539 resets = <&apb0_rst 0>;
541 interrupt-controller;
542 #address-cells = <1>;
546 r_uart_pins_a: r_uart@0 {
547 allwinner,pins = "PL2", "PL3";
548 allwinner,function = "s_uart";
549 allwinner,drive = <0>;
550 allwinner,pull = <0>;