2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
50 #include "skeleton.dtsi"
52 #include <dt-bindings/interrupt-controller/arm-gic.h>
54 #include <dt-bindings/pinctrl/sun4i-a10.h>
57 interrupt-parent = <&gic>;
65 compatible = "allwinner,simple-framebuffer",
67 allwinner,pipeline = "de_be0-lcd0";
78 compatible = "arm,cortex-a7";
84 compatible = "arm,cortex-a7";
91 reg = <0x40000000 0x40000000>;
101 compatible = "fixed-clock";
102 clock-frequency = <24000000>;
103 clock-output-names = "osc24M";
108 compatible = "fixed-clock";
109 clock-frequency = <32768>;
110 clock-output-names = "osc32k";
115 compatible = "allwinner,sun8i-a23-pll1-clk";
116 reg = <0x01c20000 0x4>;
118 clock-output-names = "pll1";
121 /* dummy clock until actually implemented */
124 compatible = "fixed-clock";
125 clock-frequency = <0>;
126 clock-output-names = "pll5";
131 compatible = "allwinner,sun6i-a31-pll6-clk";
132 reg = <0x01c20028 0x4>;
134 clock-output-names = "pll6", "pll6x2";
137 cpu: cpu_clk@01c20050 {
139 compatible = "allwinner,sun4i-a10-cpu-clk";
140 reg = <0x01c20050 0x4>;
143 * PLL1 is listed twice here.
144 * While it looks suspicious, it's actually documented
145 * that way both in the datasheet and in the code from
148 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
149 clock-output-names = "cpu";
152 axi: axi_clk@01c20050 {
154 compatible = "allwinner,sun8i-a23-axi-clk";
155 reg = <0x01c20050 0x4>;
157 clock-output-names = "axi";
160 ahb1: ahb1_clk@01c20054 {
162 compatible = "allwinner,sun6i-a31-ahb1-clk";
163 reg = <0x01c20054 0x4>;
164 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
165 clock-output-names = "ahb1";
168 apb1: apb1_clk@01c20054 {
170 compatible = "allwinner,sun4i-a10-apb0-clk";
171 reg = <0x01c20054 0x4>;
173 clock-output-names = "apb1";
176 ahb1_gates: clk@01c20060 {
178 compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
179 reg = <0x01c20060 0x8>;
181 clock-output-names = "ahb1_mipidsi", "ahb1_dma",
182 "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
183 "ahb1_nand", "ahb1_sdram",
184 "ahb1_hstimer", "ahb1_spi0",
185 "ahb1_spi1", "ahb1_otg", "ahb1_ehci",
186 "ahb1_ohci", "ahb1_ve", "ahb1_lcd",
187 "ahb1_csi", "ahb1_be", "ahb1_fe",
188 "ahb1_gpu", "ahb1_spinlock",
192 apb1_gates: clk@01c20068 {
194 compatible = "allwinner,sun8i-a23-apb1-gates-clk";
195 reg = <0x01c20068 0x4>;
197 clock-output-names = "apb1_codec", "apb1_pio",
198 "apb1_daudio0", "apb1_daudio1";
203 compatible = "allwinner,sun4i-a10-apb1-clk";
204 reg = <0x01c20058 0x4>;
205 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
206 clock-output-names = "apb2";
209 apb2_gates: clk@01c2006c {
211 compatible = "allwinner,sun8i-a23-apb2-gates-clk";
212 reg = <0x01c2006c 0x4>;
214 clock-output-names = "apb2_i2c0", "apb2_i2c1",
215 "apb2_i2c2", "apb2_uart0",
216 "apb2_uart1", "apb2_uart2",
217 "apb2_uart3", "apb2_uart4";
220 mmc0_clk: clk@01c20088 {
222 compatible = "allwinner,sun4i-a10-mmc-clk";
223 reg = <0x01c20088 0x4>;
224 clocks = <&osc24M>, <&pll6 0>;
225 clock-output-names = "mmc0",
230 mmc1_clk: clk@01c2008c {
232 compatible = "allwinner,sun4i-a10-mmc-clk";
233 reg = <0x01c2008c 0x4>;
234 clocks = <&osc24M>, <&pll6 0>;
235 clock-output-names = "mmc1",
240 mmc2_clk: clk@01c20090 {
242 compatible = "allwinner,sun4i-a10-mmc-clk";
243 reg = <0x01c20090 0x4>;
244 clocks = <&osc24M>, <&pll6 0>;
245 clock-output-names = "mmc2",
250 mbus_clk: clk@01c2015c {
252 compatible = "allwinner,sun8i-a23-mbus-clk";
253 reg = <0x01c2015c 0x4>;
254 clocks = <&osc24M>, <&pll6 1>, <&pll5>;
255 clock-output-names = "mbus";
260 compatible = "simple-bus";
261 #address-cells = <1>;
265 dma: dma-controller@01c02000 {
266 compatible = "allwinner,sun8i-a23-dma";
267 reg = <0x01c02000 0x1000>;
268 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&ahb1_gates 6>;
270 resets = <&ahb1_rst 6>;
275 compatible = "allwinner,sun5i-a13-mmc";
276 reg = <0x01c0f000 0x1000>;
277 clocks = <&ahb1_gates 8>,
285 resets = <&ahb1_rst 8>;
287 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
292 compatible = "allwinner,sun5i-a13-mmc";
293 reg = <0x01c10000 0x1000>;
294 clocks = <&ahb1_gates 9>,
302 resets = <&ahb1_rst 9>;
304 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
309 compatible = "allwinner,sun5i-a13-mmc";
310 reg = <0x01c11000 0x1000>;
311 clocks = <&ahb1_gates 10>,
319 resets = <&ahb1_rst 10>;
321 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
325 pio: pinctrl@01c20800 {
326 compatible = "allwinner,sun8i-a23-pinctrl";
327 reg = <0x01c20800 0x400>;
328 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
329 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
331 clocks = <&apb1_gates 5>;
333 interrupt-controller;
334 #address-cells = <1>;
338 uart0_pins_a: uart0@0 {
339 allwinner,pins = "PF2", "PF4";
340 allwinner,function = "uart0";
341 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
342 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
345 mmc0_pins_a: mmc0@0 {
346 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
347 allwinner,function = "mmc0";
348 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
349 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
352 mmc1_pins_a: mmc1@0 {
353 allwinner,pins = "PG0","PG1","PG2","PG3","PG4","PG5";
354 allwinner,function = "mmc1";
355 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
356 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
359 i2c0_pins_a: i2c0@0 {
360 allwinner,pins = "PH2", "PH3";
361 allwinner,function = "i2c0";
362 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
363 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
366 i2c1_pins_a: i2c1@0 {
367 allwinner,pins = "PH4", "PH5";
368 allwinner,function = "i2c1";
369 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
370 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
373 i2c2_pins_a: i2c2@0 {
374 allwinner,pins = "PE12", "PE13";
375 allwinner,function = "i2c2";
376 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
377 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
381 ahb1_rst: reset@01c202c0 {
383 compatible = "allwinner,sun6i-a31-clock-reset";
384 reg = <0x01c202c0 0xc>;
387 apb1_rst: reset@01c202d0 {
389 compatible = "allwinner,sun6i-a31-clock-reset";
390 reg = <0x01c202d0 0x4>;
393 apb2_rst: reset@01c202d8 {
395 compatible = "allwinner,sun6i-a31-clock-reset";
396 reg = <0x01c202d8 0x4>;
400 compatible = "allwinner,sun4i-a10-timer";
401 reg = <0x01c20c00 0xa0>;
402 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
403 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
407 wdt0: watchdog@01c20ca0 {
408 compatible = "allwinner,sun6i-a31-wdt";
409 reg = <0x01c20ca0 0x20>;
410 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
413 lradc: lradc@01c22800 {
414 compatible = "allwinner,sun4i-a10-lradc-keys";
415 reg = <0x01c22800 0x100>;
416 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
420 uart0: serial@01c28000 {
421 compatible = "snps,dw-apb-uart";
422 reg = <0x01c28000 0x400>;
423 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
426 clocks = <&apb2_gates 16>;
427 resets = <&apb2_rst 16>;
428 dmas = <&dma 6>, <&dma 6>;
429 dma-names = "rx", "tx";
433 uart1: serial@01c28400 {
434 compatible = "snps,dw-apb-uart";
435 reg = <0x01c28400 0x400>;
436 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
439 clocks = <&apb2_gates 17>;
440 resets = <&apb2_rst 17>;
441 dmas = <&dma 7>, <&dma 7>;
442 dma-names = "rx", "tx";
446 uart2: serial@01c28800 {
447 compatible = "snps,dw-apb-uart";
448 reg = <0x01c28800 0x400>;
449 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
452 clocks = <&apb2_gates 18>;
453 resets = <&apb2_rst 18>;
454 dmas = <&dma 8>, <&dma 8>;
455 dma-names = "rx", "tx";
459 uart3: serial@01c28c00 {
460 compatible = "snps,dw-apb-uart";
461 reg = <0x01c28c00 0x400>;
462 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
465 clocks = <&apb2_gates 19>;
466 resets = <&apb2_rst 19>;
467 dmas = <&dma 9>, <&dma 9>;
468 dma-names = "rx", "tx";
472 uart4: serial@01c29000 {
473 compatible = "snps,dw-apb-uart";
474 reg = <0x01c29000 0x400>;
475 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
478 clocks = <&apb2_gates 20>;
479 resets = <&apb2_rst 20>;
480 dmas = <&dma 10>, <&dma 10>;
481 dma-names = "rx", "tx";
486 compatible = "allwinner,sun6i-a31-i2c";
487 reg = <0x01c2ac00 0x400>;
488 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
489 clocks = <&apb2_gates 0>;
490 resets = <&apb2_rst 0>;
492 #address-cells = <1>;
497 compatible = "allwinner,sun6i-a31-i2c";
498 reg = <0x01c2b000 0x400>;
499 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
500 clocks = <&apb2_gates 1>;
501 resets = <&apb2_rst 1>;
503 #address-cells = <1>;
508 compatible = "allwinner,sun6i-a31-i2c";
509 reg = <0x01c2b400 0x400>;
510 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
511 clocks = <&apb2_gates 2>;
512 resets = <&apb2_rst 2>;
514 #address-cells = <1>;
518 gic: interrupt-controller@01c81000 {
519 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
520 reg = <0x01c81000 0x1000>,
524 interrupt-controller;
525 #interrupt-cells = <3>;
526 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
530 compatible = "allwinner,sun6i-a31-rtc";
531 reg = <0x01f00000 0x54>;
532 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
533 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
537 compatible = "allwinner,sun8i-a23-prcm";
538 reg = <0x01f01400 0x200>;
541 compatible = "fixed-factor-clock";
546 clock-output-names = "ar100";
550 compatible = "fixed-factor-clock";
555 clock-output-names = "ahb0";
559 compatible = "allwinner,sun8i-a23-apb0-clk";
562 clock-output-names = "apb0";
565 apb0_gates: apb0_gates_clk {
566 compatible = "allwinner,sun8i-a23-apb0-gates-clk";
569 clock-output-names = "apb0_pio", "apb0_timer",
570 "apb0_rsb", "apb0_uart",
575 compatible = "allwinner,sun6i-a31-clock-reset";
580 r_uart: serial@01f02800 {
581 compatible = "snps,dw-apb-uart";
582 reg = <0x01f02800 0x400>;
583 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
586 clocks = <&apb0_gates 4>;
587 resets = <&apb0_rst 4>;
591 r_pio: pinctrl@01f02c00 {
592 compatible = "allwinner,sun8i-a23-r-pinctrl";
593 reg = <0x01f02c00 0x400>;
594 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
595 clocks = <&apb0_gates 0>;
596 resets = <&apb0_rst 0>;
598 interrupt-controller;
599 #address-cells = <1>;
603 r_uart_pins_a: r_uart@0 {
604 allwinner,pins = "PL2", "PL3";
605 allwinner,function = "s_uart";
606 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
607 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;