2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
50 /include/ "skeleton.dtsi"
53 interrupt-parent = <&gic>;
69 compatible = "arm,cortex-a7";
75 compatible = "arm,cortex-a7";
82 reg = <0x40000000 0x40000000>;
92 compatible = "fixed-clock";
93 clock-frequency = <24000000>;
94 clock-output-names = "osc24M";
99 compatible = "fixed-clock";
100 clock-frequency = <32768>;
101 clock-output-names = "osc32k";
106 compatible = "allwinner,sun8i-a23-pll1-clk";
107 reg = <0x01c20000 0x4>;
109 clock-output-names = "pll1";
112 /* dummy clock until actually implemented */
115 compatible = "fixed-clock";
116 clock-frequency = <600000000>;
117 clock-output-names = "pll6";
120 cpu: cpu_clk@01c20050 {
122 compatible = "allwinner,sun4i-a10-cpu-clk";
123 reg = <0x01c20050 0x4>;
126 * PLL1 is listed twice here.
127 * While it looks suspicious, it's actually documented
128 * that way both in the datasheet and in the code from
131 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
132 clock-output-names = "cpu";
135 axi: axi_clk@01c20050 {
137 compatible = "allwinner,sun8i-a23-axi-clk";
138 reg = <0x01c20050 0x4>;
140 clock-output-names = "axi";
143 ahb1_mux: ahb1_mux_clk@01c20054 {
145 compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
146 reg = <0x01c20054 0x4>;
147 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
148 clock-output-names = "ahb1_mux";
151 ahb1: ahb1_clk@01c20054 {
153 compatible = "allwinner,sun4i-a10-ahb-clk";
154 reg = <0x01c20054 0x4>;
155 clocks = <&ahb1_mux>;
156 clock-output-names = "ahb1";
159 apb1: apb1_clk@01c20054 {
161 compatible = "allwinner,sun4i-a10-apb0-clk";
162 reg = <0x01c20054 0x4>;
164 clock-output-names = "apb1";
167 ahb1_gates: clk@01c20060 {
169 compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
170 reg = <0x01c20060 0x8>;
172 clock-output-names = "ahb1_mipidsi", "ahb1_dma",
173 "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
174 "ahb1_nand", "ahb1_sdram",
175 "ahb1_hstimer", "ahb1_spi0",
176 "ahb1_spi1", "ahb1_otg", "ahb1_ehci",
177 "ahb1_ohci", "ahb1_ve", "ahb1_lcd",
178 "ahb1_csi", "ahb1_be", "ahb1_fe",
179 "ahb1_gpu", "ahb1_spinlock",
183 apb1_gates: clk@01c20068 {
185 compatible = "allwinner,sun8i-a23-apb1-gates-clk";
186 reg = <0x01c20068 0x4>;
188 clock-output-names = "apb1_codec", "apb1_pio",
189 "apb1_daudio0", "apb1_daudio1";
192 apb2_mux: apb2_mux_clk@01c20058 {
194 compatible = "allwinner,sun4i-a10-apb1-mux-clk";
195 reg = <0x01c20058 0x4>;
196 clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
197 clock-output-names = "apb2_mux";
200 apb2: apb2_clk@01c20058 {
202 compatible = "allwinner,sun6i-a31-apb2-div-clk";
203 reg = <0x01c20058 0x4>;
204 clocks = <&apb2_mux>;
205 clock-output-names = "apb2";
208 apb2_gates: clk@01c2006c {
210 compatible = "allwinner,sun8i-a23-apb2-gates-clk";
211 reg = <0x01c2006c 0x4>;
213 clock-output-names = "apb2_i2c0", "apb2_i2c1",
214 "apb2_i2c2", "apb2_uart0",
215 "apb2_uart1", "apb2_uart2",
216 "apb2_uart3", "apb2_uart4";
219 mmc0_clk: clk@01c20088 {
221 compatible = "allwinner,sun4i-a10-mod0-clk";
222 reg = <0x01c20088 0x4>;
223 clocks = <&osc24M>, <&pll6>;
224 clock-output-names = "mmc0";
227 mmc1_clk: clk@01c2008c {
229 compatible = "allwinner,sun4i-a10-mod0-clk";
230 reg = <0x01c2008c 0x4>;
231 clocks = <&osc24M>, <&pll6>;
232 clock-output-names = "mmc1";
235 mmc2_clk: clk@01c20090 {
237 compatible = "allwinner,sun4i-a10-mod0-clk";
238 reg = <0x01c20090 0x4>;
239 clocks = <&osc24M>, <&pll6>;
240 clock-output-names = "mmc2";
245 compatible = "simple-bus";
246 #address-cells = <1>;
250 dma: dma-controller@01c02000 {
251 compatible = "allwinner,sun8i-a23-dma";
252 reg = <0x01c02000 0x1000>;
253 interrupts = <0 50 4>;
254 clocks = <&ahb1_gates 6>;
255 resets = <&ahb1_rst 6>;
260 compatible = "allwinner,sun5i-a13-mmc";
261 reg = <0x01c0f000 0x1000>;
262 clocks = <&ahb1_gates 8>, <&mmc0_clk>;
263 clock-names = "ahb", "mmc";
264 resets = <&ahb1_rst 8>;
266 interrupts = <0 60 4>;
271 compatible = "allwinner,sun5i-a13-mmc";
272 reg = <0x01c10000 0x1000>;
273 clocks = <&ahb1_gates 9>, <&mmc1_clk>;
274 clock-names = "ahb", "mmc";
275 resets = <&ahb1_rst 9>;
277 interrupts = <0 61 4>;
282 compatible = "allwinner,sun5i-a13-mmc";
283 reg = <0x01c11000 0x1000>;
284 clocks = <&ahb1_gates 10>, <&mmc2_clk>;
285 clock-names = "ahb", "mmc";
286 resets = <&ahb1_rst 10>;
288 interrupts = <0 62 4>;
292 pio: pinctrl@01c20800 {
293 compatible = "allwinner,sun8i-a23-pinctrl";
294 reg = <0x01c20800 0x400>;
295 interrupts = <0 11 4>,
298 clocks = <&apb1_gates 5>;
300 interrupt-controller;
301 #address-cells = <1>;
305 uart0_pins_a: uart0@0 {
306 allwinner,pins = "PF2", "PF4";
307 allwinner,function = "uart0";
308 allwinner,drive = <0>;
309 allwinner,pull = <0>;
312 mmc0_pins_a: mmc0@0 {
313 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
314 allwinner,function = "mmc0";
315 allwinner,drive = <2>;
316 allwinner,pull = <0>;
319 mmc1_pins_a: mmc1@0 {
320 allwinner,pins = "PG0","PG1","PG2","PG3","PG4","PG5";
321 allwinner,function = "mmc1";
322 allwinner,drive = <2>;
323 allwinner,pull = <0>;
326 i2c0_pins_a: i2c0@0 {
327 allwinner,pins = "PH2", "PH3";
328 allwinner,function = "i2c0";
329 allwinner,drive = <0>;
330 allwinner,pull = <0>;
333 i2c1_pins_a: i2c1@0 {
334 allwinner,pins = "PH4", "PH5";
335 allwinner,function = "i2c1";
336 allwinner,drive = <0>;
337 allwinner,pull = <0>;
340 i2c2_pins_a: i2c2@0 {
341 allwinner,pins = "PE12", "PE13";
342 allwinner,function = "i2c2";
343 allwinner,drive = <0>;
344 allwinner,pull = <0>;
348 ahb1_rst: reset@01c202c0 {
350 compatible = "allwinner,sun6i-a31-clock-reset";
351 reg = <0x01c202c0 0xc>;
354 apb1_rst: reset@01c202d0 {
356 compatible = "allwinner,sun6i-a31-clock-reset";
357 reg = <0x01c202d0 0x4>;
360 apb2_rst: reset@01c202d8 {
362 compatible = "allwinner,sun6i-a31-clock-reset";
363 reg = <0x01c202d8 0x4>;
367 compatible = "allwinner,sun4i-a10-timer";
368 reg = <0x01c20c00 0xa0>;
369 interrupts = <0 18 4>,
374 wdt0: watchdog@01c20ca0 {
375 compatible = "allwinner,sun6i-a31-wdt";
376 reg = <0x01c20ca0 0x20>;
377 interrupts = <0 25 4>;
380 uart0: serial@01c28000 {
381 compatible = "snps,dw-apb-uart";
382 reg = <0x01c28000 0x400>;
383 interrupts = <0 0 4>;
386 clocks = <&apb2_gates 16>;
387 resets = <&apb2_rst 16>;
388 dmas = <&dma 6>, <&dma 6>;
389 dma-names = "rx", "tx";
393 uart1: serial@01c28400 {
394 compatible = "snps,dw-apb-uart";
395 reg = <0x01c28400 0x400>;
396 interrupts = <0 1 4>;
399 clocks = <&apb2_gates 17>;
400 resets = <&apb2_rst 17>;
401 dmas = <&dma 7>, <&dma 7>;
402 dma-names = "rx", "tx";
406 uart2: serial@01c28800 {
407 compatible = "snps,dw-apb-uart";
408 reg = <0x01c28800 0x400>;
409 interrupts = <0 2 4>;
412 clocks = <&apb2_gates 18>;
413 resets = <&apb2_rst 18>;
414 dmas = <&dma 8>, <&dma 8>;
415 dma-names = "rx", "tx";
419 uart3: serial@01c28c00 {
420 compatible = "snps,dw-apb-uart";
421 reg = <0x01c28c00 0x400>;
422 interrupts = <0 3 4>;
425 clocks = <&apb2_gates 19>;
426 resets = <&apb2_rst 19>;
427 dmas = <&dma 9>, <&dma 9>;
428 dma-names = "rx", "tx";
432 uart4: serial@01c29000 {
433 compatible = "snps,dw-apb-uart";
434 reg = <0x01c29000 0x400>;
435 interrupts = <0 4 4>;
438 clocks = <&apb2_gates 20>;
439 resets = <&apb2_rst 20>;
440 dmas = <&dma 10>, <&dma 10>;
441 dma-names = "rx", "tx";
446 compatible = "allwinner,sun6i-a31-i2c";
447 reg = <0x01c2ac00 0x400>;
448 interrupts = <0 6 4>;
449 clocks = <&apb2_gates 0>;
450 resets = <&apb2_rst 0>;
452 #address-cells = <1>;
457 compatible = "allwinner,sun6i-a31-i2c";
458 reg = <0x01c2b000 0x400>;
459 interrupts = <0 7 4>;
460 clocks = <&apb2_gates 1>;
461 resets = <&apb2_rst 1>;
463 #address-cells = <1>;
468 compatible = "allwinner,sun6i-a31-i2c";
469 reg = <0x01c2b400 0x400>;
470 interrupts = <0 8 4>;
471 clocks = <&apb2_gates 2>;
472 resets = <&apb2_rst 2>;
474 #address-cells = <1>;
478 gic: interrupt-controller@01c81000 {
479 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
480 reg = <0x01c81000 0x1000>,
484 interrupt-controller;
485 #interrupt-cells = <3>;
486 interrupts = <1 9 0xf04>;
490 compatible = "allwinner,sun6i-a31-rtc";
491 reg = <0x01f00000 0x54>;
492 interrupts = <0 40 4>, <0 41 4>;
496 compatible = "allwinner,sun8i-a23-prcm";
497 reg = <0x01f01400 0x200>;
500 compatible = "fixed-factor-clock";
505 clock-output-names = "ar100";
509 compatible = "fixed-factor-clock";
514 clock-output-names = "ahb0";
518 compatible = "allwinner,sun8i-a23-apb0-clk";
521 clock-output-names = "apb0";
524 apb0_gates: apb0_gates_clk {
525 compatible = "allwinner,sun8i-a23-apb0-gates-clk";
528 clock-output-names = "apb0_pio", "apb0_timer",
529 "apb0_rsb", "apb0_uart",
534 compatible = "allwinner,sun6i-a31-clock-reset";
539 r_uart: serial@01f02800 {
540 compatible = "snps,dw-apb-uart";
541 reg = <0x01f02800 0x400>;
542 interrupts = <0 38 4>;
545 clocks = <&apb0_gates 4>;
546 resets = <&apb0_rst 4>;
550 r_pio: pinctrl@01f02c00 {
551 compatible = "allwinner,sun8i-a23-r-pinctrl";
552 reg = <0x01f02c00 0x400>;
553 interrupts = <0 45 4>;
554 clocks = <&apb0_gates 0>;
555 resets = <&apb0_rst 0>;
557 interrupt-controller;
558 #address-cells = <1>;
562 r_uart_pins_a: r_uart@0 {
563 allwinner,pins = "PL2", "PL3";
564 allwinner,function = "s_uart";
565 allwinner,drive = <0>;
566 allwinner,pull = <0>;