arch/arm/boot/dts/sun8i-a23.dtsi

   1 /*
   2  * Copyright 2014 Chen-Yu Tsai
   3  *
   4  * Chen-Yu Tsai <wens@csie.org>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include "skeleton.dtsi"
  46
  47 #include <dt-bindings/interrupt-controller/arm-gic.h>
  48
  49 #include <dt-bindings/pinctrl/sun4i-a10.h>
  50
  51 / {
  52         interrupt-parent = <&gic>;
  53
  54         chosen {
  55                 #address-cells = <1>;
  56                 #size-cells = <1>;
  57                 ranges;
  58
  59                 framebuffer@0 {
  60                         compatible = "allwinner,simple-framebuffer",
  61                                      "simple-framebuffer";
  62                         allwinner,pipeline = "de_be0-lcd0";
  63                         clocks = <&pll6 0>;
  64                         status = "disabled";
  65                 };
  66         };
  67
  68         timer {
  69                 compatible = "arm,armv7-timer";
  70                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  71                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  72                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  73                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  74                 clock-frequency = <24000000>;
  75                 arm,cpu-registers-not-fw-configured;
  76         };
  77
  78         cpus {
  79                 enable-method = "allwinner,sun8i-a23";
  80                 #address-cells = <1>;
  81                 #size-cells = <0>;
  82
  83                 cpu@0 {
  84                         compatible = "arm,cortex-a7";
  85                         device_type = "cpu";
  86                         reg = <0>;
  87                 };
  88
  89                 cpu@1 {
  90                         compatible = "arm,cortex-a7";
  91                         device_type = "cpu";
  92                         reg = <1>;
  93                 };
  94         };
  95
  96         memory {
  97                 reg = <0x40000000 0x40000000>;
  98         };
  99
 100         clocks {
 101                 #address-cells = <1>;
 102                 #size-cells = <1>;
 103                 ranges;
 104
 105                 osc24M: osc24M_clk {
 106                         #clock-cells = <0>;
 107                         compatible = "fixed-clock";
 108                         clock-frequency = <24000000>;
 109                         clock-output-names = "osc24M";
 110                 };
 111
 112                 osc32k: osc32k_clk {
 113                         #clock-cells = <0>;
 114                         compatible = "fixed-clock";
 115                         clock-frequency = <32768>;
 116                         clock-output-names = "osc32k";
 117                 };
 118
 119                 pll1: clk@01c20000 {
 120                         #clock-cells = <0>;
 121                         compatible = "allwinner,sun8i-a23-pll1-clk";
 122                         reg = <0x01c20000 0x4>;
 123                         clocks = <&osc24M>;
 124                         clock-output-names = "pll1";
 125                 };
 126
 127                 /* dummy clock until actually implemented */
 128                 pll5: pll5_clk {
 129                         #clock-cells = <0>;
 130                         compatible = "fixed-clock";
 131                         clock-frequency = <0>;
 132                         clock-output-names = "pll5";
 133                 };
 134
 135                 pll6: clk@01c20028 {
 136                         #clock-cells = <1>;
 137                         compatible = "allwinner,sun6i-a31-pll6-clk";
 138                         reg = <0x01c20028 0x4>;
 139                         clocks = <&osc24M>;
 140                         clock-output-names = "pll6", "pll6x2";
 141                 };
 142
 143                 cpu: cpu_clk@01c20050 {
 144                         #clock-cells = <0>;
 145                         compatible = "allwinner,sun4i-a10-cpu-clk";
 146                         reg = <0x01c20050 0x4>;
 147
 148                         /*
 149                          * PLL1 is listed twice here.
 150                          * While it looks suspicious, it's actually documented
 151                          * that way both in the datasheet and in the code from
 152                          * Allwinner.
 153                          */
 154                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
 155                         clock-output-names = "cpu";
 156                 };
 157
 158                 axi: axi_clk@01c20050 {
 159                         #clock-cells = <0>;
 160                         compatible = "allwinner,sun8i-a23-axi-clk";
 161                         reg = <0x01c20050 0x4>;
 162                         clocks = <&cpu>;
 163                         clock-output-names = "axi";
 164                 };
 165
 166                 ahb1: ahb1_clk@01c20054 {
 167                         #clock-cells = <0>;
 168                         compatible = "allwinner,sun6i-a31-ahb1-clk";
 169                         reg = <0x01c20054 0x4>;
 170                         clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
 171                         clock-output-names = "ahb1";
 172                 };
 173
 174                 apb1: apb1_clk@01c20054 {
 175                         #clock-cells = <0>;
 176                         compatible = "allwinner,sun4i-a10-apb0-clk";
 177                         reg = <0x01c20054 0x4>;
 178                         clocks = <&ahb1>;
 179                         clock-output-names = "apb1";
 180                 };
 181
 182                 ahb1_gates: clk@01c20060 {
 183                         #clock-cells = <1>;
 184                         compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
 185                         reg = <0x01c20060 0x8>;
 186                         clocks = <&ahb1>;
 187                         clock-output-names = "ahb1_mipidsi", "ahb1_dma",
 188                                         "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
 189                                         "ahb1_nand", "ahb1_sdram",
 190                                         "ahb1_hstimer", "ahb1_spi0",
 191                                         "ahb1_spi1", "ahb1_otg", "ahb1_ehci",
 192                                         "ahb1_ohci", "ahb1_ve", "ahb1_lcd",
 193                                         "ahb1_csi", "ahb1_be",  "ahb1_fe",
 194                                         "ahb1_gpu", "ahb1_spinlock",
 195                                         "ahb1_drc";
 196                 };
 197
 198                 apb1_gates: clk@01c20068 {
 199                         #clock-cells = <1>;
 200                         compatible = "allwinner,sun8i-a23-apb1-gates-clk";
 201                         reg = <0x01c20068 0x4>;
 202                         clocks = <&apb1>;
 203                         clock-output-names = "apb1_codec", "apb1_pio",
 204                                         "apb1_daudio0", "apb1_daudio1";
 205                 };
 206
 207                 apb2: clk@01c20058 {
 208                         #clock-cells = <0>;
 209                         compatible = "allwinner,sun4i-a10-apb1-clk";
 210                         reg = <0x01c20058 0x4>;
 211                         clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
 212                         clock-output-names = "apb2";
 213                 };
 214
 215                 apb2_gates: clk@01c2006c {
 216                         #clock-cells = <1>;
 217                         compatible = "allwinner,sun8i-a23-apb2-gates-clk";
 218                         reg = <0x01c2006c 0x4>;
 219                         clocks = <&apb2>;
 220                         clock-output-names = "apb2_i2c0", "apb2_i2c1",
 221                                         "apb2_i2c2", "apb2_uart0",
 222                                         "apb2_uart1", "apb2_uart2",
 223                                         "apb2_uart3", "apb2_uart4";
 224                 };
 225
 226                 mmc0_clk: clk@01c20088 {
 227                         #clock-cells = <1>;
 228                         compatible = "allwinner,sun4i-a10-mmc-clk";
 229                         reg = <0x01c20088 0x4>;
 230                         clocks = <&osc24M>, <&pll6 0>;
 231                         clock-output-names = "mmc0",
 232                                              "mmc0_output",
 233                                              "mmc0_sample";
 234                 };
 235
 236                 mmc1_clk: clk@01c2008c {
 237                         #clock-cells = <1>;
 238                         compatible = "allwinner,sun4i-a10-mmc-clk";
 239                         reg = <0x01c2008c 0x4>;
 240                         clocks = <&osc24M>, <&pll6 0>;
 241                         clock-output-names = "mmc1",
 242                                              "mmc1_output",
 243                                              "mmc1_sample";
 244                 };
 245
 246                 mmc2_clk: clk@01c20090 {
 247                         #clock-cells = <1>;
 248                         compatible = "allwinner,sun4i-a10-mmc-clk";
 249                         reg = <0x01c20090 0x4>;
 250                         clocks = <&osc24M>, <&pll6 0>;
 251                         clock-output-names = "mmc2",
 252                                              "mmc2_output",
 253                                              "mmc2_sample";
 254                 };
 255
 256                 mbus_clk: clk@01c2015c {
 257                         #clock-cells = <0>;
 258                         compatible = "allwinner,sun8i-a23-mbus-clk";
 259                         reg = <0x01c2015c 0x4>;
 260                         clocks = <&osc24M>, <&pll6 1>, <&pll5>;
 261                         clock-output-names = "mbus";
 262                 };
 263         };
 264
 265         soc@01c00000 {
 266                 compatible = "simple-bus";
 267                 #address-cells = <1>;
 268                 #size-cells = <1>;
 269                 ranges;
 270
 271                 dma: dma-controller@01c02000 {
 272                         compatible = "allwinner,sun8i-a23-dma";
 273                         reg = <0x01c02000 0x1000>;
 274                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 275                         clocks = <&ahb1_gates 6>;
 276                         resets = <&ahb1_rst 6>;
 277                         #dma-cells = <1>;
 278                 };
 279
 280                 mmc0: mmc@01c0f000 {
 281                         compatible = "allwinner,sun5i-a13-mmc";
 282                         reg = <0x01c0f000 0x1000>;
 283                         clocks = <&ahb1_gates 8>,
 284                                  <&mmc0_clk 0>,
 285                                  <&mmc0_clk 1>,
 286                                  <&mmc0_clk 2>;
 287                         clock-names = "ahb",
 288                                       "mmc",
 289                                       "output",
 290                                       "sample";
 291                         resets = <&ahb1_rst 8>;
 292                         reset-names = "ahb";
 293                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 294                         status = "disabled";
 295                         #address-cells = <1>;
 296                         #size-cells = <0>;
 297                 };
 298
 299                 mmc1: mmc@01c10000 {
 300                         compatible = "allwinner,sun5i-a13-mmc";
 301                         reg = <0x01c10000 0x1000>;
 302                         clocks = <&ahb1_gates 9>,
 303                                  <&mmc1_clk 0>,
 304                                  <&mmc1_clk 1>,
 305                                  <&mmc1_clk 2>;
 306                         clock-names = "ahb",
 307                                       "mmc",
 308                                       "output",
 309                                       "sample";
 310                         resets = <&ahb1_rst 9>;
 311                         reset-names = "ahb";
 312                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 313                         status = "disabled";
 314                         #address-cells = <1>;
 315                         #size-cells = <0>;
 316                 };
 317
 318                 mmc2: mmc@01c11000 {
 319                         compatible = "allwinner,sun5i-a13-mmc";
 320                         reg = <0x01c11000 0x1000>;
 321                         clocks = <&ahb1_gates 10>,
 322                                  <&mmc2_clk 0>,
 323                                  <&mmc2_clk 1>,
 324                                  <&mmc2_clk 2>;
 325                         clock-names = "ahb",
 326                                       "mmc",
 327                                       "output",
 328                                       "sample";
 329                         resets = <&ahb1_rst 10>;
 330                         reset-names = "ahb";
 331                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 332                         status = "disabled";
 333                         #address-cells = <1>;
 334                         #size-cells = <0>;
 335                 };
 336
 337                 pio: pinctrl@01c20800 {
 338                         compatible = "allwinner,sun8i-a23-pinctrl";
 339                         reg = <0x01c20800 0x400>;
 340                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 341                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 342                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 343                         clocks = <&apb1_gates 5>;
 344                         gpio-controller;
 345                         interrupt-controller;
 346                         #address-cells = <1>;
 347                         #size-cells = <0>;
 348                         #gpio-cells = <3>;
 349
 350                         uart0_pins_a: uart0@0 {
 351                                 allwinner,pins = "PF2", "PF4";
 352                                 allwinner,function = "uart0";
 353                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 354                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 355                         };
 356
 357                         mmc0_pins_a: mmc0@0 {
 358                                 allwinner,pins = "PF0", "PF1", "PF2",
 359                                                  "PF3", "PF4", "PF5";
 360                                 allwinner,function = "mmc0";
 361                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 362                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 363                         };
 364
 365                         mmc1_pins_a: mmc1@0 {
 366                                 allwinner,pins = "PG0", "PG1", "PG2",
 367                                                  "PG3", "PG4", "PG5";
 368                                 allwinner,function = "mmc1";
 369                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 370                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 371                         };
 372
 373                         i2c0_pins_a: i2c0@0 {
 374                                 allwinner,pins = "PH2", "PH3";
 375                                 allwinner,function = "i2c0";
 376                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 377                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 378                         };
 379
 380                         i2c1_pins_a: i2c1@0 {
 381                                 allwinner,pins = "PH4", "PH5";
 382                                 allwinner,function = "i2c1";
 383                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 384                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 385                         };
 386
 387                         i2c2_pins_a: i2c2@0 {
 388                                 allwinner,pins = "PE12", "PE13";
 389                                 allwinner,function = "i2c2";
 390                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 391                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 392                         };
 393                 };
 394
 395                 ahb1_rst: reset@01c202c0 {
 396                         #reset-cells = <1>;
 397                         compatible = "allwinner,sun6i-a31-clock-reset";
 398                         reg = <0x01c202c0 0xc>;
 399                 };
 400
 401                 apb1_rst: reset@01c202d0 {
 402                         #reset-cells = <1>;
 403                         compatible = "allwinner,sun6i-a31-clock-reset";
 404                         reg = <0x01c202d0 0x4>;
 405                 };
 406
 407                 apb2_rst: reset@01c202d8 {
 408                         #reset-cells = <1>;
 409                         compatible = "allwinner,sun6i-a31-clock-reset";
 410                         reg = <0x01c202d8 0x4>;
 411                 };
 412
 413                 timer@01c20c00 {
 414                         compatible = "allwinner,sun4i-a10-timer";
 415                         reg = <0x01c20c00 0xa0>;
 416                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 417                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 418                         clocks = <&osc24M>;
 419                 };
 420
 421                 wdt0: watchdog@01c20ca0 {
 422                         compatible = "allwinner,sun6i-a31-wdt";
 423                         reg = <0x01c20ca0 0x20>;
 424                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 425                 };
 426
 427                 lradc: lradc@01c22800 {
 428                         compatible = "allwinner,sun4i-a10-lradc-keys";
 429                         reg = <0x01c22800 0x100>;
 430                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 431                         status = "disabled";
 432                 };
 433
 434                 uart0: serial@01c28000 {
 435                         compatible = "snps,dw-apb-uart";
 436                         reg = <0x01c28000 0x400>;
 437                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 438                         reg-shift = <2>;
 439                         reg-io-width = <4>;
 440                         clocks = <&apb2_gates 16>;
 441                         resets = <&apb2_rst 16>;
 442                         dmas = <&dma 6>, <&dma 6>;
 443                         dma-names = "rx", "tx";
 444                         status = "disabled";
 445                 };
 446
 447                 uart1: serial@01c28400 {
 448                         compatible = "snps,dw-apb-uart";
 449                         reg = <0x01c28400 0x400>;
 450                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 451                         reg-shift = <2>;
 452                         reg-io-width = <4>;
 453                         clocks = <&apb2_gates 17>;
 454                         resets = <&apb2_rst 17>;
 455                         dmas = <&dma 7>, <&dma 7>;
 456                         dma-names = "rx", "tx";
 457                         status = "disabled";
 458                 };
 459
 460                 uart2: serial@01c28800 {
 461                         compatible = "snps,dw-apb-uart";
 462                         reg = <0x01c28800 0x400>;
 463                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 464                         reg-shift = <2>;
 465                         reg-io-width = <4>;
 466                         clocks = <&apb2_gates 18>;
 467                         resets = <&apb2_rst 18>;
 468                         dmas = <&dma 8>, <&dma 8>;
 469                         dma-names = "rx", "tx";
 470                         status = "disabled";
 471                 };
 472
 473                 uart3: serial@01c28c00 {
 474                         compatible = "snps,dw-apb-uart";
 475                         reg = <0x01c28c00 0x400>;
 476                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 477                         reg-shift = <2>;
 478                         reg-io-width = <4>;
 479                         clocks = <&apb2_gates 19>;
 480                         resets = <&apb2_rst 19>;
 481                         dmas = <&dma 9>, <&dma 9>;
 482                         dma-names = "rx", "tx";
 483                         status = "disabled";
 484                 };
 485
 486                 uart4: serial@01c29000 {
 487                         compatible = "snps,dw-apb-uart";
 488                         reg = <0x01c29000 0x400>;
 489                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 490                         reg-shift = <2>;
 491                         reg-io-width = <4>;
 492                         clocks = <&apb2_gates 20>;
 493                         resets = <&apb2_rst 20>;
 494                         dmas = <&dma 10>, <&dma 10>;
 495                         dma-names = "rx", "tx";
 496                         status = "disabled";
 497                 };
 498
 499                 i2c0: i2c@01c2ac00 {
 500                         compatible = "allwinner,sun6i-a31-i2c";
 501                         reg = <0x01c2ac00 0x400>;
 502                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 503                         clocks = <&apb2_gates 0>;
 504                         resets = <&apb2_rst 0>;
 505                         status = "disabled";
 506                         #address-cells = <1>;
 507                         #size-cells = <0>;
 508                 };
 509
 510                 i2c1: i2c@01c2b000 {
 511                         compatible = "allwinner,sun6i-a31-i2c";
 512                         reg = <0x01c2b000 0x400>;
 513                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 514                         clocks = <&apb2_gates 1>;
 515                         resets = <&apb2_rst 1>;
 516                         status = "disabled";
 517                         #address-cells = <1>;
 518                         #size-cells = <0>;
 519                 };
 520
 521                 i2c2: i2c@01c2b400 {
 522                         compatible = "allwinner,sun6i-a31-i2c";
 523                         reg = <0x01c2b400 0x400>;
 524                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 525                         clocks = <&apb2_gates 2>;
 526                         resets = <&apb2_rst 2>;
 527                         status = "disabled";
 528                         #address-cells = <1>;
 529                         #size-cells = <0>;
 530                 };
 531
 532                 gic: interrupt-controller@01c81000 {
 533                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 534                         reg = <0x01c81000 0x1000>,
 535                               <0x01c82000 0x1000>,
 536                               <0x01c84000 0x2000>,
 537                               <0x01c86000 0x2000>;
 538                         interrupt-controller;
 539                         #interrupt-cells = <3>;
 540                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 541                 };
 542
 543                 rtc: rtc@01f00000 {
 544                         compatible = "allwinner,sun6i-a31-rtc";
 545                         reg = <0x01f00000 0x54>;
 546                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 547                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 548                 };
 549
 550                 prcm@01f01400 {
 551                         compatible = "allwinner,sun8i-a23-prcm";
 552                         reg = <0x01f01400 0x200>;
 553
 554                         ar100: ar100_clk {
 555                                 compatible = "fixed-factor-clock";
 556                                 #clock-cells = <0>;
 557                                 clock-div = <1>;
 558                                 clock-mult = <1>;
 559                                 clocks = <&osc24M>;
 560                                 clock-output-names = "ar100";
 561                         };
 562
 563                         ahb0: ahb0_clk {
 564                                 compatible = "fixed-factor-clock";
 565                                 #clock-cells = <0>;
 566                                 clock-div = <1>;
 567                                 clock-mult = <1>;
 568                                 clocks = <&ar100>;
 569                                 clock-output-names = "ahb0";
 570                         };
 571
 572                         apb0: apb0_clk {
 573                                 compatible = "allwinner,sun8i-a23-apb0-clk";
 574                                 #clock-cells = <0>;
 575                                 clocks = <&ahb0>;
 576                                 clock-output-names = "apb0";
 577                         };
 578
 579                         apb0_gates: apb0_gates_clk {
 580                                 compatible = "allwinner,sun8i-a23-apb0-gates-clk";
 581                                 #clock-cells = <1>;
 582                                 clocks = <&apb0>;
 583                                 clock-output-names = "apb0_pio", "apb0_timer",
 584                                                 "apb0_rsb", "apb0_uart",
 585                                                 "apb0_i2c";
 586                         };
 587
 588                         apb0_rst: apb0_rst {
 589                                 compatible = "allwinner,sun6i-a31-clock-reset";
 590                                 #reset-cells = <1>;
 591                         };
 592                 };
 593
 594                 cpucfg@01f01c00 {
 595                         compatible = "allwinner,sun8i-a23-cpuconfig";
 596                         reg = <0x01f01c00 0x300>;
 597                 };
 598
 599                 r_uart: serial@01f02800 {
 600                         compatible = "snps,dw-apb-uart";
 601                         reg = <0x01f02800 0x400>;
 602                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 603                         reg-shift = <2>;
 604                         reg-io-width = <4>;
 605                         clocks = <&apb0_gates 4>;
 606                         resets = <&apb0_rst 4>;
 607                         status = "disabled";
 608                 };
 609
 610                 r_pio: pinctrl@01f02c00 {
 611                         compatible = "allwinner,sun8i-a23-r-pinctrl";
 612                         reg = <0x01f02c00 0x400>;
 613                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 614                         clocks = <&apb0_gates 0>;
 615                         resets = <&apb0_rst 0>;
 616                         gpio-controller;
 617                         interrupt-controller;
 618                         #address-cells = <1>;
 619                         #size-cells = <0>;
 620                         #gpio-cells = <3>;
 621
 622                         r_uart_pins_a: r_uart@0 {
 623                                 allwinner,pins = "PL2", "PL3";
 624                                 allwinner,function = "s_uart";
 625                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 626                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 627                         };
 628                 };
 629         };
 630 };