1 #include <dt-bindings/clock/tegra114-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include "skeleton.dtsi"
9 compatible = "nvidia,tegra114";
10 interrupt-parent = <&gic>;
20 compatible = "nvidia,tegra114-host1x", "simple-bus";
21 reg = <0x50000000 0x00028000>;
22 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
23 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
24 clocks = <&tegra_car TEGRA114_CLK_HOST1X>;
25 resets = <&tegra_car 28>;
26 reset-names = "host1x";
31 ranges = <0x54000000 0x54000000 0x01000000>;
34 compatible = "nvidia,tegra114-gr2d", "nvidia,tegra20-gr2d";
35 reg = <0x54140000 0x00040000>;
36 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
37 clocks = <&tegra_car TEGRA114_CLK_GR2D>;
38 resets = <&tegra_car 21>;
43 compatible = "nvidia,tegra114-gr3d", "nvidia,tegra20-gr3d";
44 reg = <0x54180000 0x00040000>;
45 clocks = <&tegra_car TEGRA114_CLK_GR3D>;
46 resets = <&tegra_car 24>;
51 compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
52 reg = <0x54200000 0x00040000>;
53 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
54 clocks = <&tegra_car TEGRA114_CLK_DISP1>,
55 <&tegra_car TEGRA114_CLK_PLL_P>;
56 clock-names = "dc", "parent";
57 resets = <&tegra_car 27>;
68 compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
69 reg = <0x54240000 0x00040000>;
70 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
71 clocks = <&tegra_car TEGRA114_CLK_DISP2>,
72 <&tegra_car TEGRA114_CLK_PLL_P>;
73 clock-names = "dc", "parent";
74 resets = <&tegra_car 26>;
85 compatible = "nvidia,tegra114-hdmi";
86 reg = <0x54280000 0x00040000>;
87 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
88 clocks = <&tegra_car TEGRA114_CLK_HDMI>,
89 <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>;
90 clock-names = "hdmi", "parent";
91 resets = <&tegra_car 51>;
97 compatible = "nvidia,tegra114-dsi";
98 reg = <0x54300000 0x00040000>;
99 clocks = <&tegra_car TEGRA114_CLK_DSIA>,
100 <&tegra_car TEGRA114_CLK_DSIALP>,
101 <&tegra_car TEGRA114_CLK_PLL_D_OUT0>;
102 clock-names = "dsi", "lp", "parent";
103 resets = <&tegra_car 48>;
105 nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
108 #address-cells = <1>;
113 compatible = "nvidia,tegra114-dsi";
114 reg = <0x54400000 0x00040000>;
115 clocks = <&tegra_car TEGRA114_CLK_DSIB>,
116 <&tegra_car TEGRA114_CLK_DSIBLP>,
117 <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>;
118 clock-names = "dsi", "lp", "parent";
119 resets = <&tegra_car 82>;
121 nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */
124 #address-cells = <1>;
129 gic: interrupt-controller@50041000 {
130 compatible = "arm,cortex-a15-gic";
131 #interrupt-cells = <3>;
132 interrupt-controller;
133 reg = <0x50041000 0x1000>,
137 interrupts = <GIC_PPI 9
138 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
142 compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
143 reg = <0x60005000 0x400>;
144 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
145 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
146 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
147 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
150 clocks = <&tegra_car TEGRA114_CLK_TIMER>;
153 tegra_car: clock@60006000 {
154 compatible = "nvidia,tegra114-car";
155 reg = <0x60006000 0x1000>;
160 flow-controller@60007000 {
161 compatible = "nvidia,tegra114-flowctrl";
162 reg = <0x60007000 0x1000>;
165 apbdma: dma@6000a000 {
166 compatible = "nvidia,tegra114-apbdma";
167 reg = <0x6000a000 0x1400>;
168 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
169 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
170 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
171 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
173 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
174 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
175 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
176 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
177 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
178 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
180 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
181 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
182 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
184 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
185 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
186 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
187 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
188 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
189 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
190 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
191 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
192 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
193 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
194 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
196 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
200 clocks = <&tegra_car TEGRA114_CLK_APBDMA>;
201 resets = <&tegra_car 34>;
207 compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
208 reg = <0x6000c004 0x14c>;
211 gpio: gpio@6000d000 {
212 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
213 reg = <0x6000d000 0x1000>;
214 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
220 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
221 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
224 #interrupt-cells = <2>;
225 interrupt-controller;
229 compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc";
230 reg = <0x70000800 0x64 /* Chip revision */
231 0x70000008 0x04>; /* Strapping options */
234 pinmux: pinmux@70000868 {
235 compatible = "nvidia,tegra114-pinmux";
236 reg = <0x70000868 0x148 /* Pad control registers */
237 0x70003000 0x40c>; /* Mux registers */
241 * There are two serial driver i.e. 8250 based simple serial
242 * driver and APB DMA based serial driver for higher baudrate
243 * and performace. To enable the 8250 based driver, the compatible
244 * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable
245 * the APB DMA based serial driver, the comptible is
246 * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart".
248 uarta: serial@70006000 {
249 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
250 reg = <0x70006000 0x40>;
252 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&tegra_car TEGRA114_CLK_UARTA>;
254 resets = <&tegra_car 6>;
255 reset-names = "serial";
256 dmas = <&apbdma 8>, <&apbdma 8>;
257 dma-names = "rx", "tx";
261 uartb: serial@70006040 {
262 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
263 reg = <0x70006040 0x40>;
265 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
266 clocks = <&tegra_car TEGRA114_CLK_UARTB>;
267 resets = <&tegra_car 7>;
268 reset-names = "serial";
269 dmas = <&apbdma 9>, <&apbdma 9>;
270 dma-names = "rx", "tx";
274 uartc: serial@70006200 {
275 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
276 reg = <0x70006200 0x100>;
278 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&tegra_car TEGRA114_CLK_UARTC>;
280 resets = <&tegra_car 55>;
281 reset-names = "serial";
282 dmas = <&apbdma 10>, <&apbdma 10>;
283 dma-names = "rx", "tx";
287 uartd: serial@70006300 {
288 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
289 reg = <0x70006300 0x100>;
291 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
292 clocks = <&tegra_car TEGRA114_CLK_UARTD>;
293 resets = <&tegra_car 65>;
294 reset-names = "serial";
295 dmas = <&apbdma 19>, <&apbdma 19>;
296 dma-names = "rx", "tx";
301 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
302 reg = <0x7000a000 0x100>;
304 clocks = <&tegra_car TEGRA114_CLK_PWM>;
305 resets = <&tegra_car 17>;
311 compatible = "nvidia,tegra114-i2c";
312 reg = <0x7000c000 0x100>;
313 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
314 #address-cells = <1>;
316 clocks = <&tegra_car TEGRA114_CLK_I2C1>;
317 clock-names = "div-clk";
318 resets = <&tegra_car 12>;
320 dmas = <&apbdma 21>, <&apbdma 21>;
321 dma-names = "rx", "tx";
326 compatible = "nvidia,tegra114-i2c";
327 reg = <0x7000c400 0x100>;
328 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
329 #address-cells = <1>;
331 clocks = <&tegra_car TEGRA114_CLK_I2C2>;
332 clock-names = "div-clk";
333 resets = <&tegra_car 54>;
335 dmas = <&apbdma 22>, <&apbdma 22>;
336 dma-names = "rx", "tx";
341 compatible = "nvidia,tegra114-i2c";
342 reg = <0x7000c500 0x100>;
343 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
344 #address-cells = <1>;
346 clocks = <&tegra_car TEGRA114_CLK_I2C3>;
347 clock-names = "div-clk";
348 resets = <&tegra_car 67>;
350 dmas = <&apbdma 23>, <&apbdma 23>;
351 dma-names = "rx", "tx";
356 compatible = "nvidia,tegra114-i2c";
357 reg = <0x7000c700 0x100>;
358 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
359 #address-cells = <1>;
361 clocks = <&tegra_car TEGRA114_CLK_I2C4>;
362 clock-names = "div-clk";
363 resets = <&tegra_car 103>;
365 dmas = <&apbdma 26>, <&apbdma 26>;
366 dma-names = "rx", "tx";
371 compatible = "nvidia,tegra114-i2c";
372 reg = <0x7000d000 0x100>;
373 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
374 #address-cells = <1>;
376 clocks = <&tegra_car TEGRA114_CLK_I2C5>;
377 clock-names = "div-clk";
378 resets = <&tegra_car 47>;
380 dmas = <&apbdma 24>, <&apbdma 24>;
381 dma-names = "rx", "tx";
386 compatible = "nvidia,tegra114-spi";
387 reg = <0x7000d400 0x200>;
388 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
389 #address-cells = <1>;
391 clocks = <&tegra_car TEGRA114_CLK_SBC1>;
393 resets = <&tegra_car 41>;
395 dmas = <&apbdma 15>, <&apbdma 15>;
396 dma-names = "rx", "tx";
401 compatible = "nvidia,tegra114-spi";
402 reg = <0x7000d600 0x200>;
403 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
404 #address-cells = <1>;
406 clocks = <&tegra_car TEGRA114_CLK_SBC2>;
408 resets = <&tegra_car 44>;
410 dmas = <&apbdma 16>, <&apbdma 16>;
411 dma-names = "rx", "tx";
416 compatible = "nvidia,tegra114-spi";
417 reg = <0x7000d800 0x200>;
418 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
419 #address-cells = <1>;
421 clocks = <&tegra_car TEGRA114_CLK_SBC3>;
423 resets = <&tegra_car 46>;
425 dmas = <&apbdma 17>, <&apbdma 17>;
426 dma-names = "rx", "tx";
431 compatible = "nvidia,tegra114-spi";
432 reg = <0x7000da00 0x200>;
433 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
434 #address-cells = <1>;
436 clocks = <&tegra_car TEGRA114_CLK_SBC4>;
438 resets = <&tegra_car 68>;
440 dmas = <&apbdma 18>, <&apbdma 18>;
441 dma-names = "rx", "tx";
446 compatible = "nvidia,tegra114-spi";
447 reg = <0x7000dc00 0x200>;
448 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
449 #address-cells = <1>;
451 clocks = <&tegra_car TEGRA114_CLK_SBC5>;
453 resets = <&tegra_car 104>;
455 dmas = <&apbdma 27>, <&apbdma 27>;
456 dma-names = "rx", "tx";
461 compatible = "nvidia,tegra114-spi";
462 reg = <0x7000de00 0x200>;
463 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
464 #address-cells = <1>;
466 clocks = <&tegra_car TEGRA114_CLK_SBC6>;
468 resets = <&tegra_car 105>;
470 dmas = <&apbdma 28>, <&apbdma 28>;
471 dma-names = "rx", "tx";
476 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
477 reg = <0x7000e000 0x100>;
478 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
479 clocks = <&tegra_car TEGRA114_CLK_RTC>;
483 compatible = "nvidia,tegra114-kbc";
484 reg = <0x7000e200 0x100>;
485 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
486 clocks = <&tegra_car TEGRA114_CLK_KBC>;
487 resets = <&tegra_car 36>;
493 compatible = "nvidia,tegra114-pmc";
494 reg = <0x7000e400 0x400>;
495 clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>;
496 clock-names = "pclk", "clk32k_in";
500 compatible = "nvidia,tegra114-efuse";
501 reg = <0x7000f800 0x400>;
502 clocks = <&tegra_car TEGRA114_CLK_FUSE>;
503 clock-names = "fuse";
504 resets = <&tegra_car 39>;
505 reset-names = "fuse";
509 compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
510 reg = <0x70019010 0x02c
514 dma-window = <0 0x40000000>;
515 nvidia,swgroups = <0x18659fe>;
520 compatible = "nvidia,tegra114-ahub";
521 reg = <0x70080000 0x200>,
524 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
525 clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>,
526 <&tegra_car TEGRA114_CLK_APBIF>;
527 clock-names = "d_audio", "apbif";
528 resets = <&tegra_car 106>, /* d_audio */
529 <&tegra_car 107>, /* apbif */
530 <&tegra_car 30>, /* i2s0 */
531 <&tegra_car 11>, /* i2s1 */
532 <&tegra_car 18>, /* i2s2 */
533 <&tegra_car 101>, /* i2s3 */
534 <&tegra_car 102>, /* i2s4 */
535 <&tegra_car 108>, /* dam0 */
536 <&tegra_car 109>, /* dam1 */
537 <&tegra_car 110>, /* dam2 */
538 <&tegra_car 10>, /* spdif */
539 <&tegra_car 153>, /* amx */
540 <&tegra_car 154>; /* adx */
541 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
542 "i2s3", "i2s4", "dam0", "dam1", "dam2",
543 "spdif", "amx", "adx";
544 dmas = <&apbdma 1>, <&apbdma 1>,
545 <&apbdma 2>, <&apbdma 2>,
546 <&apbdma 3>, <&apbdma 3>,
547 <&apbdma 4>, <&apbdma 4>,
548 <&apbdma 6>, <&apbdma 6>,
549 <&apbdma 7>, <&apbdma 7>,
550 <&apbdma 12>, <&apbdma 12>,
551 <&apbdma 13>, <&apbdma 13>,
552 <&apbdma 14>, <&apbdma 14>,
553 <&apbdma 29>, <&apbdma 29>;
554 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
555 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
556 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
559 #address-cells = <1>;
562 tegra_i2s0: i2s@70080300 {
563 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
564 reg = <0x70080300 0x100>;
565 nvidia,ahub-cif-ids = <4 4>;
566 clocks = <&tegra_car TEGRA114_CLK_I2S0>;
567 resets = <&tegra_car 30>;
572 tegra_i2s1: i2s@70080400 {
573 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
574 reg = <0x70080400 0x100>;
575 nvidia,ahub-cif-ids = <5 5>;
576 clocks = <&tegra_car TEGRA114_CLK_I2S1>;
577 resets = <&tegra_car 11>;
582 tegra_i2s2: i2s@70080500 {
583 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
584 reg = <0x70080500 0x100>;
585 nvidia,ahub-cif-ids = <6 6>;
586 clocks = <&tegra_car TEGRA114_CLK_I2S2>;
587 resets = <&tegra_car 18>;
592 tegra_i2s3: i2s@70080600 {
593 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
594 reg = <0x70080600 0x100>;
595 nvidia,ahub-cif-ids = <7 7>;
596 clocks = <&tegra_car TEGRA114_CLK_I2S3>;
597 resets = <&tegra_car 101>;
602 tegra_i2s4: i2s@70080700 {
603 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
604 reg = <0x70080700 0x100>;
605 nvidia,ahub-cif-ids = <8 8>;
606 clocks = <&tegra_car TEGRA114_CLK_I2S4>;
607 resets = <&tegra_car 102>;
613 mipi: mipi@700e3000 {
614 compatible = "nvidia,tegra114-mipi";
615 reg = <0x700e3000 0x100>;
616 clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>;
617 #nvidia,mipi-calibrate-cells = <1>;
621 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
622 reg = <0x78000000 0x200>;
623 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
624 clocks = <&tegra_car TEGRA114_CLK_SDMMC1>;
625 resets = <&tegra_car 14>;
626 reset-names = "sdhci";
631 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
632 reg = <0x78000200 0x200>;
633 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
634 clocks = <&tegra_car TEGRA114_CLK_SDMMC2>;
635 resets = <&tegra_car 9>;
636 reset-names = "sdhci";
641 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
642 reg = <0x78000400 0x200>;
643 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
644 clocks = <&tegra_car TEGRA114_CLK_SDMMC3>;
645 resets = <&tegra_car 69>;
646 reset-names = "sdhci";
651 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
652 reg = <0x78000600 0x200>;
653 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
654 clocks = <&tegra_car TEGRA114_CLK_SDMMC4>;
655 resets = <&tegra_car 15>;
656 reset-names = "sdhci";
661 compatible = "nvidia,tegra30-ehci", "usb-ehci";
662 reg = <0x7d000000 0x4000>;
663 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
665 clocks = <&tegra_car TEGRA114_CLK_USBD>;
666 resets = <&tegra_car 22>;
668 nvidia,phy = <&phy1>;
672 phy1: usb-phy@7d000000 {
673 compatible = "nvidia,tegra30-usb-phy";
674 reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
676 clocks = <&tegra_car TEGRA114_CLK_USBD>,
677 <&tegra_car TEGRA114_CLK_PLL_U>,
678 <&tegra_car TEGRA114_CLK_USBD>;
679 clock-names = "reg", "pll_u", "utmi-pads";
680 resets = <&tegra_car 22>, <&tegra_car 22>;
681 reset-names = "usb", "utmi-pads";
682 nvidia,hssync-start-delay = <0>;
683 nvidia,idle-wait-delay = <17>;
684 nvidia,elastic-limit = <16>;
685 nvidia,term-range-adj = <6>;
686 nvidia,xcvr-setup = <9>;
687 nvidia,xcvr-lsfslew = <0>;
688 nvidia,xcvr-lsrslew = <3>;
689 nvidia,hssquelch-level = <2>;
690 nvidia,hsdiscon-level = <5>;
691 nvidia,xcvr-hsslew = <12>;
692 nvidia,has-utmi-pad-registers;
697 compatible = "nvidia,tegra30-ehci", "usb-ehci";
698 reg = <0x7d008000 0x4000>;
699 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
701 clocks = <&tegra_car TEGRA114_CLK_USB3>;
702 resets = <&tegra_car 59>;
704 nvidia,phy = <&phy3>;
708 phy3: usb-phy@7d008000 {
709 compatible = "nvidia,tegra30-usb-phy";
710 reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
712 clocks = <&tegra_car TEGRA114_CLK_USB3>,
713 <&tegra_car TEGRA114_CLK_PLL_U>,
714 <&tegra_car TEGRA114_CLK_USBD>;
715 clock-names = "reg", "pll_u", "utmi-pads";
716 resets = <&tegra_car 59>, <&tegra_car 22>;
717 reset-names = "usb", "utmi-pads";
718 nvidia,hssync-start-delay = <0>;
719 nvidia,idle-wait-delay = <17>;
720 nvidia,elastic-limit = <16>;
721 nvidia,term-range-adj = <6>;
722 nvidia,xcvr-setup = <9>;
723 nvidia,xcvr-lsfslew = <0>;
724 nvidia,xcvr-lsrslew = <3>;
725 nvidia,hssquelch-level = <2>;
726 nvidia,hsdiscon-level = <5>;
727 nvidia,xcvr-hsslew = <12>;
732 #address-cells = <1>;
737 compatible = "arm,cortex-a15";
743 compatible = "arm,cortex-a15";
749 compatible = "arm,cortex-a15";
755 compatible = "arm,cortex-a15";
761 compatible = "arm,armv7-timer";
764 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
766 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
768 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
770 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;