1 #include <dt-bindings/clock/tegra114-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include "skeleton.dtsi"
9 compatible = "nvidia,tegra114";
10 interrupt-parent = <&gic>;
20 compatible = "nvidia,tegra114-host1x", "simple-bus";
21 reg = <0x50000000 0x00028000>;
22 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
23 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
24 clocks = <&tegra_car TEGRA114_CLK_HOST1X>;
25 resets = <&tegra_car 28>;
26 reset-names = "host1x";
31 ranges = <0x54000000 0x54000000 0x01000000>;
34 compatible = "nvidia,tegra114-gr2d", "nvidia,tegra20-gr2d";
35 reg = <0x54140000 0x00040000>;
36 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
37 clocks = <&tegra_car TEGRA114_CLK_GR2D>;
38 resets = <&tegra_car 21>;
43 compatible = "nvidia,tegra114-gr3d", "nvidia,tegra20-gr3d";
44 reg = <0x54180000 0x00040000>;
45 clocks = <&tegra_car TEGRA114_CLK_GR3D>;
46 resets = <&tegra_car 24>;
51 compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
52 reg = <0x54200000 0x00040000>;
53 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
54 clocks = <&tegra_car TEGRA114_CLK_DISP1>,
55 <&tegra_car TEGRA114_CLK_PLL_P>;
56 clock-names = "dc", "parent";
57 resets = <&tegra_car 27>;
68 compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
69 reg = <0x54240000 0x00040000>;
70 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
71 clocks = <&tegra_car TEGRA114_CLK_DISP2>,
72 <&tegra_car TEGRA114_CLK_PLL_P>;
73 clock-names = "dc", "parent";
74 resets = <&tegra_car 26>;
85 compatible = "nvidia,tegra114-hdmi";
86 reg = <0x54280000 0x00040000>;
87 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
88 clocks = <&tegra_car TEGRA114_CLK_HDMI>,
89 <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>;
90 clock-names = "hdmi", "parent";
91 resets = <&tegra_car 51>;
97 compatible = "nvidia,tegra114-dsi";
98 reg = <0x54300000 0x00040000>;
99 clocks = <&tegra_car TEGRA114_CLK_DSIA>,
100 <&tegra_car TEGRA114_CLK_DSIALP>,
101 <&tegra_car TEGRA114_CLK_PLL_D_OUT0>;
102 clock-names = "dsi", "lp", "parent";
103 resets = <&tegra_car 48>;
105 nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
108 #address-cells = <1>;
113 compatible = "nvidia,tegra114-dsi";
114 reg = <0x54400000 0x00040000>;
115 clocks = <&tegra_car TEGRA114_CLK_DSIB>,
116 <&tegra_car TEGRA114_CLK_DSIBLP>,
117 <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>;
118 clock-names = "dsi", "lp", "parent";
119 resets = <&tegra_car 82>;
121 nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */
124 #address-cells = <1>;
129 gic: interrupt-controller@50041000 {
130 compatible = "arm,cortex-a15-gic";
131 #interrupt-cells = <3>;
132 interrupt-controller;
133 reg = <0x50041000 0x1000>,
137 interrupts = <GIC_PPI 9
138 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
142 compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
143 reg = <0x60005000 0x400>;
144 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
145 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
146 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
147 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
150 clocks = <&tegra_car TEGRA114_CLK_TIMER>;
153 tegra_car: clock@60006000 {
154 compatible = "nvidia,tegra114-car";
155 reg = <0x60006000 0x1000>;
160 apbdma: dma@6000a000 {
161 compatible = "nvidia,tegra114-apbdma";
162 reg = <0x6000a000 0x1400>;
163 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
164 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
165 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
166 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
167 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
168 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
169 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
170 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
171 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
173 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
174 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
175 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
176 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
177 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
178 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
180 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
181 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
182 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
184 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
185 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
186 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
187 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
188 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
189 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
190 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
191 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
192 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
193 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
194 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
195 clocks = <&tegra_car TEGRA114_CLK_APBDMA>;
196 resets = <&tegra_car 34>;
202 compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
203 reg = <0x6000c004 0x14c>;
206 gpio: gpio@6000d000 {
207 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
208 reg = <0x6000d000 0x1000>;
209 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
210 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
219 #interrupt-cells = <2>;
220 interrupt-controller;
223 pinmux: pinmux@70000868 {
224 compatible = "nvidia,tegra114-pinmux";
225 reg = <0x70000868 0x148 /* Pad control registers */
226 0x70003000 0x40c>; /* Mux registers */
230 * There are two serial driver i.e. 8250 based simple serial
231 * driver and APB DMA based serial driver for higher baudrate
232 * and performace. To enable the 8250 based driver, the compatible
233 * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable
234 * the APB DMA based serial driver, the comptible is
235 * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart".
237 uarta: serial@70006000 {
238 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
239 reg = <0x70006000 0x40>;
241 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
242 clocks = <&tegra_car TEGRA114_CLK_UARTA>;
243 resets = <&tegra_car 6>;
244 reset-names = "serial";
245 dmas = <&apbdma 8>, <&apbdma 8>;
246 dma-names = "rx", "tx";
250 uartb: serial@70006040 {
251 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
252 reg = <0x70006040 0x40>;
254 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
255 clocks = <&tegra_car TEGRA114_CLK_UARTB>;
256 resets = <&tegra_car 7>;
257 reset-names = "serial";
258 dmas = <&apbdma 9>, <&apbdma 9>;
259 dma-names = "rx", "tx";
263 uartc: serial@70006200 {
264 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
265 reg = <0x70006200 0x100>;
267 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
268 clocks = <&tegra_car TEGRA114_CLK_UARTC>;
269 resets = <&tegra_car 55>;
270 reset-names = "serial";
271 dmas = <&apbdma 10>, <&apbdma 10>;
272 dma-names = "rx", "tx";
276 uartd: serial@70006300 {
277 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
278 reg = <0x70006300 0x100>;
280 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
281 clocks = <&tegra_car TEGRA114_CLK_UARTD>;
282 resets = <&tegra_car 65>;
283 reset-names = "serial";
284 dmas = <&apbdma 19>, <&apbdma 19>;
285 dma-names = "rx", "tx";
290 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
291 reg = <0x7000a000 0x100>;
293 clocks = <&tegra_car TEGRA114_CLK_PWM>;
294 resets = <&tegra_car 17>;
300 compatible = "nvidia,tegra114-i2c";
301 reg = <0x7000c000 0x100>;
302 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
303 #address-cells = <1>;
305 clocks = <&tegra_car TEGRA114_CLK_I2C1>;
306 clock-names = "div-clk";
307 resets = <&tegra_car 12>;
309 dmas = <&apbdma 21>, <&apbdma 21>;
310 dma-names = "rx", "tx";
315 compatible = "nvidia,tegra114-i2c";
316 reg = <0x7000c400 0x100>;
317 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
318 #address-cells = <1>;
320 clocks = <&tegra_car TEGRA114_CLK_I2C2>;
321 clock-names = "div-clk";
322 resets = <&tegra_car 54>;
324 dmas = <&apbdma 22>, <&apbdma 22>;
325 dma-names = "rx", "tx";
330 compatible = "nvidia,tegra114-i2c";
331 reg = <0x7000c500 0x100>;
332 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
333 #address-cells = <1>;
335 clocks = <&tegra_car TEGRA114_CLK_I2C3>;
336 clock-names = "div-clk";
337 resets = <&tegra_car 67>;
339 dmas = <&apbdma 23>, <&apbdma 23>;
340 dma-names = "rx", "tx";
345 compatible = "nvidia,tegra114-i2c";
346 reg = <0x7000c700 0x100>;
347 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
348 #address-cells = <1>;
350 clocks = <&tegra_car TEGRA114_CLK_I2C4>;
351 clock-names = "div-clk";
352 resets = <&tegra_car 103>;
354 dmas = <&apbdma 26>, <&apbdma 26>;
355 dma-names = "rx", "tx";
360 compatible = "nvidia,tegra114-i2c";
361 reg = <0x7000d000 0x100>;
362 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
363 #address-cells = <1>;
365 clocks = <&tegra_car TEGRA114_CLK_I2C5>;
366 clock-names = "div-clk";
367 resets = <&tegra_car 47>;
369 dmas = <&apbdma 24>, <&apbdma 24>;
370 dma-names = "rx", "tx";
375 compatible = "nvidia,tegra114-spi";
376 reg = <0x7000d400 0x200>;
377 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
378 #address-cells = <1>;
380 clocks = <&tegra_car TEGRA114_CLK_SBC1>;
382 resets = <&tegra_car 41>;
384 dmas = <&apbdma 15>, <&apbdma 15>;
385 dma-names = "rx", "tx";
390 compatible = "nvidia,tegra114-spi";
391 reg = <0x7000d600 0x200>;
392 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
393 #address-cells = <1>;
395 clocks = <&tegra_car TEGRA114_CLK_SBC2>;
397 resets = <&tegra_car 44>;
399 dmas = <&apbdma 16>, <&apbdma 16>;
400 dma-names = "rx", "tx";
405 compatible = "nvidia,tegra114-spi";
406 reg = <0x7000d800 0x200>;
407 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
408 #address-cells = <1>;
410 clocks = <&tegra_car TEGRA114_CLK_SBC3>;
412 resets = <&tegra_car 46>;
414 dmas = <&apbdma 17>, <&apbdma 17>;
415 dma-names = "rx", "tx";
420 compatible = "nvidia,tegra114-spi";
421 reg = <0x7000da00 0x200>;
422 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
423 #address-cells = <1>;
425 clocks = <&tegra_car TEGRA114_CLK_SBC4>;
427 resets = <&tegra_car 68>;
429 dmas = <&apbdma 18>, <&apbdma 18>;
430 dma-names = "rx", "tx";
435 compatible = "nvidia,tegra114-spi";
436 reg = <0x7000dc00 0x200>;
437 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
438 #address-cells = <1>;
440 clocks = <&tegra_car TEGRA114_CLK_SBC5>;
442 resets = <&tegra_car 104>;
444 dmas = <&apbdma 27>, <&apbdma 27>;
445 dma-names = "rx", "tx";
450 compatible = "nvidia,tegra114-spi";
451 reg = <0x7000de00 0x200>;
452 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
453 #address-cells = <1>;
455 clocks = <&tegra_car TEGRA114_CLK_SBC6>;
457 resets = <&tegra_car 105>;
459 dmas = <&apbdma 28>, <&apbdma 28>;
460 dma-names = "rx", "tx";
465 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
466 reg = <0x7000e000 0x100>;
467 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
468 clocks = <&tegra_car TEGRA114_CLK_RTC>;
472 compatible = "nvidia,tegra114-kbc";
473 reg = <0x7000e200 0x100>;
474 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
475 clocks = <&tegra_car TEGRA114_CLK_KBC>;
476 resets = <&tegra_car 36>;
482 compatible = "nvidia,tegra114-pmc";
483 reg = <0x7000e400 0x400>;
484 clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>;
485 clock-names = "pclk", "clk32k_in";
489 compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
490 reg = <0x70019010 0x02c
494 dma-window = <0 0x40000000>;
495 nvidia,swgroups = <0x18659fe>;
500 compatible = "nvidia,tegra114-ahub";
501 reg = <0x70080000 0x200>,
504 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
505 clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>,
506 <&tegra_car TEGRA114_CLK_APBIF>;
507 clock-names = "d_audio", "apbif";
508 resets = <&tegra_car 106>, /* d_audio */
509 <&tegra_car 107>, /* apbif */
510 <&tegra_car 30>, /* i2s0 */
511 <&tegra_car 11>, /* i2s1 */
512 <&tegra_car 18>, /* i2s2 */
513 <&tegra_car 101>, /* i2s3 */
514 <&tegra_car 102>, /* i2s4 */
515 <&tegra_car 108>, /* dam0 */
516 <&tegra_car 109>, /* dam1 */
517 <&tegra_car 110>, /* dam2 */
518 <&tegra_car 10>, /* spdif */
519 <&tegra_car 153>, /* amx */
520 <&tegra_car 154>; /* adx */
521 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
522 "i2s3", "i2s4", "dam0", "dam1", "dam2",
523 "spdif", "amx", "adx";
524 dmas = <&apbdma 1>, <&apbdma 1>,
525 <&apbdma 2>, <&apbdma 2>,
526 <&apbdma 3>, <&apbdma 3>,
527 <&apbdma 4>, <&apbdma 4>,
528 <&apbdma 6>, <&apbdma 6>,
529 <&apbdma 7>, <&apbdma 7>,
530 <&apbdma 12>, <&apbdma 12>,
531 <&apbdma 13>, <&apbdma 13>,
532 <&apbdma 14>, <&apbdma 14>,
533 <&apbdma 29>, <&apbdma 29>;
534 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
535 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
536 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
539 #address-cells = <1>;
542 tegra_i2s0: i2s@70080300 {
543 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
544 reg = <0x70080300 0x100>;
545 nvidia,ahub-cif-ids = <4 4>;
546 clocks = <&tegra_car TEGRA114_CLK_I2S0>;
547 resets = <&tegra_car 30>;
552 tegra_i2s1: i2s@70080400 {
553 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
554 reg = <0x70080400 0x100>;
555 nvidia,ahub-cif-ids = <5 5>;
556 clocks = <&tegra_car TEGRA114_CLK_I2S1>;
557 resets = <&tegra_car 11>;
562 tegra_i2s2: i2s@70080500 {
563 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
564 reg = <0x70080500 0x100>;
565 nvidia,ahub-cif-ids = <6 6>;
566 clocks = <&tegra_car TEGRA114_CLK_I2S2>;
567 resets = <&tegra_car 18>;
572 tegra_i2s3: i2s@70080600 {
573 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
574 reg = <0x70080600 0x100>;
575 nvidia,ahub-cif-ids = <7 7>;
576 clocks = <&tegra_car TEGRA114_CLK_I2S3>;
577 resets = <&tegra_car 101>;
582 tegra_i2s4: i2s@70080700 {
583 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
584 reg = <0x70080700 0x100>;
585 nvidia,ahub-cif-ids = <8 8>;
586 clocks = <&tegra_car TEGRA114_CLK_I2S4>;
587 resets = <&tegra_car 102>;
593 mipi: mipi@700e3000 {
594 compatible = "nvidia,tegra114-mipi";
595 reg = <0x700e3000 0x100>;
596 clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>;
597 #nvidia,mipi-calibrate-cells = <1>;
601 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
602 reg = <0x78000000 0x200>;
603 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
604 clocks = <&tegra_car TEGRA114_CLK_SDMMC1>;
605 resets = <&tegra_car 14>;
606 reset-names = "sdhci";
611 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
612 reg = <0x78000200 0x200>;
613 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
614 clocks = <&tegra_car TEGRA114_CLK_SDMMC2>;
615 resets = <&tegra_car 9>;
616 reset-names = "sdhci";
621 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
622 reg = <0x78000400 0x200>;
623 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
624 clocks = <&tegra_car TEGRA114_CLK_SDMMC3>;
625 resets = <&tegra_car 69>;
626 reset-names = "sdhci";
631 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
632 reg = <0x78000600 0x200>;
633 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
634 clocks = <&tegra_car TEGRA114_CLK_SDMMC4>;
635 resets = <&tegra_car 15>;
636 reset-names = "sdhci";
641 compatible = "nvidia,tegra30-ehci", "usb-ehci";
642 reg = <0x7d000000 0x4000>;
643 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
645 clocks = <&tegra_car TEGRA114_CLK_USBD>;
646 resets = <&tegra_car 22>;
648 nvidia,phy = <&phy1>;
652 phy1: usb-phy@7d000000 {
653 compatible = "nvidia,tegra30-usb-phy";
654 reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
656 clocks = <&tegra_car TEGRA114_CLK_USBD>,
657 <&tegra_car TEGRA114_CLK_PLL_U>,
658 <&tegra_car TEGRA114_CLK_USBD>;
659 clock-names = "reg", "pll_u", "utmi-pads";
660 nvidia,hssync-start-delay = <0>;
661 nvidia,idle-wait-delay = <17>;
662 nvidia,elastic-limit = <16>;
663 nvidia,term-range-adj = <6>;
664 nvidia,xcvr-setup = <9>;
665 nvidia,xcvr-lsfslew = <0>;
666 nvidia,xcvr-lsrslew = <3>;
667 nvidia,hssquelch-level = <2>;
668 nvidia,hsdiscon-level = <5>;
669 nvidia,xcvr-hsslew = <12>;
674 compatible = "nvidia,tegra30-ehci", "usb-ehci";
675 reg = <0x7d008000 0x4000>;
676 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
678 clocks = <&tegra_car TEGRA114_CLK_USB3>;
679 resets = <&tegra_car 59>;
681 nvidia,phy = <&phy3>;
685 phy3: usb-phy@7d008000 {
686 compatible = "nvidia,tegra30-usb-phy";
687 reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
689 clocks = <&tegra_car TEGRA114_CLK_USB3>,
690 <&tegra_car TEGRA114_CLK_PLL_U>,
691 <&tegra_car TEGRA114_CLK_USBD>;
692 clock-names = "reg", "pll_u", "utmi-pads";
693 nvidia,hssync-start-delay = <0>;
694 nvidia,idle-wait-delay = <17>;
695 nvidia,elastic-limit = <16>;
696 nvidia,term-range-adj = <6>;
697 nvidia,xcvr-setup = <9>;
698 nvidia,xcvr-lsfslew = <0>;
699 nvidia,xcvr-lsrslew = <3>;
700 nvidia,hssquelch-level = <2>;
701 nvidia,hsdiscon-level = <5>;
702 nvidia,xcvr-hsslew = <12>;
707 #address-cells = <1>;
712 compatible = "arm,cortex-a15";
718 compatible = "arm,cortex-a15";
724 compatible = "arm,cortex-a15";
730 compatible = "arm,cortex-a15";
736 compatible = "arm,armv7-timer";
739 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
741 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
743 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
745 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;