1 #include <dt-bindings/clock/tegra124-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
4 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include "skeleton.dtsi"
10 compatible = "nvidia,tegra124";
11 interrupt-parent = <&gic>;
16 compatible = "nvidia,tegra124-host1x", "simple-bus";
17 reg = <0x0 0x50000000 0x0 0x00034000>;
18 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
19 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
20 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
21 resets = <&tegra_car 28>;
22 reset-names = "host1x";
27 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
30 compatible = "nvidia,tegra124-dc";
31 reg = <0x0 0x54200000 0x0 0x00040000>;
32 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
33 clocks = <&tegra_car TEGRA124_CLK_DISP1>,
34 <&tegra_car TEGRA124_CLK_PLL_P>;
35 clock-names = "dc", "parent";
36 resets = <&tegra_car 27>;
43 compatible = "nvidia,tegra124-dc";
44 reg = <0x0 0x54240000 0x0 0x00040000>;
45 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
46 clocks = <&tegra_car TEGRA124_CLK_DISP2>,
47 <&tegra_car TEGRA124_CLK_PLL_P>;
48 clock-names = "dc", "parent";
49 resets = <&tegra_car 26>;
56 compatible = "nvidia,tegra124-hdmi";
57 reg = <0x0 0x54280000 0x0 0x00040000>;
58 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
59 clocks = <&tegra_car TEGRA124_CLK_HDMI>,
60 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
61 clock-names = "hdmi", "parent";
62 resets = <&tegra_car 51>;
68 compatible = "nvidia,tegra124-sor";
69 reg = <0x0 0x54540000 0x0 0x00040000>;
70 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
71 clocks = <&tegra_car TEGRA124_CLK_SOR0>,
72 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
73 <&tegra_car TEGRA124_CLK_PLL_DP>,
74 <&tegra_car TEGRA124_CLK_CLK_M>;
75 clock-names = "sor", "parent", "dp", "safe";
76 resets = <&tegra_car 182>;
82 compatible = "nvidia,tegra124-dpaux";
83 reg = <0x0 0x545c0000 0x0 0x00040000>;
84 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
85 clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
86 <&tegra_car TEGRA124_CLK_PLL_DP>;
87 clock-names = "dpaux", "parent";
88 resets = <&tegra_car 181>;
89 reset-names = "dpaux";
94 gic: interrupt-controller@0,50041000 {
95 compatible = "arm,cortex-a15-gic";
96 #interrupt-cells = <3>;
98 reg = <0x0 0x50041000 0x0 0x1000>,
99 <0x0 0x50042000 0x0 0x1000>,
100 <0x0 0x50044000 0x0 0x2000>,
101 <0x0 0x50046000 0x0 0x2000>;
102 interrupts = <GIC_PPI 9
103 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
107 compatible = "nvidia,gk20a";
108 reg = <0x0 0x57000000 0x0 0x01000000>,
109 <0x0 0x58000000 0x0 0x01000000>;
110 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
111 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
112 interrupt-names = "stall", "nonstall";
113 clocks = <&tegra_car TEGRA124_CLK_GPU>,
114 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
115 clock-names = "gpu", "pwr";
116 resets = <&tegra_car 184>;
122 compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
123 reg = <0x0 0x60005000 0x0 0x400>;
124 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
125 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
126 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
127 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
128 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
129 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
130 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
133 tegra_car: clock@0,60006000 {
134 compatible = "nvidia,tegra124-car";
135 reg = <0x0 0x60006000 0x0 0x1000>;
140 gpio: gpio@0,6000d000 {
141 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
142 reg = <0x0 0x6000d000 0x0 0x1000>;
143 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
144 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
145 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
146 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
147 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
153 #interrupt-cells = <2>;
154 interrupt-controller;
157 apbdma: dma@0,60020000 {
158 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
159 reg = <0x0 0x60020000 0x0 0x1400>;
160 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
162 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
163 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
164 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
165 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
166 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
167 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
168 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
169 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
170 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
171 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
173 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
174 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
175 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
176 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
177 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
178 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
180 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
181 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
182 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
184 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
185 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
186 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
187 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
188 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
189 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
190 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
191 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
192 clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
193 resets = <&tegra_car 34>;
199 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
200 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
201 <0x0 0x7000E864 0x0 0x04>; /* Strapping options */
204 pinmux: pinmux@0,70000868 {
205 compatible = "nvidia,tegra124-pinmux";
206 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
207 <0x0 0x70003000 0x0 0x434>; /* Mux registers */
211 * There are two serial driver i.e. 8250 based simple serial
212 * driver and APB DMA based serial driver for higher baudrate
213 * and performace. To enable the 8250 based driver, the compatible
214 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
215 * the APB DMA based serial driver, the comptible is
216 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
219 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
220 reg = <0x0 0x70006000 0x0 0x40>;
222 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
223 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
224 resets = <&tegra_car 6>;
225 reset-names = "serial";
226 dmas = <&apbdma 8>, <&apbdma 8>;
227 dma-names = "rx", "tx";
232 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
233 reg = <0x0 0x70006040 0x0 0x40>;
235 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
236 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
237 resets = <&tegra_car 7>;
238 reset-names = "serial";
239 dmas = <&apbdma 9>, <&apbdma 9>;
240 dma-names = "rx", "tx";
245 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
246 reg = <0x0 0x70006200 0x0 0x40>;
248 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
249 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
250 resets = <&tegra_car 55>;
251 reset-names = "serial";
252 dmas = <&apbdma 10>, <&apbdma 10>;
253 dma-names = "rx", "tx";
258 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
259 reg = <0x0 0x70006300 0x0 0x40>;
261 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
262 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
263 resets = <&tegra_car 65>;
264 reset-names = "serial";
265 dmas = <&apbdma 19>, <&apbdma 19>;
266 dma-names = "rx", "tx";
271 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
272 reg = <0x0 0x7000a000 0x0 0x100>;
274 clocks = <&tegra_car TEGRA124_CLK_PWM>;
275 resets = <&tegra_car 17>;
281 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
282 reg = <0x0 0x7000c000 0x0 0x100>;
283 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
284 #address-cells = <1>;
286 clocks = <&tegra_car TEGRA124_CLK_I2C1>;
287 clock-names = "div-clk";
288 resets = <&tegra_car 12>;
290 dmas = <&apbdma 21>, <&apbdma 21>;
291 dma-names = "rx", "tx";
296 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
297 reg = <0x0 0x7000c400 0x0 0x100>;
298 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
299 #address-cells = <1>;
301 clocks = <&tegra_car TEGRA124_CLK_I2C2>;
302 clock-names = "div-clk";
303 resets = <&tegra_car 54>;
305 dmas = <&apbdma 22>, <&apbdma 22>;
306 dma-names = "rx", "tx";
311 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
312 reg = <0x0 0x7000c500 0x0 0x100>;
313 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
314 #address-cells = <1>;
316 clocks = <&tegra_car TEGRA124_CLK_I2C3>;
317 clock-names = "div-clk";
318 resets = <&tegra_car 67>;
320 dmas = <&apbdma 23>, <&apbdma 23>;
321 dma-names = "rx", "tx";
326 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
327 reg = <0x0 0x7000c700 0x0 0x100>;
328 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
329 #address-cells = <1>;
331 clocks = <&tegra_car TEGRA124_CLK_I2C4>;
332 clock-names = "div-clk";
333 resets = <&tegra_car 103>;
335 dmas = <&apbdma 26>, <&apbdma 26>;
336 dma-names = "rx", "tx";
341 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
342 reg = <0x0 0x7000d000 0x0 0x100>;
343 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
344 #address-cells = <1>;
346 clocks = <&tegra_car TEGRA124_CLK_I2C5>;
347 clock-names = "div-clk";
348 resets = <&tegra_car 47>;
350 dmas = <&apbdma 24>, <&apbdma 24>;
351 dma-names = "rx", "tx";
356 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
357 reg = <0x0 0x7000d100 0x0 0x100>;
358 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
359 #address-cells = <1>;
361 clocks = <&tegra_car TEGRA124_CLK_I2C6>;
362 clock-names = "div-clk";
363 resets = <&tegra_car 166>;
365 dmas = <&apbdma 30>, <&apbdma 30>;
366 dma-names = "rx", "tx";
371 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
372 reg = <0x0 0x7000d400 0x0 0x200>;
373 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
374 #address-cells = <1>;
376 clocks = <&tegra_car TEGRA124_CLK_SBC1>;
378 resets = <&tegra_car 41>;
380 dmas = <&apbdma 15>, <&apbdma 15>;
381 dma-names = "rx", "tx";
386 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
387 reg = <0x0 0x7000d600 0x0 0x200>;
388 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
389 #address-cells = <1>;
391 clocks = <&tegra_car TEGRA124_CLK_SBC2>;
393 resets = <&tegra_car 44>;
395 dmas = <&apbdma 16>, <&apbdma 16>;
396 dma-names = "rx", "tx";
401 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
402 reg = <0x0 0x7000d800 0x0 0x200>;
403 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
404 #address-cells = <1>;
406 clocks = <&tegra_car TEGRA124_CLK_SBC3>;
408 resets = <&tegra_car 46>;
410 dmas = <&apbdma 17>, <&apbdma 17>;
411 dma-names = "rx", "tx";
416 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
417 reg = <0x0 0x7000da00 0x0 0x200>;
418 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
419 #address-cells = <1>;
421 clocks = <&tegra_car TEGRA124_CLK_SBC4>;
423 resets = <&tegra_car 68>;
425 dmas = <&apbdma 18>, <&apbdma 18>;
426 dma-names = "rx", "tx";
431 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
432 reg = <0x0 0x7000dc00 0x0 0x200>;
433 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
434 #address-cells = <1>;
436 clocks = <&tegra_car TEGRA124_CLK_SBC5>;
438 resets = <&tegra_car 104>;
440 dmas = <&apbdma 27>, <&apbdma 27>;
441 dma-names = "rx", "tx";
446 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
447 reg = <0x0 0x7000de00 0x0 0x200>;
448 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
449 #address-cells = <1>;
451 clocks = <&tegra_car TEGRA124_CLK_SBC6>;
453 resets = <&tegra_car 105>;
455 dmas = <&apbdma 28>, <&apbdma 28>;
456 dma-names = "rx", "tx";
461 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
462 reg = <0x0 0x7000e000 0x0 0x100>;
463 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
464 clocks = <&tegra_car TEGRA124_CLK_RTC>;
468 compatible = "nvidia,tegra124-pmc";
469 reg = <0x0 0x7000e400 0x0 0x400>;
470 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
471 clock-names = "pclk", "clk32k_in";
475 compatible = "nvidia,tegra124-efuse";
476 reg = <0x0 0x7000f800 0x0 0x400>;
477 clocks = <&tegra_car TEGRA124_CLK_FUSE>;
478 clock-names = "fuse";
479 resets = <&tegra_car 39>;
480 reset-names = "fuse";
484 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda";
485 reg = <0x0 0x70030000 0x0 0x10000>;
486 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
487 clocks = <&tegra_car TEGRA124_CLK_HDA>,
488 <&tegra_car TEGRA124_CLK_HDA2HDMI>,
489 <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
490 clock-names = "hda", "hda2hdmi", "hdacodec_2x";
491 resets = <&tegra_car 125>, /* hda */
492 <&tegra_car 128>, /* hda2hdmi */
493 <&tegra_car 111>; /* hda2codec_2x */
494 reset-names = "hda", "hda2hdmi", "hdacodec_2x";
498 padctl: padctl@0,7009f000 {
499 compatible = "nvidia,tegra124-xusb-padctl";
500 reg = <0x0 0x7009f000 0x0 0x1000>;
501 resets = <&tegra_car 142>;
502 reset-names = "padctl";
508 compatible = "nvidia,tegra124-sdhci";
509 reg = <0x0 0x700b0000 0x0 0x200>;
510 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
511 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
512 resets = <&tegra_car 14>;
513 reset-names = "sdhci";
518 compatible = "nvidia,tegra124-sdhci";
519 reg = <0x0 0x700b0200 0x0 0x200>;
520 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
521 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
522 resets = <&tegra_car 9>;
523 reset-names = "sdhci";
528 compatible = "nvidia,tegra124-sdhci";
529 reg = <0x0 0x700b0400 0x0 0x200>;
530 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
531 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
532 resets = <&tegra_car 69>;
533 reset-names = "sdhci";
538 compatible = "nvidia,tegra124-sdhci";
539 reg = <0x0 0x700b0600 0x0 0x200>;
540 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
541 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
542 resets = <&tegra_car 15>;
543 reset-names = "sdhci";
548 compatible = "nvidia,tegra124-ahub";
549 reg = <0x0 0x70300000 0x0 0x200>,
550 <0x0 0x70300800 0x0 0x800>,
551 <0x0 0x70300200 0x0 0x600>;
552 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
553 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
554 <&tegra_car TEGRA124_CLK_APBIF>;
555 clock-names = "d_audio", "apbif";
556 resets = <&tegra_car 106>, /* d_audio */
557 <&tegra_car 107>, /* apbif */
558 <&tegra_car 30>, /* i2s0 */
559 <&tegra_car 11>, /* i2s1 */
560 <&tegra_car 18>, /* i2s2 */
561 <&tegra_car 101>, /* i2s3 */
562 <&tegra_car 102>, /* i2s4 */
563 <&tegra_car 108>, /* dam0 */
564 <&tegra_car 109>, /* dam1 */
565 <&tegra_car 110>, /* dam2 */
566 <&tegra_car 10>, /* spdif */
567 <&tegra_car 153>, /* amx */
568 <&tegra_car 185>, /* amx1 */
569 <&tegra_car 154>, /* adx */
570 <&tegra_car 180>, /* adx1 */
571 <&tegra_car 186>, /* afc0 */
572 <&tegra_car 187>, /* afc1 */
573 <&tegra_car 188>, /* afc2 */
574 <&tegra_car 189>, /* afc3 */
575 <&tegra_car 190>, /* afc4 */
576 <&tegra_car 191>; /* afc5 */
577 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
578 "i2s3", "i2s4", "dam0", "dam1", "dam2",
579 "spdif", "amx", "amx1", "adx", "adx1",
580 "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
581 dmas = <&apbdma 1>, <&apbdma 1>,
582 <&apbdma 2>, <&apbdma 2>,
583 <&apbdma 3>, <&apbdma 3>,
584 <&apbdma 4>, <&apbdma 4>,
585 <&apbdma 6>, <&apbdma 6>,
586 <&apbdma 7>, <&apbdma 7>,
587 <&apbdma 12>, <&apbdma 12>,
588 <&apbdma 13>, <&apbdma 13>,
589 <&apbdma 14>, <&apbdma 14>,
590 <&apbdma 29>, <&apbdma 29>;
591 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
592 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
593 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
596 #address-cells = <2>;
599 tegra_i2s0: i2s@0,70301000 {
600 compatible = "nvidia,tegra124-i2s";
601 reg = <0x0 0x70301000 0x0 0x100>;
602 nvidia,ahub-cif-ids = <4 4>;
603 clocks = <&tegra_car TEGRA124_CLK_I2S0>;
604 resets = <&tegra_car 30>;
609 tegra_i2s1: i2s@0,70301100 {
610 compatible = "nvidia,tegra124-i2s";
611 reg = <0x0 0x70301100 0x0 0x100>;
612 nvidia,ahub-cif-ids = <5 5>;
613 clocks = <&tegra_car TEGRA124_CLK_I2S1>;
614 resets = <&tegra_car 11>;
619 tegra_i2s2: i2s@0,70301200 {
620 compatible = "nvidia,tegra124-i2s";
621 reg = <0x0 0x70301200 0x0 0x100>;
622 nvidia,ahub-cif-ids = <6 6>;
623 clocks = <&tegra_car TEGRA124_CLK_I2S2>;
624 resets = <&tegra_car 18>;
629 tegra_i2s3: i2s@0,70301300 {
630 compatible = "nvidia,tegra124-i2s";
631 reg = <0x0 0x70301300 0x0 0x100>;
632 nvidia,ahub-cif-ids = <7 7>;
633 clocks = <&tegra_car TEGRA124_CLK_I2S3>;
634 resets = <&tegra_car 101>;
639 tegra_i2s4: i2s@0,70301400 {
640 compatible = "nvidia,tegra124-i2s";
641 reg = <0x0 0x70301400 0x0 0x100>;
642 nvidia,ahub-cif-ids = <8 8>;
643 clocks = <&tegra_car TEGRA124_CLK_I2S4>;
644 resets = <&tegra_car 102>;
651 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
652 reg = <0x0 0x7d000000 0x0 0x4000>;
653 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
655 clocks = <&tegra_car TEGRA124_CLK_USBD>;
656 resets = <&tegra_car 22>;
658 nvidia,phy = <&phy1>;
662 phy1: usb-phy@0,7d000000 {
663 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
664 reg = <0x0 0x7d000000 0x0 0x4000>,
665 <0x0 0x7d000000 0x0 0x4000>;
667 clocks = <&tegra_car TEGRA124_CLK_USBD>,
668 <&tegra_car TEGRA124_CLK_PLL_U>,
669 <&tegra_car TEGRA124_CLK_USBD>;
670 clock-names = "reg", "pll_u", "utmi-pads";
671 nvidia,hssync-start-delay = <0>;
672 nvidia,idle-wait-delay = <17>;
673 nvidia,elastic-limit = <16>;
674 nvidia,term-range-adj = <6>;
675 nvidia,xcvr-setup = <9>;
676 nvidia,xcvr-lsfslew = <0>;
677 nvidia,xcvr-lsrslew = <3>;
678 nvidia,hssquelch-level = <2>;
679 nvidia,hsdiscon-level = <5>;
680 nvidia,xcvr-hsslew = <12>;
685 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
686 reg = <0x0 0x7d004000 0x0 0x4000>;
687 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
689 clocks = <&tegra_car TEGRA124_CLK_USB2>;
690 resets = <&tegra_car 58>;
692 nvidia,phy = <&phy2>;
696 phy2: usb-phy@0,7d004000 {
697 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
698 reg = <0x0 0x7d004000 0x0 0x4000>,
699 <0x0 0x7d000000 0x0 0x4000>;
701 clocks = <&tegra_car TEGRA124_CLK_USB2>,
702 <&tegra_car TEGRA124_CLK_PLL_U>,
703 <&tegra_car TEGRA124_CLK_USBD>;
704 clock-names = "reg", "pll_u", "utmi-pads";
705 nvidia,hssync-start-delay = <0>;
706 nvidia,idle-wait-delay = <17>;
707 nvidia,elastic-limit = <16>;
708 nvidia,term-range-adj = <6>;
709 nvidia,xcvr-setup = <9>;
710 nvidia,xcvr-lsfslew = <0>;
711 nvidia,xcvr-lsrslew = <3>;
712 nvidia,hssquelch-level = <2>;
713 nvidia,hsdiscon-level = <5>;
714 nvidia,xcvr-hsslew = <12>;
719 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
720 reg = <0x0 0x7d008000 0x0 0x4000>;
721 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
723 clocks = <&tegra_car TEGRA124_CLK_USB3>;
724 resets = <&tegra_car 59>;
726 nvidia,phy = <&phy3>;
730 phy3: usb-phy@0,7d008000 {
731 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
732 reg = <0x0 0x7d008000 0x0 0x4000>,
733 <0x0 0x7d000000 0x0 0x4000>;
735 clocks = <&tegra_car TEGRA124_CLK_USB3>,
736 <&tegra_car TEGRA124_CLK_PLL_U>,
737 <&tegra_car TEGRA124_CLK_USBD>;
738 clock-names = "reg", "pll_u", "utmi-pads";
739 nvidia,hssync-start-delay = <0>;
740 nvidia,idle-wait-delay = <17>;
741 nvidia,elastic-limit = <16>;
742 nvidia,term-range-adj = <6>;
743 nvidia,xcvr-setup = <9>;
744 nvidia,xcvr-lsfslew = <0>;
745 nvidia,xcvr-lsrslew = <3>;
746 nvidia,hssquelch-level = <2>;
747 nvidia,hsdiscon-level = <5>;
748 nvidia,xcvr-hsslew = <12>;
753 #address-cells = <1>;
758 compatible = "arm,cortex-a15";
764 compatible = "arm,cortex-a15";
770 compatible = "arm,cortex-a15";
776 compatible = "arm,cortex-a15";
782 compatible = "arm,armv7-timer";
783 interrupts = <GIC_PPI 13
784 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
786 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
788 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
790 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;