arch/arm/boot/dts/tegra124.dtsi

   1 #include <dt-bindings/clock/tegra124-car.h>
   2 #include <dt-bindings/gpio/tegra-gpio.h>
   3 #include <dt-bindings/memory/tegra124-mc.h>
   4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   5 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/reset/tegra124-car.h>
   8 #include <dt-bindings/thermal/tegra124-soctherm.h>
   9
  10 #include "skeleton.dtsi"
  11
  12 / {
  13         compatible = "nvidia,tegra124";
  14         interrupt-parent = <&lic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         pcie-controller@0,01003000 {
  19                 compatible = "nvidia,tegra124-pcie";
  20                 device_type = "pci";
  21                 reg = <0x0 0x01003000 0x0 0x00000800   /* PADS registers */
  22                        0x0 0x01003800 0x0 0x00000800   /* AFI registers */
  23                        0x0 0x02000000 0x0 0x10000000>; /* configuration space */
  24                 reg-names = "pads", "afi", "cs";
  25                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
  26                              <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
  27                 interrupt-names = "intr", "msi";
  28
  29                 #interrupt-cells = <1>;
  30                 interrupt-map-mask = <0 0 0 0>;
  31                 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
  32
  33                 bus-range = <0x00 0xff>;
  34                 #address-cells = <3>;
  35                 #size-cells = <2>;
  36
  37                 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000   /* port 0 configuration space */
  38                           0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000   /* port 1 configuration space */
  39                           0x81000000 0 0x0        0x0 0x12000000 0 0x00010000   /* downstream I/O (64 KiB) */
  40                           0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000   /* non-prefetchable memory (208 MiB) */
  41                           0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
  42
  43                 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
  44                          <&tegra_car TEGRA124_CLK_AFI>,
  45                          <&tegra_car TEGRA124_CLK_PLL_E>,
  46                          <&tegra_car TEGRA124_CLK_CML0>;
  47                 clock-names = "pex", "afi", "pll_e", "cml";
  48                 resets = <&tegra_car 70>,
  49                          <&tegra_car 72>,
  50                          <&tegra_car 74>;
  51                 reset-names = "pex", "afi", "pcie_x";
  52                 status = "disabled";
  53
  54                 phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>;
  55                 phy-names = "pcie";
  56
  57                 pci@1,0 {
  58                         device_type = "pci";
  59                         assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
  60                         reg = <0x000800 0 0 0 0>;
  61                         status = "disabled";
  62
  63                         #address-cells = <3>;
  64                         #size-cells = <2>;
  65                         ranges;
  66
  67                         nvidia,num-lanes = <2>;
  68                 };
  69
  70                 pci@2,0 {
  71                         device_type = "pci";
  72                         assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
  73                         reg = <0x001000 0 0 0 0>;
  74                         status = "disabled";
  75
  76                         #address-cells = <3>;
  77                         #size-cells = <2>;
  78                         ranges;
  79
  80                         nvidia,num-lanes = <1>;
  81                 };
  82         };
  83
  84         host1x@0,50000000 {
  85                 compatible = "nvidia,tegra124-host1x", "simple-bus";
  86                 reg = <0x0 0x50000000 0x0 0x00034000>;
  87                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
  88                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
  89                 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
  90                 resets = <&tegra_car 28>;
  91                 reset-names = "host1x";
  92
  93                 #address-cells = <2>;
  94                 #size-cells = <2>;
  95
  96                 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
  97
  98                 dc@0,54200000 {
  99                         compatible = "nvidia,tegra124-dc";
 100                         reg = <0x0 0x54200000 0x0 0x00040000>;
 101                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 102                         clocks = <&tegra_car TEGRA124_CLK_DISP1>,
 103                                  <&tegra_car TEGRA124_CLK_PLL_P>;
 104                         clock-names = "dc", "parent";
 105                         resets = <&tegra_car 27>;
 106                         reset-names = "dc";
 107
 108                         iommus = <&mc TEGRA_SWGROUP_DC>;
 109
 110                         nvidia,head = <0>;
 111                 };
 112
 113                 dc@0,54240000 {
 114                         compatible = "nvidia,tegra124-dc";
 115                         reg = <0x0 0x54240000 0x0 0x00040000>;
 116                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 117                         clocks = <&tegra_car TEGRA124_CLK_DISP2>,
 118                                  <&tegra_car TEGRA124_CLK_PLL_P>;
 119                         clock-names = "dc", "parent";
 120                         resets = <&tegra_car 26>;
 121                         reset-names = "dc";
 122
 123                         iommus = <&mc TEGRA_SWGROUP_DCB>;
 124
 125                         nvidia,head = <1>;
 126                 };
 127
 128                 hdmi@0,54280000 {
 129                         compatible = "nvidia,tegra124-hdmi";
 130                         reg = <0x0 0x54280000 0x0 0x00040000>;
 131                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 132                         clocks = <&tegra_car TEGRA124_CLK_HDMI>,
 133                                  <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
 134                         clock-names = "hdmi", "parent";
 135                         resets = <&tegra_car 51>;
 136                         reset-names = "hdmi";
 137                         status = "disabled";
 138                 };
 139
 140                 sor@0,54540000 {
 141                         compatible = "nvidia,tegra124-sor";
 142                         reg = <0x0 0x54540000 0x0 0x00040000>;
 143                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 144                         clocks = <&tegra_car TEGRA124_CLK_SOR0>,
 145                                  <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
 146                                  <&tegra_car TEGRA124_CLK_PLL_DP>,
 147                                  <&tegra_car TEGRA124_CLK_CLK_M>;
 148                         clock-names = "sor", "parent", "dp", "safe";
 149                         resets = <&tegra_car 182>;
 150                         reset-names = "sor";
 151                         status = "disabled";
 152                 };
 153
 154                 dpaux: dpaux@0,545c0000 {
 155                         compatible = "nvidia,tegra124-dpaux";
 156                         reg = <0x0 0x545c0000 0x0 0x00040000>;
 157                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
 158                         clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
 159                                  <&tegra_car TEGRA124_CLK_PLL_DP>;
 160                         clock-names = "dpaux", "parent";
 161                         resets = <&tegra_car 181>;
 162                         reset-names = "dpaux";
 163                         status = "disabled";
 164                 };
 165         };
 166
 167         gic: interrupt-controller@0,50041000 {
 168                 compatible = "arm,cortex-a15-gic";
 169                 #interrupt-cells = <3>;
 170                 interrupt-controller;
 171                 reg = <0x0 0x50041000 0x0 0x1000>,
 172                       <0x0 0x50042000 0x0 0x1000>,
 173                       <0x0 0x50044000 0x0 0x2000>,
 174                       <0x0 0x50046000 0x0 0x2000>;
 175                 interrupts = <GIC_PPI 9
 176                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 177                 interrupt-parent = <&gic>;
 178         };
 179
 180         gpu@0,57000000 {
 181                 compatible = "nvidia,gk20a";
 182                 reg = <0x0 0x57000000 0x0 0x01000000>,
 183                       <0x0 0x58000000 0x0 0x01000000>;
 184                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 185                              <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
 186                 interrupt-names = "stall", "nonstall";
 187                 clocks = <&tegra_car TEGRA124_CLK_GPU>,
 188                          <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
 189                 clock-names = "gpu", "pwr";
 190                 resets = <&tegra_car 184>;
 191                 reset-names = "gpu";
 192
 193                 iommus = <&mc TEGRA_SWGROUP_GPU>;
 194
 195                 status = "disabled";
 196         };
 197
 198         lic: interrupt-controller@60004000 {
 199                 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr";
 200                 reg = <0x0 0x60004000 0x0 0x100>,
 201                       <0x0 0x60004100 0x0 0x100>,
 202                       <0x0 0x60004200 0x0 0x100>,
 203                       <0x0 0x60004300 0x0 0x100>,
 204                       <0x0 0x60004400 0x0 0x100>;
 205                 interrupt-controller;
 206                 #interrupt-cells = <3>;
 207                 interrupt-parent = <&gic>;
 208         };
 209
 210         timer@0,60005000 {
 211                 compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
 212                 reg = <0x0 0x60005000 0x0 0x400>;
 213                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 214                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 215                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 216                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 217                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 218                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 219                 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
 220         };
 221
 222         tegra_car: clock@0,60006000 {
 223                 compatible = "nvidia,tegra124-car";
 224                 reg = <0x0 0x60006000 0x0 0x1000>;
 225                 #clock-cells = <1>;
 226                 #reset-cells = <1>;
 227                 nvidia,external-memory-controller = <&emc>;
 228         };
 229
 230         flow-controller@0,60007000 {
 231                 compatible = "nvidia,tegra124-flowctrl";
 232                 reg = <0x0 0x60007000 0x0 0x1000>;
 233         };
 234
 235         actmon@0,6000c800 {
 236                 compatible = "nvidia,tegra124-actmon";
 237                 reg = <0x0 0x6000c800 0x0 0x400>;
 238                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 239                 clocks = <&tegra_car TEGRA124_CLK_ACTMON>,
 240                          <&tegra_car TEGRA124_CLK_EMC>;
 241                 clock-names = "actmon", "emc";
 242                 resets = <&tegra_car 119>;
 243                 reset-names = "actmon";
 244         };
 245
 246         gpio: gpio@0,6000d000 {
 247                 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
 248                 reg = <0x0 0x6000d000 0x0 0x1000>;
 249                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 250                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 251                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 252                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 253                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 254                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 255                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 256                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 257                 #gpio-cells = <2>;
 258                 gpio-controller;
 259                 #interrupt-cells = <2>;
 260                 interrupt-controller;
 261         };
 262
 263         apbdma: dma@0,60020000 {
 264                 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
 265                 reg = <0x0 0x60020000 0x0 0x1400>;
 266                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 267                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 268                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 269                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 270                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 271                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 272                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 273                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 274                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 275                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 276                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 277                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 278                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 279                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 280                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 281                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 282                              <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 283                              <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 284                              <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 285                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 286                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 287                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 288                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 289                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 290                              <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 291                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 292                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 293                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 294                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 295                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 296                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 297                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 298                 clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
 299                 resets = <&tegra_car 34>;
 300                 reset-names = "dma";
 301                 #dma-cells = <1>;
 302         };
 303
 304         apbmisc@0,70000800 {
 305                 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
 306                 reg = <0x0 0x70000800 0x0 0x64>,   /* Chip revision */
 307                       <0x0 0x7000e864 0x0 0x04>;   /* Strapping options */
 308         };
 309
 310         pinmux: pinmux@0,70000868 {
 311                 compatible = "nvidia,tegra124-pinmux";
 312                 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
 313                       <0x0 0x70003000 0x0 0x434>, /* Mux registers */
 314                       <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
 315         };
 316
 317         /*
 318          * There are two serial driver i.e. 8250 based simple serial
 319          * driver and APB DMA based serial driver for higher baudrate
 320          * and performace. To enable the 8250 based driver, the compatible
 321          * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
 322          * the APB DMA based serial driver, the comptible is
 323          * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
 324          */
 325         uarta: serial@0,70006000 {
 326                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 327                 reg = <0x0 0x70006000 0x0 0x40>;
 328                 reg-shift = <2>;
 329                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 330                 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
 331                 resets = <&tegra_car 6>;
 332                 reset-names = "serial";
 333                 dmas = <&apbdma 8>, <&apbdma 8>;
 334                 dma-names = "rx", "tx";
 335                 status = "disabled";
 336         };
 337
 338         uartb: serial@0,70006040 {
 339                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 340                 reg = <0x0 0x70006040 0x0 0x40>;
 341                 reg-shift = <2>;
 342                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 343                 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
 344                 resets = <&tegra_car 7>;
 345                 reset-names = "serial";
 346                 dmas = <&apbdma 9>, <&apbdma 9>;
 347                 dma-names = "rx", "tx";
 348                 status = "disabled";
 349         };
 350
 351         uartc: serial@0,70006200 {
 352                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 353                 reg = <0x0 0x70006200 0x0 0x40>;
 354                 reg-shift = <2>;
 355                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 356                 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
 357                 resets = <&tegra_car 55>;
 358                 reset-names = "serial";
 359                 dmas = <&apbdma 10>, <&apbdma 10>;
 360                 dma-names = "rx", "tx";
 361                 status = "disabled";
 362         };
 363
 364         uartd: serial@0,70006300 {
 365                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 366                 reg = <0x0 0x70006300 0x0 0x40>;
 367                 reg-shift = <2>;
 368                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 369                 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
 370                 resets = <&tegra_car 65>;
 371                 reset-names = "serial";
 372                 dmas = <&apbdma 19>, <&apbdma 19>;
 373                 dma-names = "rx", "tx";
 374                 status = "disabled";
 375         };
 376
 377         pwm: pwm@0,7000a000 {
 378                 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
 379                 reg = <0x0 0x7000a000 0x0 0x100>;
 380                 #pwm-cells = <2>;
 381                 clocks = <&tegra_car TEGRA124_CLK_PWM>;
 382                 resets = <&tegra_car 17>;
 383                 reset-names = "pwm";
 384                 status = "disabled";
 385         };
 386
 387         i2c@0,7000c000 {
 388                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 389                 reg = <0x0 0x7000c000 0x0 0x100>;
 390                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 391                 #address-cells = <1>;
 392                 #size-cells = <0>;
 393                 clocks = <&tegra_car TEGRA124_CLK_I2C1>;
 394                 clock-names = "div-clk";
 395                 resets = <&tegra_car 12>;
 396                 reset-names = "i2c";
 397                 dmas = <&apbdma 21>, <&apbdma 21>;
 398                 dma-names = "rx", "tx";
 399                 status = "disabled";
 400         };
 401
 402         i2c@0,7000c400 {
 403                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 404                 reg = <0x0 0x7000c400 0x0 0x100>;
 405                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 406                 #address-cells = <1>;
 407                 #size-cells = <0>;
 408                 clocks = <&tegra_car TEGRA124_CLK_I2C2>;
 409                 clock-names = "div-clk";
 410                 resets = <&tegra_car 54>;
 411                 reset-names = "i2c";
 412                 dmas = <&apbdma 22>, <&apbdma 22>;
 413                 dma-names = "rx", "tx";
 414                 status = "disabled";
 415         };
 416
 417         i2c@0,7000c500 {
 418                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 419                 reg = <0x0 0x7000c500 0x0 0x100>;
 420                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 421                 #address-cells = <1>;
 422                 #size-cells = <0>;
 423                 clocks = <&tegra_car TEGRA124_CLK_I2C3>;
 424                 clock-names = "div-clk";
 425                 resets = <&tegra_car 67>;
 426                 reset-names = "i2c";
 427                 dmas = <&apbdma 23>, <&apbdma 23>;
 428                 dma-names = "rx", "tx";
 429                 status = "disabled";
 430         };
 431
 432         i2c@0,7000c700 {
 433                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 434                 reg = <0x0 0x7000c700 0x0 0x100>;
 435                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 436                 #address-cells = <1>;
 437                 #size-cells = <0>;
 438                 clocks = <&tegra_car TEGRA124_CLK_I2C4>;
 439                 clock-names = "div-clk";
 440                 resets = <&tegra_car 103>;
 441                 reset-names = "i2c";
 442                 dmas = <&apbdma 26>, <&apbdma 26>;
 443                 dma-names = "rx", "tx";
 444                 status = "disabled";
 445         };
 446
 447         i2c@0,7000d000 {
 448                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 449                 reg = <0x0 0x7000d000 0x0 0x100>;
 450                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 451                 #address-cells = <1>;
 452                 #size-cells = <0>;
 453                 clocks = <&tegra_car TEGRA124_CLK_I2C5>;
 454                 clock-names = "div-clk";
 455                 resets = <&tegra_car 47>;
 456                 reset-names = "i2c";
 457                 dmas = <&apbdma 24>, <&apbdma 24>;
 458                 dma-names = "rx", "tx";
 459                 status = "disabled";
 460         };
 461
 462         i2c@0,7000d100 {
 463                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 464                 reg = <0x0 0x7000d100 0x0 0x100>;
 465                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 466                 #address-cells = <1>;
 467                 #size-cells = <0>;
 468                 clocks = <&tegra_car TEGRA124_CLK_I2C6>;
 469                 clock-names = "div-clk";
 470                 resets = <&tegra_car 166>;
 471                 reset-names = "i2c";
 472                 dmas = <&apbdma 30>, <&apbdma 30>;
 473                 dma-names = "rx", "tx";
 474                 status = "disabled";
 475         };
 476
 477         spi@0,7000d400 {
 478                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 479                 reg = <0x0 0x7000d400 0x0 0x200>;
 480                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 481                 #address-cells = <1>;
 482                 #size-cells = <0>;
 483                 clocks = <&tegra_car TEGRA124_CLK_SBC1>;
 484                 clock-names = "spi";
 485                 resets = <&tegra_car 41>;
 486                 reset-names = "spi";
 487                 dmas = <&apbdma 15>, <&apbdma 15>;
 488                 dma-names = "rx", "tx";
 489                 status = "disabled";
 490         };
 491
 492         spi@0,7000d600 {
 493                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 494                 reg = <0x0 0x7000d600 0x0 0x200>;
 495                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 496                 #address-cells = <1>;
 497                 #size-cells = <0>;
 498                 clocks = <&tegra_car TEGRA124_CLK_SBC2>;
 499                 clock-names = "spi";
 500                 resets = <&tegra_car 44>;
 501                 reset-names = "spi";
 502                 dmas = <&apbdma 16>, <&apbdma 16>;
 503                 dma-names = "rx", "tx";
 504                 status = "disabled";
 505         };
 506
 507         spi@0,7000d800 {
 508                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 509                 reg = <0x0 0x7000d800 0x0 0x200>;
 510                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 511                 #address-cells = <1>;
 512                 #size-cells = <0>;
 513                 clocks = <&tegra_car TEGRA124_CLK_SBC3>;
 514                 clock-names = "spi";
 515                 resets = <&tegra_car 46>;
 516                 reset-names = "spi";
 517                 dmas = <&apbdma 17>, <&apbdma 17>;
 518                 dma-names = "rx", "tx";
 519                 status = "disabled";
 520         };
 521
 522         spi@0,7000da00 {
 523                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 524                 reg = <0x0 0x7000da00 0x0 0x200>;
 525                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 526                 #address-cells = <1>;
 527                 #size-cells = <0>;
 528                 clocks = <&tegra_car TEGRA124_CLK_SBC4>;
 529                 clock-names = "spi";
 530                 resets = <&tegra_car 68>;
 531                 reset-names = "spi";
 532                 dmas = <&apbdma 18>, <&apbdma 18>;
 533                 dma-names = "rx", "tx";
 534                 status = "disabled";
 535         };
 536
 537         spi@0,7000dc00 {
 538                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 539                 reg = <0x0 0x7000dc00 0x0 0x200>;
 540                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 541                 #address-cells = <1>;
 542                 #size-cells = <0>;
 543                 clocks = <&tegra_car TEGRA124_CLK_SBC5>;
 544                 clock-names = "spi";
 545                 resets = <&tegra_car 104>;
 546                 reset-names = "spi";
 547                 dmas = <&apbdma 27>, <&apbdma 27>;
 548                 dma-names = "rx", "tx";
 549                 status = "disabled";
 550         };
 551
 552         spi@0,7000de00 {
 553                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 554                 reg = <0x0 0x7000de00 0x0 0x200>;
 555                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 556                 #address-cells = <1>;
 557                 #size-cells = <0>;
 558                 clocks = <&tegra_car TEGRA124_CLK_SBC6>;
 559                 clock-names = "spi";
 560                 resets = <&tegra_car 105>;
 561                 reset-names = "spi";
 562                 dmas = <&apbdma 28>, <&apbdma 28>;
 563                 dma-names = "rx", "tx";
 564                 status = "disabled";
 565         };
 566
 567         rtc@0,7000e000 {
 568                 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
 569                 reg = <0x0 0x7000e000 0x0 0x100>;
 570                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 571                 clocks = <&tegra_car TEGRA124_CLK_RTC>;
 572         };
 573
 574         pmc@0,7000e400 {
 575                 compatible = "nvidia,tegra124-pmc";
 576                 reg = <0x0 0x7000e400 0x0 0x400>;
 577                 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
 578                 clock-names = "pclk", "clk32k_in";
 579         };
 580
 581         fuse@0,7000f800 {
 582                 compatible = "nvidia,tegra124-efuse";
 583                 reg = <0x0 0x7000f800 0x0 0x400>;
 584                 clocks = <&tegra_car TEGRA124_CLK_FUSE>;
 585                 clock-names = "fuse";
 586                 resets = <&tegra_car 39>;
 587                 reset-names = "fuse";
 588         };
 589
 590         mc: memory-controller@0,70019000 {
 591                 compatible = "nvidia,tegra124-mc";
 592                 reg = <0x0 0x70019000 0x0 0x1000>;
 593                 clocks = <&tegra_car TEGRA124_CLK_MC>;
 594                 clock-names = "mc";
 595
 596                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 597
 598                 #iommu-cells = <1>;
 599         };
 600
 601         emc: emc@0,7001b000 {
 602                 compatible = "nvidia,tegra124-emc";
 603                 reg = <0x0 0x7001b000 0x0 0x1000>;
 604
 605                 nvidia,memory-controller = <&mc>;
 606         };
 607
 608         sata@0,70020000 {
 609                 compatible = "nvidia,tegra124-ahci";
 610
 611                 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
 612                         <0x0 0x70020000 0x0 0x7000>; /* SATA */
 613
 614                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 615
 616                 clocks = <&tegra_car TEGRA124_CLK_SATA>,
 617                         <&tegra_car TEGRA124_CLK_SATA_OOB>,
 618                         <&tegra_car TEGRA124_CLK_CML1>,
 619                         <&tegra_car TEGRA124_CLK_PLL_E>;
 620                 clock-names = "sata", "sata-oob", "cml1", "pll_e";
 621
 622                 resets = <&tegra_car 124>,
 623                         <&tegra_car 123>,
 624                         <&tegra_car 129>;
 625                 reset-names = "sata", "sata-oob", "sata-cold";
 626
 627                 phys = <&padctl TEGRA_XUSB_PADCTL_SATA>;
 628                 phy-names = "sata-phy";
 629
 630                 status = "disabled";
 631         };
 632
 633         hda@0,70030000 {
 634                 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda";
 635                 reg = <0x0 0x70030000 0x0 0x10000>;
 636                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 637                 clocks = <&tegra_car TEGRA124_CLK_HDA>,
 638                          <&tegra_car TEGRA124_CLK_HDA2HDMI>,
 639                          <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
 640                 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
 641                 resets = <&tegra_car 125>, /* hda */
 642                          <&tegra_car 128>, /* hda2hdmi */
 643                          <&tegra_car 111>; /* hda2codec_2x */
 644                 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
 645                 status = "disabled";
 646         };
 647
 648         padctl: padctl@0,7009f000 {
 649                 compatible = "nvidia,tegra124-xusb-padctl";
 650                 reg = <0x0 0x7009f000 0x0 0x1000>;
 651                 resets = <&tegra_car 142>;
 652                 reset-names = "padctl";
 653
 654                 #phy-cells = <1>;
 655         };
 656
 657         sdhci@0,700b0000 {
 658                 compatible = "nvidia,tegra124-sdhci";
 659                 reg = <0x0 0x700b0000 0x0 0x200>;
 660                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 661                 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
 662                 resets = <&tegra_car 14>;
 663                 reset-names = "sdhci";
 664                 status = "disabled";
 665         };
 666
 667         sdhci@0,700b0200 {
 668                 compatible = "nvidia,tegra124-sdhci";
 669                 reg = <0x0 0x700b0200 0x0 0x200>;
 670                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 671                 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
 672                 resets = <&tegra_car 9>;
 673                 reset-names = "sdhci";
 674                 status = "disabled";
 675         };
 676
 677         sdhci@0,700b0400 {
 678                 compatible = "nvidia,tegra124-sdhci";
 679                 reg = <0x0 0x700b0400 0x0 0x200>;
 680                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 681                 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
 682                 resets = <&tegra_car 69>;
 683                 reset-names = "sdhci";
 684                 status = "disabled";
 685         };
 686
 687         sdhci@0,700b0600 {
 688                 compatible = "nvidia,tegra124-sdhci";
 689                 reg = <0x0 0x700b0600 0x0 0x200>;
 690                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 691                 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
 692                 resets = <&tegra_car 15>;
 693                 reset-names = "sdhci";
 694                 status = "disabled";
 695         };
 696
 697         soctherm: thermal-sensor@0,700e2000 {
 698                 compatible = "nvidia,tegra124-soctherm";
 699                 reg = <0x0 0x700e2000 0x0 0x1000>;
 700                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 701                 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
 702                         <&tegra_car TEGRA124_CLK_SOC_THERM>;
 703                 clock-names = "tsensor", "soctherm";
 704                 resets = <&tegra_car 78>;
 705                 reset-names = "soctherm";
 706                 #thermal-sensor-cells = <1>;
 707         };
 708
 709         dfll: clock@0,70110000 {
 710                 compatible = "nvidia,tegra124-dfll";
 711                 reg = <0 0x70110000 0 0x100>, /* DFLL control */
 712                       <0 0x70110000 0 0x100>, /* I2C output control */
 713                       <0 0x70110100 0 0x100>, /* Integrated I2C controller */
 714                       <0 0x70110200 0 0x100>; /* Look-up table RAM */
 715                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 716                 clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>,
 717                          <&tegra_car TEGRA124_CLK_DFLL_REF>,
 718                          <&tegra_car TEGRA124_CLK_I2C5>;
 719                 clock-names = "soc", "ref", "i2c";
 720                 resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
 721                 reset-names = "dvco";
 722                 #clock-cells = <0>;
 723                 clock-output-names = "dfllCPU_out";
 724                 nvidia,sample-rate = <12500>;
 725                 nvidia,droop-ctrl = <0x00000f00>;
 726                 nvidia,force-mode = <1>;
 727                 nvidia,cf = <10>;
 728                 nvidia,ci = <0>;
 729                 nvidia,cg = <2>;
 730                 status = "disabled";
 731         };
 732
 733         ahub@0,70300000 {
 734                 compatible = "nvidia,tegra124-ahub";
 735                 reg = <0x0 0x70300000 0x0 0x200>,
 736                       <0x0 0x70300800 0x0 0x800>,
 737                       <0x0 0x70300200 0x0 0x600>;
 738                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 739                 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
 740                          <&tegra_car TEGRA124_CLK_APBIF>;
 741                 clock-names = "d_audio", "apbif";
 742                 resets = <&tegra_car 106>, /* d_audio */
 743                          <&tegra_car 107>, /* apbif */
 744                          <&tegra_car 30>,  /* i2s0 */
 745                          <&tegra_car 11>,  /* i2s1 */
 746                          <&tegra_car 18>,  /* i2s2 */
 747                          <&tegra_car 101>, /* i2s3 */
 748                          <&tegra_car 102>, /* i2s4 */
 749                          <&tegra_car 108>, /* dam0 */
 750                          <&tegra_car 109>, /* dam1 */
 751                          <&tegra_car 110>, /* dam2 */
 752                          <&tegra_car 10>,  /* spdif */
 753                          <&tegra_car 153>, /* amx */
 754                          <&tegra_car 185>, /* amx1 */
 755                          <&tegra_car 154>, /* adx */
 756                          <&tegra_car 180>, /* adx1 */
 757                          <&tegra_car 186>, /* afc0 */
 758                          <&tegra_car 187>, /* afc1 */
 759                          <&tegra_car 188>, /* afc2 */
 760                          <&tegra_car 189>, /* afc3 */
 761                          <&tegra_car 190>, /* afc4 */
 762                          <&tegra_car 191>; /* afc5 */
 763                 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 764                               "i2s3", "i2s4", "dam0", "dam1", "dam2",
 765                               "spdif", "amx", "amx1", "adx", "adx1",
 766                               "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
 767                 dmas = <&apbdma 1>, <&apbdma 1>,
 768                        <&apbdma 2>, <&apbdma 2>,
 769                        <&apbdma 3>, <&apbdma 3>,
 770                        <&apbdma 4>, <&apbdma 4>,
 771                        <&apbdma 6>, <&apbdma 6>,
 772                        <&apbdma 7>, <&apbdma 7>,
 773                        <&apbdma 12>, <&apbdma 12>,
 774                        <&apbdma 13>, <&apbdma 13>,
 775                        <&apbdma 14>, <&apbdma 14>,
 776                        <&apbdma 29>, <&apbdma 29>;
 777                 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
 778                             "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
 779                             "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
 780                             "rx9", "tx9";
 781                 ranges;
 782                 #address-cells = <2>;
 783                 #size-cells = <2>;
 784
 785                 tegra_i2s0: i2s@0,70301000 {
 786                         compatible = "nvidia,tegra124-i2s";
 787                         reg = <0x0 0x70301000 0x0 0x100>;
 788                         nvidia,ahub-cif-ids = <4 4>;
 789                         clocks = <&tegra_car TEGRA124_CLK_I2S0>;
 790                         resets = <&tegra_car 30>;
 791                         reset-names = "i2s";
 792                         status = "disabled";
 793                 };
 794
 795                 tegra_i2s1: i2s@0,70301100 {
 796                         compatible = "nvidia,tegra124-i2s";
 797                         reg = <0x0 0x70301100 0x0 0x100>;
 798                         nvidia,ahub-cif-ids = <5 5>;
 799                         clocks = <&tegra_car TEGRA124_CLK_I2S1>;
 800                         resets = <&tegra_car 11>;
 801                         reset-names = "i2s";
 802                         status = "disabled";
 803                 };
 804
 805                 tegra_i2s2: i2s@0,70301200 {
 806                         compatible = "nvidia,tegra124-i2s";
 807                         reg = <0x0 0x70301200 0x0 0x100>;
 808                         nvidia,ahub-cif-ids = <6 6>;
 809                         clocks = <&tegra_car TEGRA124_CLK_I2S2>;
 810                         resets = <&tegra_car 18>;
 811                         reset-names = "i2s";
 812                         status = "disabled";
 813                 };
 814
 815                 tegra_i2s3: i2s@0,70301300 {
 816                         compatible = "nvidia,tegra124-i2s";
 817                         reg = <0x0 0x70301300 0x0 0x100>;
 818                         nvidia,ahub-cif-ids = <7 7>;
 819                         clocks = <&tegra_car TEGRA124_CLK_I2S3>;
 820                         resets = <&tegra_car 101>;
 821                         reset-names = "i2s";
 822                         status = "disabled";
 823                 };
 824
 825                 tegra_i2s4: i2s@0,70301400 {
 826                         compatible = "nvidia,tegra124-i2s";
 827                         reg = <0x0 0x70301400 0x0 0x100>;
 828                         nvidia,ahub-cif-ids = <8 8>;
 829                         clocks = <&tegra_car TEGRA124_CLK_I2S4>;
 830                         resets = <&tegra_car 102>;
 831                         reset-names = "i2s";
 832                         status = "disabled";
 833                 };
 834         };
 835
 836         usb@0,7d000000 {
 837                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
 838                 reg = <0x0 0x7d000000 0x0 0x4000>;
 839                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 840                 phy_type = "utmi";
 841                 clocks = <&tegra_car TEGRA124_CLK_USBD>;
 842                 resets = <&tegra_car 22>;
 843                 reset-names = "usb";
 844                 nvidia,phy = <&phy1>;
 845                 status = "disabled";
 846         };
 847
 848         phy1: usb-phy@0,7d000000 {
 849                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
 850                 reg = <0x0 0x7d000000 0x0 0x4000>,
 851                       <0x0 0x7d000000 0x0 0x4000>;
 852                 phy_type = "utmi";
 853                 clocks = <&tegra_car TEGRA124_CLK_USBD>,
 854                          <&tegra_car TEGRA124_CLK_PLL_U>,
 855                          <&tegra_car TEGRA124_CLK_USBD>;
 856                 clock-names = "reg", "pll_u", "utmi-pads";
 857                 resets = <&tegra_car 22>, <&tegra_car 22>;
 858                 reset-names = "usb", "utmi-pads";
 859                 nvidia,hssync-start-delay = <0>;
 860                 nvidia,idle-wait-delay = <17>;
 861                 nvidia,elastic-limit = <16>;
 862                 nvidia,term-range-adj = <6>;
 863                 nvidia,xcvr-setup = <9>;
 864                 nvidia,xcvr-lsfslew = <0>;
 865                 nvidia,xcvr-lsrslew = <3>;
 866                 nvidia,hssquelch-level = <2>;
 867                 nvidia,hsdiscon-level = <5>;
 868                 nvidia,xcvr-hsslew = <12>;
 869                 nvidia,has-utmi-pad-registers;
 870                 status = "disabled";
 871         };
 872
 873         usb@0,7d004000 {
 874                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
 875                 reg = <0x0 0x7d004000 0x0 0x4000>;
 876                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 877                 phy_type = "utmi";
 878                 clocks = <&tegra_car TEGRA124_CLK_USB2>;
 879                 resets = <&tegra_car 58>;
 880                 reset-names = "usb";
 881                 nvidia,phy = <&phy2>;
 882                 status = "disabled";
 883         };
 884
 885         phy2: usb-phy@0,7d004000 {
 886                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
 887                 reg = <0x0 0x7d004000 0x0 0x4000>,
 888                       <0x0 0x7d000000 0x0 0x4000>;
 889                 phy_type = "utmi";
 890                 clocks = <&tegra_car TEGRA124_CLK_USB2>,
 891                          <&tegra_car TEGRA124_CLK_PLL_U>,
 892                          <&tegra_car TEGRA124_CLK_USBD>;
 893                 clock-names = "reg", "pll_u", "utmi-pads";
 894                 resets = <&tegra_car 58>, <&tegra_car 22>;
 895                 reset-names = "usb", "utmi-pads";
 896                 nvidia,hssync-start-delay = <0>;
 897                 nvidia,idle-wait-delay = <17>;
 898                 nvidia,elastic-limit = <16>;
 899                 nvidia,term-range-adj = <6>;
 900                 nvidia,xcvr-setup = <9>;
 901                 nvidia,xcvr-lsfslew = <0>;
 902                 nvidia,xcvr-lsrslew = <3>;
 903                 nvidia,hssquelch-level = <2>;
 904                 nvidia,hsdiscon-level = <5>;
 905                 nvidia,xcvr-hsslew = <12>;
 906                 status = "disabled";
 907         };
 908
 909         usb@0,7d008000 {
 910                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
 911                 reg = <0x0 0x7d008000 0x0 0x4000>;
 912                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 913                 phy_type = "utmi";
 914                 clocks = <&tegra_car TEGRA124_CLK_USB3>;
 915                 resets = <&tegra_car 59>;
 916                 reset-names = "usb";
 917                 nvidia,phy = <&phy3>;
 918                 status = "disabled";
 919         };
 920
 921         phy3: usb-phy@0,7d008000 {
 922                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
 923                 reg = <0x0 0x7d008000 0x0 0x4000>,
 924                       <0x0 0x7d000000 0x0 0x4000>;
 925                 phy_type = "utmi";
 926                 clocks = <&tegra_car TEGRA124_CLK_USB3>,
 927                          <&tegra_car TEGRA124_CLK_PLL_U>,
 928                          <&tegra_car TEGRA124_CLK_USBD>;
 929                 clock-names = "reg", "pll_u", "utmi-pads";
 930                 resets = <&tegra_car 59>, <&tegra_car 22>;
 931                 reset-names = "usb", "utmi-pads";
 932                 nvidia,hssync-start-delay = <0>;
 933                 nvidia,idle-wait-delay = <17>;
 934                 nvidia,elastic-limit = <16>;
 935                 nvidia,term-range-adj = <6>;
 936                 nvidia,xcvr-setup = <9>;
 937                 nvidia,xcvr-lsfslew = <0>;
 938                 nvidia,xcvr-lsrslew = <3>;
 939                 nvidia,hssquelch-level = <2>;
 940                 nvidia,hsdiscon-level = <5>;
 941                 nvidia,xcvr-hsslew = <12>;
 942                 status = "disabled";
 943         };
 944
 945         cpus {
 946                 #address-cells = <1>;
 947                 #size-cells = <0>;
 948
 949                 cpu@0 {
 950                         device_type = "cpu";
 951                         compatible = "arm,cortex-a15";
 952                         reg = <0>;
 953
 954                         clocks = <&tegra_car TEGRA124_CLK_CCLK_G>,
 955                                  <&tegra_car TEGRA124_CLK_CCLK_LP>,
 956                                  <&tegra_car TEGRA124_CLK_PLL_X>,
 957                                  <&tegra_car TEGRA124_CLK_PLL_P>,
 958                                  <&dfll>;
 959                         clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
 960                         /* FIXME: what's the actual transition time? */
 961                         clock-latency = <300000>;
 962                 };
 963
 964                 cpu@1 {
 965                         device_type = "cpu";
 966                         compatible = "arm,cortex-a15";
 967                         reg = <1>;
 968                 };
 969
 970                 cpu@2 {
 971                         device_type = "cpu";
 972                         compatible = "arm,cortex-a15";
 973                         reg = <2>;
 974                 };
 975
 976                 cpu@3 {
 977                         device_type = "cpu";
 978                         compatible = "arm,cortex-a15";
 979                         reg = <3>;
 980                 };
 981         };
 982
 983         pmu {
 984                 compatible = "arm,cortex-a15-pmu";
 985                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
 986                              <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
 987                              <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 988                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 989                 interrupt-affinity = <&{/cpus/cpu@0}>,
 990                                      <&{/cpus/cpu@1}>,
 991                                      <&{/cpus/cpu@2}>,
 992                                      <&{/cpus/cpu@3}>;
 993         };
 994
 995         thermal-zones {
 996                 cpu {
 997                         polling-delay-passive = <1000>;
 998                         polling-delay = <1000>;
 999
1000                         thermal-sensors =
1001                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
1002                 };
1003
1004                 mem {
1005                         polling-delay-passive = <1000>;
1006                         polling-delay = <1000>;
1007
1008                         thermal-sensors =
1009                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
1010                 };
1011
1012                 gpu {
1013                         polling-delay-passive = <1000>;
1014                         polling-delay = <1000>;
1015
1016                         thermal-sensors =
1017                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
1018                 };
1019
1020                 pllx {
1021                         polling-delay-passive = <1000>;
1022                         polling-delay = <1000>;
1023
1024                         thermal-sensors =
1025                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
1026                 };
1027         };
1028
1029         timer {
1030                 compatible = "arm,armv7-timer";
1031                 interrupts = <GIC_PPI 13
1032                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1033                              <GIC_PPI 14
1034                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1035                              <GIC_PPI 11
1036                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1037                              <GIC_PPI 10
1038                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1039                 interrupt-parent = <&gic>;
1040         };
1041 };