1 #include <dt-bindings/clock/tegra124-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/memory/tegra124-mc.h>
4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/tegra124-car.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
10 #include "skeleton.dtsi"
13 compatible = "nvidia,tegra124";
14 interrupt-parent = <&lic>;
18 pcie-controller@0,01003000 {
19 compatible = "nvidia,tegra124-pcie";
21 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
22 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
23 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
24 reg-names = "pads", "afi", "cs";
25 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
26 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
27 interrupt-names = "intr", "msi";
29 #interrupt-cells = <1>;
30 interrupt-map-mask = <0 0 0 0>;
31 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
33 bus-range = <0x00 0xff>;
37 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
38 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
39 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
40 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
41 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
43 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
44 <&tegra_car TEGRA124_CLK_AFI>,
45 <&tegra_car TEGRA124_CLK_PLL_E>,
46 <&tegra_car TEGRA124_CLK_CML0>;
47 clock-names = "pex", "afi", "pll_e", "cml";
48 resets = <&tegra_car 70>,
51 reset-names = "pex", "afi", "pcie_x";
54 phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>;
59 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
60 reg = <0x000800 0 0 0 0>;
67 nvidia,num-lanes = <2>;
72 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
73 reg = <0x001000 0 0 0 0>;
80 nvidia,num-lanes = <1>;
85 compatible = "nvidia,tegra124-host1x", "simple-bus";
86 reg = <0x0 0x50000000 0x0 0x00034000>;
87 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
88 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
89 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
90 resets = <&tegra_car 28>;
91 reset-names = "host1x";
96 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
99 compatible = "nvidia,tegra124-dc";
100 reg = <0x0 0x54200000 0x0 0x00040000>;
101 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
102 clocks = <&tegra_car TEGRA124_CLK_DISP1>,
103 <&tegra_car TEGRA124_CLK_PLL_P>;
104 clock-names = "dc", "parent";
105 resets = <&tegra_car 27>;
108 iommus = <&mc TEGRA_SWGROUP_DC>;
114 compatible = "nvidia,tegra124-dc";
115 reg = <0x0 0x54240000 0x0 0x00040000>;
116 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
117 clocks = <&tegra_car TEGRA124_CLK_DISP2>,
118 <&tegra_car TEGRA124_CLK_PLL_P>;
119 clock-names = "dc", "parent";
120 resets = <&tegra_car 26>;
123 iommus = <&mc TEGRA_SWGROUP_DCB>;
129 compatible = "nvidia,tegra124-hdmi";
130 reg = <0x0 0x54280000 0x0 0x00040000>;
131 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
132 clocks = <&tegra_car TEGRA124_CLK_HDMI>,
133 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
134 clock-names = "hdmi", "parent";
135 resets = <&tegra_car 51>;
136 reset-names = "hdmi";
141 compatible = "nvidia,tegra124-sor";
142 reg = <0x0 0x54540000 0x0 0x00040000>;
143 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
144 clocks = <&tegra_car TEGRA124_CLK_SOR0>,
145 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
146 <&tegra_car TEGRA124_CLK_PLL_DP>,
147 <&tegra_car TEGRA124_CLK_CLK_M>;
148 clock-names = "sor", "parent", "dp", "safe";
149 resets = <&tegra_car 182>;
154 dpaux: dpaux@0,545c0000 {
155 compatible = "nvidia,tegra124-dpaux";
156 reg = <0x0 0x545c0000 0x0 0x00040000>;
157 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
158 clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
159 <&tegra_car TEGRA124_CLK_PLL_DP>;
160 clock-names = "dpaux", "parent";
161 resets = <&tegra_car 181>;
162 reset-names = "dpaux";
167 gic: interrupt-controller@0,50041000 {
168 compatible = "arm,cortex-a15-gic";
169 #interrupt-cells = <3>;
170 interrupt-controller;
171 reg = <0x0 0x50041000 0x0 0x1000>,
172 <0x0 0x50042000 0x0 0x1000>,
173 <0x0 0x50044000 0x0 0x2000>,
174 <0x0 0x50046000 0x0 0x2000>;
175 interrupts = <GIC_PPI 9
176 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
177 interrupt-parent = <&gic>;
181 compatible = "nvidia,gk20a";
182 reg = <0x0 0x57000000 0x0 0x01000000>,
183 <0x0 0x58000000 0x0 0x01000000>;
184 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
185 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
186 interrupt-names = "stall", "nonstall";
187 clocks = <&tegra_car TEGRA124_CLK_GPU>,
188 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
189 clock-names = "gpu", "pwr";
190 resets = <&tegra_car 184>;
193 iommus = <&mc TEGRA_SWGROUP_GPU>;
198 lic: interrupt-controller@60004000 {
199 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr";
200 reg = <0x0 0x60004000 0x0 0x100>,
201 <0x0 0x60004100 0x0 0x100>,
202 <0x0 0x60004200 0x0 0x100>,
203 <0x0 0x60004300 0x0 0x100>,
204 <0x0 0x60004400 0x0 0x100>;
205 interrupt-controller;
206 #interrupt-cells = <3>;
207 interrupt-parent = <&gic>;
211 compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
212 reg = <0x0 0x60005000 0x0 0x400>;
213 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
222 tegra_car: clock@0,60006000 {
223 compatible = "nvidia,tegra124-car";
224 reg = <0x0 0x60006000 0x0 0x1000>;
227 nvidia,external-memory-controller = <&emc>;
230 flow-controller@0,60007000 {
231 compatible = "nvidia,tegra124-flowctrl";
232 reg = <0x0 0x60007000 0x0 0x1000>;
236 compatible = "nvidia,tegra124-actmon";
237 reg = <0x0 0x6000c800 0x0 0x400>;
238 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
239 clocks = <&tegra_car TEGRA124_CLK_ACTMON>,
240 <&tegra_car TEGRA124_CLK_EMC>;
241 clock-names = "actmon", "emc";
242 resets = <&tegra_car 119>;
243 reset-names = "actmon";
246 gpio: gpio@0,6000d000 {
247 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
248 reg = <0x0 0x6000d000 0x0 0x1000>;
249 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
250 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
251 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
254 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
255 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
256 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
259 #interrupt-cells = <2>;
260 interrupt-controller;
262 gpio-ranges = <&pinmux 0 0 251>;
266 apbdma: dma@0,60020000 {
267 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
268 reg = <0x0 0x60020000 0x0 0x1400>;
269 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
270 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
271 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
272 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
273 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
274 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
275 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
276 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
277 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
278 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
279 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
287 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
288 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
290 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
297 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
298 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
299 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
300 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
301 clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
302 resets = <&tegra_car 34>;
308 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
309 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
310 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */
313 pinmux: pinmux@0,70000868 {
314 compatible = "nvidia,tegra124-pinmux";
315 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
316 <0x0 0x70003000 0x0 0x434>, /* Mux registers */
317 <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
321 * There are two serial driver i.e. 8250 based simple serial
322 * driver and APB DMA based serial driver for higher baudrate
323 * and performace. To enable the 8250 based driver, the compatible
324 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
325 * the APB DMA based serial driver, the comptible is
326 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
328 uarta: serial@0,70006000 {
329 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
330 reg = <0x0 0x70006000 0x0 0x40>;
332 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
333 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
334 resets = <&tegra_car 6>;
335 reset-names = "serial";
336 dmas = <&apbdma 8>, <&apbdma 8>;
337 dma-names = "rx", "tx";
341 uartb: serial@0,70006040 {
342 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
343 reg = <0x0 0x70006040 0x0 0x40>;
345 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
346 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
347 resets = <&tegra_car 7>;
348 reset-names = "serial";
349 dmas = <&apbdma 9>, <&apbdma 9>;
350 dma-names = "rx", "tx";
354 uartc: serial@0,70006200 {
355 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
356 reg = <0x0 0x70006200 0x0 0x40>;
358 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
359 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
360 resets = <&tegra_car 55>;
361 reset-names = "serial";
362 dmas = <&apbdma 10>, <&apbdma 10>;
363 dma-names = "rx", "tx";
367 uartd: serial@0,70006300 {
368 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
369 reg = <0x0 0x70006300 0x0 0x40>;
371 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
372 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
373 resets = <&tegra_car 65>;
374 reset-names = "serial";
375 dmas = <&apbdma 19>, <&apbdma 19>;
376 dma-names = "rx", "tx";
380 pwm: pwm@0,7000a000 {
381 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
382 reg = <0x0 0x7000a000 0x0 0x100>;
384 clocks = <&tegra_car TEGRA124_CLK_PWM>;
385 resets = <&tegra_car 17>;
391 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
392 reg = <0x0 0x7000c000 0x0 0x100>;
393 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
394 #address-cells = <1>;
396 clocks = <&tegra_car TEGRA124_CLK_I2C1>;
397 clock-names = "div-clk";
398 resets = <&tegra_car 12>;
400 dmas = <&apbdma 21>, <&apbdma 21>;
401 dma-names = "rx", "tx";
406 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
407 reg = <0x0 0x7000c400 0x0 0x100>;
408 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
409 #address-cells = <1>;
411 clocks = <&tegra_car TEGRA124_CLK_I2C2>;
412 clock-names = "div-clk";
413 resets = <&tegra_car 54>;
415 dmas = <&apbdma 22>, <&apbdma 22>;
416 dma-names = "rx", "tx";
421 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
422 reg = <0x0 0x7000c500 0x0 0x100>;
423 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
424 #address-cells = <1>;
426 clocks = <&tegra_car TEGRA124_CLK_I2C3>;
427 clock-names = "div-clk";
428 resets = <&tegra_car 67>;
430 dmas = <&apbdma 23>, <&apbdma 23>;
431 dma-names = "rx", "tx";
436 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
437 reg = <0x0 0x7000c700 0x0 0x100>;
438 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
439 #address-cells = <1>;
441 clocks = <&tegra_car TEGRA124_CLK_I2C4>;
442 clock-names = "div-clk";
443 resets = <&tegra_car 103>;
445 dmas = <&apbdma 26>, <&apbdma 26>;
446 dma-names = "rx", "tx";
451 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
452 reg = <0x0 0x7000d000 0x0 0x100>;
453 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
454 #address-cells = <1>;
456 clocks = <&tegra_car TEGRA124_CLK_I2C5>;
457 clock-names = "div-clk";
458 resets = <&tegra_car 47>;
460 dmas = <&apbdma 24>, <&apbdma 24>;
461 dma-names = "rx", "tx";
466 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
467 reg = <0x0 0x7000d100 0x0 0x100>;
468 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
469 #address-cells = <1>;
471 clocks = <&tegra_car TEGRA124_CLK_I2C6>;
472 clock-names = "div-clk";
473 resets = <&tegra_car 166>;
475 dmas = <&apbdma 30>, <&apbdma 30>;
476 dma-names = "rx", "tx";
481 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
482 reg = <0x0 0x7000d400 0x0 0x200>;
483 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
484 #address-cells = <1>;
486 clocks = <&tegra_car TEGRA124_CLK_SBC1>;
488 resets = <&tegra_car 41>;
490 dmas = <&apbdma 15>, <&apbdma 15>;
491 dma-names = "rx", "tx";
496 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
497 reg = <0x0 0x7000d600 0x0 0x200>;
498 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
499 #address-cells = <1>;
501 clocks = <&tegra_car TEGRA124_CLK_SBC2>;
503 resets = <&tegra_car 44>;
505 dmas = <&apbdma 16>, <&apbdma 16>;
506 dma-names = "rx", "tx";
511 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
512 reg = <0x0 0x7000d800 0x0 0x200>;
513 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
514 #address-cells = <1>;
516 clocks = <&tegra_car TEGRA124_CLK_SBC3>;
518 resets = <&tegra_car 46>;
520 dmas = <&apbdma 17>, <&apbdma 17>;
521 dma-names = "rx", "tx";
526 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
527 reg = <0x0 0x7000da00 0x0 0x200>;
528 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
529 #address-cells = <1>;
531 clocks = <&tegra_car TEGRA124_CLK_SBC4>;
533 resets = <&tegra_car 68>;
535 dmas = <&apbdma 18>, <&apbdma 18>;
536 dma-names = "rx", "tx";
541 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
542 reg = <0x0 0x7000dc00 0x0 0x200>;
543 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
544 #address-cells = <1>;
546 clocks = <&tegra_car TEGRA124_CLK_SBC5>;
548 resets = <&tegra_car 104>;
550 dmas = <&apbdma 27>, <&apbdma 27>;
551 dma-names = "rx", "tx";
556 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
557 reg = <0x0 0x7000de00 0x0 0x200>;
558 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
559 #address-cells = <1>;
561 clocks = <&tegra_car TEGRA124_CLK_SBC6>;
563 resets = <&tegra_car 105>;
565 dmas = <&apbdma 28>, <&apbdma 28>;
566 dma-names = "rx", "tx";
571 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
572 reg = <0x0 0x7000e000 0x0 0x100>;
573 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
574 clocks = <&tegra_car TEGRA124_CLK_RTC>;
578 compatible = "nvidia,tegra124-pmc";
579 reg = <0x0 0x7000e400 0x0 0x400>;
580 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
581 clock-names = "pclk", "clk32k_in";
585 compatible = "nvidia,tegra124-efuse";
586 reg = <0x0 0x7000f800 0x0 0x400>;
587 clocks = <&tegra_car TEGRA124_CLK_FUSE>;
588 clock-names = "fuse";
589 resets = <&tegra_car 39>;
590 reset-names = "fuse";
593 mc: memory-controller@0,70019000 {
594 compatible = "nvidia,tegra124-mc";
595 reg = <0x0 0x70019000 0x0 0x1000>;
596 clocks = <&tegra_car TEGRA124_CLK_MC>;
599 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
604 emc: emc@0,7001b000 {
605 compatible = "nvidia,tegra124-emc";
606 reg = <0x0 0x7001b000 0x0 0x1000>;
608 nvidia,memory-controller = <&mc>;
612 compatible = "nvidia,tegra124-ahci";
614 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
615 <0x0 0x70020000 0x0 0x7000>; /* SATA */
617 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
619 clocks = <&tegra_car TEGRA124_CLK_SATA>,
620 <&tegra_car TEGRA124_CLK_SATA_OOB>,
621 <&tegra_car TEGRA124_CLK_CML1>,
622 <&tegra_car TEGRA124_CLK_PLL_E>;
623 clock-names = "sata", "sata-oob", "cml1", "pll_e";
625 resets = <&tegra_car 124>,
628 reset-names = "sata", "sata-oob", "sata-cold";
630 phys = <&padctl TEGRA_XUSB_PADCTL_SATA>;
631 phy-names = "sata-phy";
637 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda";
638 reg = <0x0 0x70030000 0x0 0x10000>;
639 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
640 clocks = <&tegra_car TEGRA124_CLK_HDA>,
641 <&tegra_car TEGRA124_CLK_HDA2HDMI>,
642 <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
643 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
644 resets = <&tegra_car 125>, /* hda */
645 <&tegra_car 128>, /* hda2hdmi */
646 <&tegra_car 111>; /* hda2codec_2x */
647 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
651 padctl: padctl@0,7009f000 {
652 compatible = "nvidia,tegra124-xusb-padctl";
653 reg = <0x0 0x7009f000 0x0 0x1000>;
654 resets = <&tegra_car 142>;
655 reset-names = "padctl";
661 compatible = "nvidia,tegra124-sdhci";
662 reg = <0x0 0x700b0000 0x0 0x200>;
663 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
664 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
665 resets = <&tegra_car 14>;
666 reset-names = "sdhci";
671 compatible = "nvidia,tegra124-sdhci";
672 reg = <0x0 0x700b0200 0x0 0x200>;
673 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
674 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
675 resets = <&tegra_car 9>;
676 reset-names = "sdhci";
681 compatible = "nvidia,tegra124-sdhci";
682 reg = <0x0 0x700b0400 0x0 0x200>;
683 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
684 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
685 resets = <&tegra_car 69>;
686 reset-names = "sdhci";
691 compatible = "nvidia,tegra124-sdhci";
692 reg = <0x0 0x700b0600 0x0 0x200>;
693 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
694 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
695 resets = <&tegra_car 15>;
696 reset-names = "sdhci";
700 soctherm: thermal-sensor@0,700e2000 {
701 compatible = "nvidia,tegra124-soctherm";
702 reg = <0x0 0x700e2000 0x0 0x1000>;
703 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
704 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
705 <&tegra_car TEGRA124_CLK_SOC_THERM>;
706 clock-names = "tsensor", "soctherm";
707 resets = <&tegra_car 78>;
708 reset-names = "soctherm";
709 #thermal-sensor-cells = <1>;
712 dfll: clock@0,70110000 {
713 compatible = "nvidia,tegra124-dfll";
714 reg = <0 0x70110000 0 0x100>, /* DFLL control */
715 <0 0x70110000 0 0x100>, /* I2C output control */
716 <0 0x70110100 0 0x100>, /* Integrated I2C controller */
717 <0 0x70110200 0 0x100>; /* Look-up table RAM */
718 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
719 clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>,
720 <&tegra_car TEGRA124_CLK_DFLL_REF>,
721 <&tegra_car TEGRA124_CLK_I2C5>;
722 clock-names = "soc", "ref", "i2c";
723 resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
724 reset-names = "dvco";
726 clock-output-names = "dfllCPU_out";
727 nvidia,sample-rate = <12500>;
728 nvidia,droop-ctrl = <0x00000f00>;
729 nvidia,force-mode = <1>;
737 compatible = "nvidia,tegra124-ahub";
738 reg = <0x0 0x70300000 0x0 0x200>,
739 <0x0 0x70300800 0x0 0x800>,
740 <0x0 0x70300200 0x0 0x600>;
741 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
742 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
743 <&tegra_car TEGRA124_CLK_APBIF>;
744 clock-names = "d_audio", "apbif";
745 resets = <&tegra_car 106>, /* d_audio */
746 <&tegra_car 107>, /* apbif */
747 <&tegra_car 30>, /* i2s0 */
748 <&tegra_car 11>, /* i2s1 */
749 <&tegra_car 18>, /* i2s2 */
750 <&tegra_car 101>, /* i2s3 */
751 <&tegra_car 102>, /* i2s4 */
752 <&tegra_car 108>, /* dam0 */
753 <&tegra_car 109>, /* dam1 */
754 <&tegra_car 110>, /* dam2 */
755 <&tegra_car 10>, /* spdif */
756 <&tegra_car 153>, /* amx */
757 <&tegra_car 185>, /* amx1 */
758 <&tegra_car 154>, /* adx */
759 <&tegra_car 180>, /* adx1 */
760 <&tegra_car 186>, /* afc0 */
761 <&tegra_car 187>, /* afc1 */
762 <&tegra_car 188>, /* afc2 */
763 <&tegra_car 189>, /* afc3 */
764 <&tegra_car 190>, /* afc4 */
765 <&tegra_car 191>; /* afc5 */
766 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
767 "i2s3", "i2s4", "dam0", "dam1", "dam2",
768 "spdif", "amx", "amx1", "adx", "adx1",
769 "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
770 dmas = <&apbdma 1>, <&apbdma 1>,
771 <&apbdma 2>, <&apbdma 2>,
772 <&apbdma 3>, <&apbdma 3>,
773 <&apbdma 4>, <&apbdma 4>,
774 <&apbdma 6>, <&apbdma 6>,
775 <&apbdma 7>, <&apbdma 7>,
776 <&apbdma 12>, <&apbdma 12>,
777 <&apbdma 13>, <&apbdma 13>,
778 <&apbdma 14>, <&apbdma 14>,
779 <&apbdma 29>, <&apbdma 29>;
780 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
781 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
782 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
785 #address-cells = <2>;
788 tegra_i2s0: i2s@0,70301000 {
789 compatible = "nvidia,tegra124-i2s";
790 reg = <0x0 0x70301000 0x0 0x100>;
791 nvidia,ahub-cif-ids = <4 4>;
792 clocks = <&tegra_car TEGRA124_CLK_I2S0>;
793 resets = <&tegra_car 30>;
798 tegra_i2s1: i2s@0,70301100 {
799 compatible = "nvidia,tegra124-i2s";
800 reg = <0x0 0x70301100 0x0 0x100>;
801 nvidia,ahub-cif-ids = <5 5>;
802 clocks = <&tegra_car TEGRA124_CLK_I2S1>;
803 resets = <&tegra_car 11>;
808 tegra_i2s2: i2s@0,70301200 {
809 compatible = "nvidia,tegra124-i2s";
810 reg = <0x0 0x70301200 0x0 0x100>;
811 nvidia,ahub-cif-ids = <6 6>;
812 clocks = <&tegra_car TEGRA124_CLK_I2S2>;
813 resets = <&tegra_car 18>;
818 tegra_i2s3: i2s@0,70301300 {
819 compatible = "nvidia,tegra124-i2s";
820 reg = <0x0 0x70301300 0x0 0x100>;
821 nvidia,ahub-cif-ids = <7 7>;
822 clocks = <&tegra_car TEGRA124_CLK_I2S3>;
823 resets = <&tegra_car 101>;
828 tegra_i2s4: i2s@0,70301400 {
829 compatible = "nvidia,tegra124-i2s";
830 reg = <0x0 0x70301400 0x0 0x100>;
831 nvidia,ahub-cif-ids = <8 8>;
832 clocks = <&tegra_car TEGRA124_CLK_I2S4>;
833 resets = <&tegra_car 102>;
840 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
841 reg = <0x0 0x7d000000 0x0 0x4000>;
842 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
844 clocks = <&tegra_car TEGRA124_CLK_USBD>;
845 resets = <&tegra_car 22>;
847 nvidia,phy = <&phy1>;
851 phy1: usb-phy@0,7d000000 {
852 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
853 reg = <0x0 0x7d000000 0x0 0x4000>,
854 <0x0 0x7d000000 0x0 0x4000>;
856 clocks = <&tegra_car TEGRA124_CLK_USBD>,
857 <&tegra_car TEGRA124_CLK_PLL_U>,
858 <&tegra_car TEGRA124_CLK_USBD>;
859 clock-names = "reg", "pll_u", "utmi-pads";
860 resets = <&tegra_car 22>, <&tegra_car 22>;
861 reset-names = "usb", "utmi-pads";
862 nvidia,hssync-start-delay = <0>;
863 nvidia,idle-wait-delay = <17>;
864 nvidia,elastic-limit = <16>;
865 nvidia,term-range-adj = <6>;
866 nvidia,xcvr-setup = <9>;
867 nvidia,xcvr-lsfslew = <0>;
868 nvidia,xcvr-lsrslew = <3>;
869 nvidia,hssquelch-level = <2>;
870 nvidia,hsdiscon-level = <5>;
871 nvidia,xcvr-hsslew = <12>;
872 nvidia,has-utmi-pad-registers;
877 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
878 reg = <0x0 0x7d004000 0x0 0x4000>;
879 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
881 clocks = <&tegra_car TEGRA124_CLK_USB2>;
882 resets = <&tegra_car 58>;
884 nvidia,phy = <&phy2>;
888 phy2: usb-phy@0,7d004000 {
889 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
890 reg = <0x0 0x7d004000 0x0 0x4000>,
891 <0x0 0x7d000000 0x0 0x4000>;
893 clocks = <&tegra_car TEGRA124_CLK_USB2>,
894 <&tegra_car TEGRA124_CLK_PLL_U>,
895 <&tegra_car TEGRA124_CLK_USBD>;
896 clock-names = "reg", "pll_u", "utmi-pads";
897 resets = <&tegra_car 58>, <&tegra_car 22>;
898 reset-names = "usb", "utmi-pads";
899 nvidia,hssync-start-delay = <0>;
900 nvidia,idle-wait-delay = <17>;
901 nvidia,elastic-limit = <16>;
902 nvidia,term-range-adj = <6>;
903 nvidia,xcvr-setup = <9>;
904 nvidia,xcvr-lsfslew = <0>;
905 nvidia,xcvr-lsrslew = <3>;
906 nvidia,hssquelch-level = <2>;
907 nvidia,hsdiscon-level = <5>;
908 nvidia,xcvr-hsslew = <12>;
913 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
914 reg = <0x0 0x7d008000 0x0 0x4000>;
915 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
917 clocks = <&tegra_car TEGRA124_CLK_USB3>;
918 resets = <&tegra_car 59>;
920 nvidia,phy = <&phy3>;
924 phy3: usb-phy@0,7d008000 {
925 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
926 reg = <0x0 0x7d008000 0x0 0x4000>,
927 <0x0 0x7d000000 0x0 0x4000>;
929 clocks = <&tegra_car TEGRA124_CLK_USB3>,
930 <&tegra_car TEGRA124_CLK_PLL_U>,
931 <&tegra_car TEGRA124_CLK_USBD>;
932 clock-names = "reg", "pll_u", "utmi-pads";
933 resets = <&tegra_car 59>, <&tegra_car 22>;
934 reset-names = "usb", "utmi-pads";
935 nvidia,hssync-start-delay = <0>;
936 nvidia,idle-wait-delay = <17>;
937 nvidia,elastic-limit = <16>;
938 nvidia,term-range-adj = <6>;
939 nvidia,xcvr-setup = <9>;
940 nvidia,xcvr-lsfslew = <0>;
941 nvidia,xcvr-lsrslew = <3>;
942 nvidia,hssquelch-level = <2>;
943 nvidia,hsdiscon-level = <5>;
944 nvidia,xcvr-hsslew = <12>;
949 #address-cells = <1>;
954 compatible = "arm,cortex-a15";
957 clocks = <&tegra_car TEGRA124_CLK_CCLK_G>,
958 <&tegra_car TEGRA124_CLK_CCLK_LP>,
959 <&tegra_car TEGRA124_CLK_PLL_X>,
960 <&tegra_car TEGRA124_CLK_PLL_P>,
962 clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
963 /* FIXME: what's the actual transition time? */
964 clock-latency = <300000>;
969 compatible = "arm,cortex-a15";
975 compatible = "arm,cortex-a15";
981 compatible = "arm,cortex-a15";
987 compatible = "arm,cortex-a15-pmu";
988 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
989 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
990 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
991 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
992 interrupt-affinity = <&{/cpus/cpu@0}>,
1000 polling-delay-passive = <1000>;
1001 polling-delay = <1000>;
1004 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
1008 polling-delay-passive = <1000>;
1009 polling-delay = <1000>;
1012 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
1016 polling-delay-passive = <1000>;
1017 polling-delay = <1000>;
1020 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
1024 polling-delay-passive = <1000>;
1025 polling-delay = <1000>;
1028 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
1033 compatible = "arm,armv7-timer";
1034 interrupts = <GIC_PPI 13
1035 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1037 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1039 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1041 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1042 interrupt-parent = <&gic>;