arch/arm/boot/dts/tegra124.dtsi

   1 #include <dt-bindings/clock/tegra124-car.h>
   2 #include <dt-bindings/gpio/tegra-gpio.h>
   3 #include <dt-bindings/memory/tegra124-mc.h>
   4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   5 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/reset/tegra124-car.h>
   8 #include <dt-bindings/thermal/tegra124-soctherm.h>
   9
  10 #include "skeleton.dtsi"
  11
  12 / {
  13         compatible = "nvidia,tegra124";
  14         interrupt-parent = <&lic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         pcie-controller@0,01003000 {
  19                 compatible = "nvidia,tegra124-pcie";
  20                 device_type = "pci";
  21                 reg = <0x0 0x01003000 0x0 0x00000800   /* PADS registers */
  22                        0x0 0x01003800 0x0 0x00000800   /* AFI registers */
  23                        0x0 0x02000000 0x0 0x10000000>; /* configuration space */
  24                 reg-names = "pads", "afi", "cs";
  25                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
  26                              <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
  27                 interrupt-names = "intr", "msi";
  28
  29                 #interrupt-cells = <1>;
  30                 interrupt-map-mask = <0 0 0 0>;
  31                 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
  32
  33                 bus-range = <0x00 0xff>;
  34                 #address-cells = <3>;
  35                 #size-cells = <2>;
  36
  37                 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000   /* port 0 configuration space */
  38                           0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000   /* port 1 configuration space */
  39                           0x81000000 0 0x0        0x0 0x12000000 0 0x00010000   /* downstream I/O (64 KiB) */
  40                           0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000   /* non-prefetchable memory (208 MiB) */
  41                           0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
  42
  43                 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
  44                          <&tegra_car TEGRA124_CLK_AFI>,
  45                          <&tegra_car TEGRA124_CLK_PLL_E>,
  46                          <&tegra_car TEGRA124_CLK_CML0>;
  47                 clock-names = "pex", "afi", "pll_e", "cml";
  48                 resets = <&tegra_car 70>,
  49                          <&tegra_car 72>,
  50                          <&tegra_car 74>;
  51                 reset-names = "pex", "afi", "pcie_x";
  52                 status = "disabled";
  53
  54                 phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>;
  55                 phy-names = "pcie";
  56
  57                 pci@1,0 {
  58                         device_type = "pci";
  59                         assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
  60                         reg = <0x000800 0 0 0 0>;
  61                         status = "disabled";
  62
  63                         #address-cells = <3>;
  64                         #size-cells = <2>;
  65                         ranges;
  66
  67                         nvidia,num-lanes = <2>;
  68                 };
  69
  70                 pci@2,0 {
  71                         device_type = "pci";
  72                         assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
  73                         reg = <0x001000 0 0 0 0>;
  74                         status = "disabled";
  75
  76                         #address-cells = <3>;
  77                         #size-cells = <2>;
  78                         ranges;
  79
  80                         nvidia,num-lanes = <1>;
  81                 };
  82         };
  83
  84         host1x@0,50000000 {
  85                 compatible = "nvidia,tegra124-host1x", "simple-bus";
  86                 reg = <0x0 0x50000000 0x0 0x00034000>;
  87                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
  88                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
  89                 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
  90                 resets = <&tegra_car 28>;
  91                 reset-names = "host1x";
  92
  93                 #address-cells = <2>;
  94                 #size-cells = <2>;
  95
  96                 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
  97
  98                 dc@0,54200000 {
  99                         compatible = "nvidia,tegra124-dc";
 100                         reg = <0x0 0x54200000 0x0 0x00040000>;
 101                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 102                         clocks = <&tegra_car TEGRA124_CLK_DISP1>,
 103                                  <&tegra_car TEGRA124_CLK_PLL_P>;
 104                         clock-names = "dc", "parent";
 105                         resets = <&tegra_car 27>;
 106                         reset-names = "dc";
 107
 108                         iommus = <&mc TEGRA_SWGROUP_DC>;
 109
 110                         nvidia,head = <0>;
 111                 };
 112
 113                 dc@0,54240000 {
 114                         compatible = "nvidia,tegra124-dc";
 115                         reg = <0x0 0x54240000 0x0 0x00040000>;
 116                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 117                         clocks = <&tegra_car TEGRA124_CLK_DISP2>,
 118                                  <&tegra_car TEGRA124_CLK_PLL_P>;
 119                         clock-names = "dc", "parent";
 120                         resets = <&tegra_car 26>;
 121                         reset-names = "dc";
 122
 123                         iommus = <&mc TEGRA_SWGROUP_DCB>;
 124
 125                         nvidia,head = <1>;
 126                 };
 127
 128                 hdmi@0,54280000 {
 129                         compatible = "nvidia,tegra124-hdmi";
 130                         reg = <0x0 0x54280000 0x0 0x00040000>;
 131                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 132                         clocks = <&tegra_car TEGRA124_CLK_HDMI>,
 133                                  <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
 134                         clock-names = "hdmi", "parent";
 135                         resets = <&tegra_car 51>;
 136                         reset-names = "hdmi";
 137                         status = "disabled";
 138                 };
 139
 140                 sor@0,54540000 {
 141                         compatible = "nvidia,tegra124-sor";
 142                         reg = <0x0 0x54540000 0x0 0x00040000>;
 143                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 144                         clocks = <&tegra_car TEGRA124_CLK_SOR0>,
 145                                  <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
 146                                  <&tegra_car TEGRA124_CLK_PLL_DP>,
 147                                  <&tegra_car TEGRA124_CLK_CLK_M>;
 148                         clock-names = "sor", "parent", "dp", "safe";
 149                         resets = <&tegra_car 182>;
 150                         reset-names = "sor";
 151                         status = "disabled";
 152                 };
 153
 154                 dpaux: dpaux@0,545c0000 {
 155                         compatible = "nvidia,tegra124-dpaux";
 156                         reg = <0x0 0x545c0000 0x0 0x00040000>;
 157                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
 158                         clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
 159                                  <&tegra_car TEGRA124_CLK_PLL_DP>;
 160                         clock-names = "dpaux", "parent";
 161                         resets = <&tegra_car 181>;
 162                         reset-names = "dpaux";
 163                         status = "disabled";
 164                 };
 165         };
 166
 167         gic: interrupt-controller@0,50041000 {
 168                 compatible = "arm,cortex-a15-gic";
 169                 #interrupt-cells = <3>;
 170                 interrupt-controller;
 171                 reg = <0x0 0x50041000 0x0 0x1000>,
 172                       <0x0 0x50042000 0x0 0x1000>,
 173                       <0x0 0x50044000 0x0 0x2000>,
 174                       <0x0 0x50046000 0x0 0x2000>;
 175                 interrupts = <GIC_PPI 9
 176                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 177                 interrupt-parent = <&gic>;
 178         };
 179
 180         gpu@0,57000000 {
 181                 compatible = "nvidia,gk20a";
 182                 reg = <0x0 0x57000000 0x0 0x01000000>,
 183                       <0x0 0x58000000 0x0 0x01000000>;
 184                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 185                              <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
 186                 interrupt-names = "stall", "nonstall";
 187                 clocks = <&tegra_car TEGRA124_CLK_GPU>,
 188                          <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
 189                 clock-names = "gpu", "pwr";
 190                 resets = <&tegra_car 184>;
 191                 reset-names = "gpu";
 192                 status = "disabled";
 193         };
 194
 195         lic: interrupt-controller@60004000 {
 196                 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr";
 197                 reg = <0x0 0x60004000 0x0 0x100>,
 198                       <0x0 0x60004100 0x0 0x100>,
 199                       <0x0 0x60004200 0x0 0x100>,
 200                       <0x0 0x60004300 0x0 0x100>,
 201                       <0x0 0x60004400 0x0 0x100>;
 202                 interrupt-controller;
 203                 #interrupt-cells = <3>;
 204                 interrupt-parent = <&gic>;
 205         };
 206
 207         timer@0,60005000 {
 208                 compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
 209                 reg = <0x0 0x60005000 0x0 0x400>;
 210                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 211                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 212                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 213                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 214                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 215                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 216                 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
 217         };
 218
 219         tegra_car: clock@0,60006000 {
 220                 compatible = "nvidia,tegra124-car";
 221                 reg = <0x0 0x60006000 0x0 0x1000>;
 222                 #clock-cells = <1>;
 223                 #reset-cells = <1>;
 224                 nvidia,external-memory-controller = <&emc>;
 225         };
 226
 227         flow-controller@0,60007000 {
 228                 compatible = "nvidia,tegra124-flowctrl";
 229                 reg = <0x0 0x60007000 0x0 0x1000>;
 230         };
 231
 232         actmon@0,6000c800 {
 233                 compatible = "nvidia,tegra124-actmon";
 234                 reg = <0x0 0x6000c800 0x0 0x400>;
 235                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 236                 clocks = <&tegra_car TEGRA124_CLK_ACTMON>,
 237                          <&tegra_car TEGRA124_CLK_EMC>;
 238                 clock-names = "actmon", "emc";
 239                 resets = <&tegra_car 119>;
 240                 reset-names = "actmon";
 241         };
 242
 243         gpio: gpio@0,6000d000 {
 244                 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
 245                 reg = <0x0 0x6000d000 0x0 0x1000>;
 246                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 247                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 248                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 249                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 250                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 251                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 252                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 253                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 254                 #gpio-cells = <2>;
 255                 gpio-controller;
 256                 #interrupt-cells = <2>;
 257                 interrupt-controller;
 258         };
 259
 260         apbdma: dma@0,60020000 {
 261                 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
 262                 reg = <0x0 0x60020000 0x0 0x1400>;
 263                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 264                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 265                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 266                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 267                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 268                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 269                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 270                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 271                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 272                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 273                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 274                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 275                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 276                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 277                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 278                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 279                              <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 280                              <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 281                              <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 282                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 283                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 284                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 285                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 286                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 287                              <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 288                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 289                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 290                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 291                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 292                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 293                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 294                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 295                 clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
 296                 resets = <&tegra_car 34>;
 297                 reset-names = "dma";
 298                 #dma-cells = <1>;
 299         };
 300
 301         apbmisc@0,70000800 {
 302                 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
 303                 reg = <0x0 0x70000800 0x0 0x64>,   /* Chip revision */
 304                       <0x0 0x7000e864 0x0 0x04>;   /* Strapping options */
 305         };
 306
 307         pinmux: pinmux@0,70000868 {
 308                 compatible = "nvidia,tegra124-pinmux";
 309                 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
 310                       <0x0 0x70003000 0x0 0x434>, /* Mux registers */
 311                       <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
 312         };
 313
 314         /*
 315          * There are two serial driver i.e. 8250 based simple serial
 316          * driver and APB DMA based serial driver for higher baudrate
 317          * and performace. To enable the 8250 based driver, the compatible
 318          * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
 319          * the APB DMA based serial driver, the comptible is
 320          * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
 321          */
 322         uarta: serial@0,70006000 {
 323                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 324                 reg = <0x0 0x70006000 0x0 0x40>;
 325                 reg-shift = <2>;
 326                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 327                 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
 328                 resets = <&tegra_car 6>;
 329                 reset-names = "serial";
 330                 dmas = <&apbdma 8>, <&apbdma 8>;
 331                 dma-names = "rx", "tx";
 332                 status = "disabled";
 333         };
 334
 335         uartb: serial@0,70006040 {
 336                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 337                 reg = <0x0 0x70006040 0x0 0x40>;
 338                 reg-shift = <2>;
 339                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 340                 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
 341                 resets = <&tegra_car 7>;
 342                 reset-names = "serial";
 343                 dmas = <&apbdma 9>, <&apbdma 9>;
 344                 dma-names = "rx", "tx";
 345                 status = "disabled";
 346         };
 347
 348         uartc: serial@0,70006200 {
 349                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 350                 reg = <0x0 0x70006200 0x0 0x40>;
 351                 reg-shift = <2>;
 352                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 353                 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
 354                 resets = <&tegra_car 55>;
 355                 reset-names = "serial";
 356                 dmas = <&apbdma 10>, <&apbdma 10>;
 357                 dma-names = "rx", "tx";
 358                 status = "disabled";
 359         };
 360
 361         uartd: serial@0,70006300 {
 362                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 363                 reg = <0x0 0x70006300 0x0 0x40>;
 364                 reg-shift = <2>;
 365                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 366                 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
 367                 resets = <&tegra_car 65>;
 368                 reset-names = "serial";
 369                 dmas = <&apbdma 19>, <&apbdma 19>;
 370                 dma-names = "rx", "tx";
 371                 status = "disabled";
 372         };
 373
 374         pwm: pwm@0,7000a000 {
 375                 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
 376                 reg = <0x0 0x7000a000 0x0 0x100>;
 377                 #pwm-cells = <2>;
 378                 clocks = <&tegra_car TEGRA124_CLK_PWM>;
 379                 resets = <&tegra_car 17>;
 380                 reset-names = "pwm";
 381                 status = "disabled";
 382         };
 383
 384         i2c@0,7000c000 {
 385                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 386                 reg = <0x0 0x7000c000 0x0 0x100>;
 387                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 388                 #address-cells = <1>;
 389                 #size-cells = <0>;
 390                 clocks = <&tegra_car TEGRA124_CLK_I2C1>;
 391                 clock-names = "div-clk";
 392                 resets = <&tegra_car 12>;
 393                 reset-names = "i2c";
 394                 dmas = <&apbdma 21>, <&apbdma 21>;
 395                 dma-names = "rx", "tx";
 396                 status = "disabled";
 397         };
 398
 399         i2c@0,7000c400 {
 400                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 401                 reg = <0x0 0x7000c400 0x0 0x100>;
 402                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 403                 #address-cells = <1>;
 404                 #size-cells = <0>;
 405                 clocks = <&tegra_car TEGRA124_CLK_I2C2>;
 406                 clock-names = "div-clk";
 407                 resets = <&tegra_car 54>;
 408                 reset-names = "i2c";
 409                 dmas = <&apbdma 22>, <&apbdma 22>;
 410                 dma-names = "rx", "tx";
 411                 status = "disabled";
 412         };
 413
 414         i2c@0,7000c500 {
 415                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 416                 reg = <0x0 0x7000c500 0x0 0x100>;
 417                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 418                 #address-cells = <1>;
 419                 #size-cells = <0>;
 420                 clocks = <&tegra_car TEGRA124_CLK_I2C3>;
 421                 clock-names = "div-clk";
 422                 resets = <&tegra_car 67>;
 423                 reset-names = "i2c";
 424                 dmas = <&apbdma 23>, <&apbdma 23>;
 425                 dma-names = "rx", "tx";
 426                 status = "disabled";
 427         };
 428
 429         i2c@0,7000c700 {
 430                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 431                 reg = <0x0 0x7000c700 0x0 0x100>;
 432                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 433                 #address-cells = <1>;
 434                 #size-cells = <0>;
 435                 clocks = <&tegra_car TEGRA124_CLK_I2C4>;
 436                 clock-names = "div-clk";
 437                 resets = <&tegra_car 103>;
 438                 reset-names = "i2c";
 439                 dmas = <&apbdma 26>, <&apbdma 26>;
 440                 dma-names = "rx", "tx";
 441                 status = "disabled";
 442         };
 443
 444         i2c@0,7000d000 {
 445                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 446                 reg = <0x0 0x7000d000 0x0 0x100>;
 447                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 448                 #address-cells = <1>;
 449                 #size-cells = <0>;
 450                 clocks = <&tegra_car TEGRA124_CLK_I2C5>;
 451                 clock-names = "div-clk";
 452                 resets = <&tegra_car 47>;
 453                 reset-names = "i2c";
 454                 dmas = <&apbdma 24>, <&apbdma 24>;
 455                 dma-names = "rx", "tx";
 456                 status = "disabled";
 457         };
 458
 459         i2c@0,7000d100 {
 460                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 461                 reg = <0x0 0x7000d100 0x0 0x100>;
 462                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 463                 #address-cells = <1>;
 464                 #size-cells = <0>;
 465                 clocks = <&tegra_car TEGRA124_CLK_I2C6>;
 466                 clock-names = "div-clk";
 467                 resets = <&tegra_car 166>;
 468                 reset-names = "i2c";
 469                 dmas = <&apbdma 30>, <&apbdma 30>;
 470                 dma-names = "rx", "tx";
 471                 status = "disabled";
 472         };
 473
 474         spi@0,7000d400 {
 475                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 476                 reg = <0x0 0x7000d400 0x0 0x200>;
 477                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 478                 #address-cells = <1>;
 479                 #size-cells = <0>;
 480                 clocks = <&tegra_car TEGRA124_CLK_SBC1>;
 481                 clock-names = "spi";
 482                 resets = <&tegra_car 41>;
 483                 reset-names = "spi";
 484                 dmas = <&apbdma 15>, <&apbdma 15>;
 485                 dma-names = "rx", "tx";
 486                 status = "disabled";
 487         };
 488
 489         spi@0,7000d600 {
 490                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 491                 reg = <0x0 0x7000d600 0x0 0x200>;
 492                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 493                 #address-cells = <1>;
 494                 #size-cells = <0>;
 495                 clocks = <&tegra_car TEGRA124_CLK_SBC2>;
 496                 clock-names = "spi";
 497                 resets = <&tegra_car 44>;
 498                 reset-names = "spi";
 499                 dmas = <&apbdma 16>, <&apbdma 16>;
 500                 dma-names = "rx", "tx";
 501                 status = "disabled";
 502         };
 503
 504         spi@0,7000d800 {
 505                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 506                 reg = <0x0 0x7000d800 0x0 0x200>;
 507                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 508                 #address-cells = <1>;
 509                 #size-cells = <0>;
 510                 clocks = <&tegra_car TEGRA124_CLK_SBC3>;
 511                 clock-names = "spi";
 512                 resets = <&tegra_car 46>;
 513                 reset-names = "spi";
 514                 dmas = <&apbdma 17>, <&apbdma 17>;
 515                 dma-names = "rx", "tx";
 516                 status = "disabled";
 517         };
 518
 519         spi@0,7000da00 {
 520                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 521                 reg = <0x0 0x7000da00 0x0 0x200>;
 522                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 523                 #address-cells = <1>;
 524                 #size-cells = <0>;
 525                 clocks = <&tegra_car TEGRA124_CLK_SBC4>;
 526                 clock-names = "spi";
 527                 resets = <&tegra_car 68>;
 528                 reset-names = "spi";
 529                 dmas = <&apbdma 18>, <&apbdma 18>;
 530                 dma-names = "rx", "tx";
 531                 status = "disabled";
 532         };
 533
 534         spi@0,7000dc00 {
 535                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 536                 reg = <0x0 0x7000dc00 0x0 0x200>;
 537                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 538                 #address-cells = <1>;
 539                 #size-cells = <0>;
 540                 clocks = <&tegra_car TEGRA124_CLK_SBC5>;
 541                 clock-names = "spi";
 542                 resets = <&tegra_car 104>;
 543                 reset-names = "spi";
 544                 dmas = <&apbdma 27>, <&apbdma 27>;
 545                 dma-names = "rx", "tx";
 546                 status = "disabled";
 547         };
 548
 549         spi@0,7000de00 {
 550                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 551                 reg = <0x0 0x7000de00 0x0 0x200>;
 552                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 553                 #address-cells = <1>;
 554                 #size-cells = <0>;
 555                 clocks = <&tegra_car TEGRA124_CLK_SBC6>;
 556                 clock-names = "spi";
 557                 resets = <&tegra_car 105>;
 558                 reset-names = "spi";
 559                 dmas = <&apbdma 28>, <&apbdma 28>;
 560                 dma-names = "rx", "tx";
 561                 status = "disabled";
 562         };
 563
 564         rtc@0,7000e000 {
 565                 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
 566                 reg = <0x0 0x7000e000 0x0 0x100>;
 567                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 568                 clocks = <&tegra_car TEGRA124_CLK_RTC>;
 569         };
 570
 571         pmc@0,7000e400 {
 572                 compatible = "nvidia,tegra124-pmc";
 573                 reg = <0x0 0x7000e400 0x0 0x400>;
 574                 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
 575                 clock-names = "pclk", "clk32k_in";
 576         };
 577
 578         fuse@0,7000f800 {
 579                 compatible = "nvidia,tegra124-efuse";
 580                 reg = <0x0 0x7000f800 0x0 0x400>;
 581                 clocks = <&tegra_car TEGRA124_CLK_FUSE>;
 582                 clock-names = "fuse";
 583                 resets = <&tegra_car 39>;
 584                 reset-names = "fuse";
 585         };
 586
 587         mc: memory-controller@0,70019000 {
 588                 compatible = "nvidia,tegra124-mc";
 589                 reg = <0x0 0x70019000 0x0 0x1000>;
 590                 clocks = <&tegra_car TEGRA124_CLK_MC>;
 591                 clock-names = "mc";
 592
 593                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 594
 595                 #iommu-cells = <1>;
 596         };
 597
 598         emc: emc@0,7001b000 {
 599                 compatible = "nvidia,tegra124-emc";
 600                 reg = <0x0 0x7001b000 0x0 0x1000>;
 601
 602                 nvidia,memory-controller = <&mc>;
 603         };
 604
 605         sata@0,70020000 {
 606                 compatible = "nvidia,tegra124-ahci";
 607
 608                 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
 609                         <0x0 0x70020000 0x0 0x7000>; /* SATA */
 610
 611                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 612
 613                 clocks = <&tegra_car TEGRA124_CLK_SATA>,
 614                         <&tegra_car TEGRA124_CLK_SATA_OOB>,
 615                         <&tegra_car TEGRA124_CLK_CML1>,
 616                         <&tegra_car TEGRA124_CLK_PLL_E>;
 617                 clock-names = "sata", "sata-oob", "cml1", "pll_e";
 618
 619                 resets = <&tegra_car 124>,
 620                         <&tegra_car 123>,
 621                         <&tegra_car 129>;
 622                 reset-names = "sata", "sata-oob", "sata-cold";
 623
 624                 phys = <&padctl TEGRA_XUSB_PADCTL_SATA>;
 625                 phy-names = "sata-phy";
 626
 627                 status = "disabled";
 628         };
 629
 630         hda@0,70030000 {
 631                 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda";
 632                 reg = <0x0 0x70030000 0x0 0x10000>;
 633                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 634                 clocks = <&tegra_car TEGRA124_CLK_HDA>,
 635                          <&tegra_car TEGRA124_CLK_HDA2HDMI>,
 636                          <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
 637                 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
 638                 resets = <&tegra_car 125>, /* hda */
 639                          <&tegra_car 128>, /* hda2hdmi */
 640                          <&tegra_car 111>; /* hda2codec_2x */
 641                 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
 642                 status = "disabled";
 643         };
 644
 645         padctl: padctl@0,7009f000 {
 646                 compatible = "nvidia,tegra124-xusb-padctl";
 647                 reg = <0x0 0x7009f000 0x0 0x1000>;
 648                 resets = <&tegra_car 142>;
 649                 reset-names = "padctl";
 650
 651                 #phy-cells = <1>;
 652         };
 653
 654         sdhci@0,700b0000 {
 655                 compatible = "nvidia,tegra124-sdhci";
 656                 reg = <0x0 0x700b0000 0x0 0x200>;
 657                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 658                 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
 659                 resets = <&tegra_car 14>;
 660                 reset-names = "sdhci";
 661                 status = "disabled";
 662         };
 663
 664         sdhci@0,700b0200 {
 665                 compatible = "nvidia,tegra124-sdhci";
 666                 reg = <0x0 0x700b0200 0x0 0x200>;
 667                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 668                 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
 669                 resets = <&tegra_car 9>;
 670                 reset-names = "sdhci";
 671                 status = "disabled";
 672         };
 673
 674         sdhci@0,700b0400 {
 675                 compatible = "nvidia,tegra124-sdhci";
 676                 reg = <0x0 0x700b0400 0x0 0x200>;
 677                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 678                 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
 679                 resets = <&tegra_car 69>;
 680                 reset-names = "sdhci";
 681                 status = "disabled";
 682         };
 683
 684         sdhci@0,700b0600 {
 685                 compatible = "nvidia,tegra124-sdhci";
 686                 reg = <0x0 0x700b0600 0x0 0x200>;
 687                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 688                 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
 689                 resets = <&tegra_car 15>;
 690                 reset-names = "sdhci";
 691                 status = "disabled";
 692         };
 693
 694         soctherm: thermal-sensor@0,700e2000 {
 695                 compatible = "nvidia,tegra124-soctherm";
 696                 reg = <0x0 0x700e2000 0x0 0x1000>;
 697                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 698                 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
 699                         <&tegra_car TEGRA124_CLK_SOC_THERM>;
 700                 clock-names = "tsensor", "soctherm";
 701                 resets = <&tegra_car 78>;
 702                 reset-names = "soctherm";
 703                 #thermal-sensor-cells = <1>;
 704         };
 705
 706         dfll: clock@0,70110000 {
 707                 compatible = "nvidia,tegra124-dfll";
 708                 reg = <0 0x70110000 0 0x100>, /* DFLL control */
 709                       <0 0x70110000 0 0x100>, /* I2C output control */
 710                       <0 0x70110100 0 0x100>, /* Integrated I2C controller */
 711                       <0 0x70110200 0 0x100>; /* Look-up table RAM */
 712                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 713                 clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>,
 714                          <&tegra_car TEGRA124_CLK_DFLL_REF>,
 715                          <&tegra_car TEGRA124_CLK_I2C5>;
 716                 clock-names = "soc", "ref", "i2c";
 717                 resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
 718                 reset-names = "dvco";
 719                 #clock-cells = <0>;
 720                 clock-output-names = "dfllCPU_out";
 721                 nvidia,sample-rate = <12500>;
 722                 nvidia,droop-ctrl = <0x00000f00>;
 723                 nvidia,force-mode = <1>;
 724                 nvidia,cf = <10>;
 725                 nvidia,ci = <0>;
 726                 nvidia,cg = <2>;
 727                 status = "disabled";
 728         };
 729
 730         ahub@0,70300000 {
 731                 compatible = "nvidia,tegra124-ahub";
 732                 reg = <0x0 0x70300000 0x0 0x200>,
 733                       <0x0 0x70300800 0x0 0x800>,
 734                       <0x0 0x70300200 0x0 0x600>;
 735                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 736                 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
 737                          <&tegra_car TEGRA124_CLK_APBIF>;
 738                 clock-names = "d_audio", "apbif";
 739                 resets = <&tegra_car 106>, /* d_audio */
 740                          <&tegra_car 107>, /* apbif */
 741                          <&tegra_car 30>,  /* i2s0 */
 742                          <&tegra_car 11>,  /* i2s1 */
 743                          <&tegra_car 18>,  /* i2s2 */
 744                          <&tegra_car 101>, /* i2s3 */
 745                          <&tegra_car 102>, /* i2s4 */
 746                          <&tegra_car 108>, /* dam0 */
 747                          <&tegra_car 109>, /* dam1 */
 748                          <&tegra_car 110>, /* dam2 */
 749                          <&tegra_car 10>,  /* spdif */
 750                          <&tegra_car 153>, /* amx */
 751                          <&tegra_car 185>, /* amx1 */
 752                          <&tegra_car 154>, /* adx */
 753                          <&tegra_car 180>, /* adx1 */
 754                          <&tegra_car 186>, /* afc0 */
 755                          <&tegra_car 187>, /* afc1 */
 756                          <&tegra_car 188>, /* afc2 */
 757                          <&tegra_car 189>, /* afc3 */
 758                          <&tegra_car 190>, /* afc4 */
 759                          <&tegra_car 191>; /* afc5 */
 760                 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 761                               "i2s3", "i2s4", "dam0", "dam1", "dam2",
 762                               "spdif", "amx", "amx1", "adx", "adx1",
 763                               "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
 764                 dmas = <&apbdma 1>, <&apbdma 1>,
 765                        <&apbdma 2>, <&apbdma 2>,
 766                        <&apbdma 3>, <&apbdma 3>,
 767                        <&apbdma 4>, <&apbdma 4>,
 768                        <&apbdma 6>, <&apbdma 6>,
 769                        <&apbdma 7>, <&apbdma 7>,
 770                        <&apbdma 12>, <&apbdma 12>,
 771                        <&apbdma 13>, <&apbdma 13>,
 772                        <&apbdma 14>, <&apbdma 14>,
 773                        <&apbdma 29>, <&apbdma 29>;
 774                 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
 775                             "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
 776                             "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
 777                             "rx9", "tx9";
 778                 ranges;
 779                 #address-cells = <2>;
 780                 #size-cells = <2>;
 781
 782                 tegra_i2s0: i2s@0,70301000 {
 783                         compatible = "nvidia,tegra124-i2s";
 784                         reg = <0x0 0x70301000 0x0 0x100>;
 785                         nvidia,ahub-cif-ids = <4 4>;
 786                         clocks = <&tegra_car TEGRA124_CLK_I2S0>;
 787                         resets = <&tegra_car 30>;
 788                         reset-names = "i2s";
 789                         status = "disabled";
 790                 };
 791
 792                 tegra_i2s1: i2s@0,70301100 {
 793                         compatible = "nvidia,tegra124-i2s";
 794                         reg = <0x0 0x70301100 0x0 0x100>;
 795                         nvidia,ahub-cif-ids = <5 5>;
 796                         clocks = <&tegra_car TEGRA124_CLK_I2S1>;
 797                         resets = <&tegra_car 11>;
 798                         reset-names = "i2s";
 799                         status = "disabled";
 800                 };
 801
 802                 tegra_i2s2: i2s@0,70301200 {
 803                         compatible = "nvidia,tegra124-i2s";
 804                         reg = <0x0 0x70301200 0x0 0x100>;
 805                         nvidia,ahub-cif-ids = <6 6>;
 806                         clocks = <&tegra_car TEGRA124_CLK_I2S2>;
 807                         resets = <&tegra_car 18>;
 808                         reset-names = "i2s";
 809                         status = "disabled";
 810                 };
 811
 812                 tegra_i2s3: i2s@0,70301300 {
 813                         compatible = "nvidia,tegra124-i2s";
 814                         reg = <0x0 0x70301300 0x0 0x100>;
 815                         nvidia,ahub-cif-ids = <7 7>;
 816                         clocks = <&tegra_car TEGRA124_CLK_I2S3>;
 817                         resets = <&tegra_car 101>;
 818                         reset-names = "i2s";
 819                         status = "disabled";
 820                 };
 821
 822                 tegra_i2s4: i2s@0,70301400 {
 823                         compatible = "nvidia,tegra124-i2s";
 824                         reg = <0x0 0x70301400 0x0 0x100>;
 825                         nvidia,ahub-cif-ids = <8 8>;
 826                         clocks = <&tegra_car TEGRA124_CLK_I2S4>;
 827                         resets = <&tegra_car 102>;
 828                         reset-names = "i2s";
 829                         status = "disabled";
 830                 };
 831         };
 832
 833         usb@0,7d000000 {
 834                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
 835                 reg = <0x0 0x7d000000 0x0 0x4000>;
 836                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 837                 phy_type = "utmi";
 838                 clocks = <&tegra_car TEGRA124_CLK_USBD>;
 839                 resets = <&tegra_car 22>;
 840                 reset-names = "usb";
 841                 nvidia,phy = <&phy1>;
 842                 status = "disabled";
 843         };
 844
 845         phy1: usb-phy@0,7d000000 {
 846                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
 847                 reg = <0x0 0x7d000000 0x0 0x4000>,
 848                       <0x0 0x7d000000 0x0 0x4000>;
 849                 phy_type = "utmi";
 850                 clocks = <&tegra_car TEGRA124_CLK_USBD>,
 851                          <&tegra_car TEGRA124_CLK_PLL_U>,
 852                          <&tegra_car TEGRA124_CLK_USBD>;
 853                 clock-names = "reg", "pll_u", "utmi-pads";
 854                 resets = <&tegra_car 22>, <&tegra_car 22>;
 855                 reset-names = "usb", "utmi-pads";
 856                 nvidia,hssync-start-delay = <0>;
 857                 nvidia,idle-wait-delay = <17>;
 858                 nvidia,elastic-limit = <16>;
 859                 nvidia,term-range-adj = <6>;
 860                 nvidia,xcvr-setup = <9>;
 861                 nvidia,xcvr-lsfslew = <0>;
 862                 nvidia,xcvr-lsrslew = <3>;
 863                 nvidia,hssquelch-level = <2>;
 864                 nvidia,hsdiscon-level = <5>;
 865                 nvidia,xcvr-hsslew = <12>;
 866                 nvidia,has-utmi-pad-registers;
 867                 status = "disabled";
 868         };
 869
 870         usb@0,7d004000 {
 871                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
 872                 reg = <0x0 0x7d004000 0x0 0x4000>;
 873                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 874                 phy_type = "utmi";
 875                 clocks = <&tegra_car TEGRA124_CLK_USB2>;
 876                 resets = <&tegra_car 58>;
 877                 reset-names = "usb";
 878                 nvidia,phy = <&phy2>;
 879                 status = "disabled";
 880         };
 881
 882         phy2: usb-phy@0,7d004000 {
 883                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
 884                 reg = <0x0 0x7d004000 0x0 0x4000>,
 885                       <0x0 0x7d000000 0x0 0x4000>;
 886                 phy_type = "utmi";
 887                 clocks = <&tegra_car TEGRA124_CLK_USB2>,
 888                          <&tegra_car TEGRA124_CLK_PLL_U>,
 889                          <&tegra_car TEGRA124_CLK_USBD>;
 890                 clock-names = "reg", "pll_u", "utmi-pads";
 891                 resets = <&tegra_car 58>, <&tegra_car 22>;
 892                 reset-names = "usb", "utmi-pads";
 893                 nvidia,hssync-start-delay = <0>;
 894                 nvidia,idle-wait-delay = <17>;
 895                 nvidia,elastic-limit = <16>;
 896                 nvidia,term-range-adj = <6>;
 897                 nvidia,xcvr-setup = <9>;
 898                 nvidia,xcvr-lsfslew = <0>;
 899                 nvidia,xcvr-lsrslew = <3>;
 900                 nvidia,hssquelch-level = <2>;
 901                 nvidia,hsdiscon-level = <5>;
 902                 nvidia,xcvr-hsslew = <12>;
 903                 status = "disabled";
 904         };
 905
 906         usb@0,7d008000 {
 907                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
 908                 reg = <0x0 0x7d008000 0x0 0x4000>;
 909                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 910                 phy_type = "utmi";
 911                 clocks = <&tegra_car TEGRA124_CLK_USB3>;
 912                 resets = <&tegra_car 59>;
 913                 reset-names = "usb";
 914                 nvidia,phy = <&phy3>;
 915                 status = "disabled";
 916         };
 917
 918         phy3: usb-phy@0,7d008000 {
 919                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
 920                 reg = <0x0 0x7d008000 0x0 0x4000>,
 921                       <0x0 0x7d000000 0x0 0x4000>;
 922                 phy_type = "utmi";
 923                 clocks = <&tegra_car TEGRA124_CLK_USB3>,
 924                          <&tegra_car TEGRA124_CLK_PLL_U>,
 925                          <&tegra_car TEGRA124_CLK_USBD>;
 926                 clock-names = "reg", "pll_u", "utmi-pads";
 927                 resets = <&tegra_car 59>, <&tegra_car 22>;
 928                 reset-names = "usb", "utmi-pads";
 929                 nvidia,hssync-start-delay = <0>;
 930                 nvidia,idle-wait-delay = <17>;
 931                 nvidia,elastic-limit = <16>;
 932                 nvidia,term-range-adj = <6>;
 933                 nvidia,xcvr-setup = <9>;
 934                 nvidia,xcvr-lsfslew = <0>;
 935                 nvidia,xcvr-lsrslew = <3>;
 936                 nvidia,hssquelch-level = <2>;
 937                 nvidia,hsdiscon-level = <5>;
 938                 nvidia,xcvr-hsslew = <12>;
 939                 status = "disabled";
 940         };
 941
 942         cpus {
 943                 #address-cells = <1>;
 944                 #size-cells = <0>;
 945
 946                 cpu@0 {
 947                         device_type = "cpu";
 948                         compatible = "arm,cortex-a15";
 949                         reg = <0>;
 950                 };
 951
 952                 cpu@1 {
 953                         device_type = "cpu";
 954                         compatible = "arm,cortex-a15";
 955                         reg = <1>;
 956                 };
 957
 958                 cpu@2 {
 959                         device_type = "cpu";
 960                         compatible = "arm,cortex-a15";
 961                         reg = <2>;
 962                 };
 963
 964                 cpu@3 {
 965                         device_type = "cpu";
 966                         compatible = "arm,cortex-a15";
 967                         reg = <3>;
 968                 };
 969         };
 970
 971         thermal-zones {
 972                 cpu {
 973                         polling-delay-passive = <1000>;
 974                         polling-delay = <1000>;
 975
 976                         thermal-sensors =
 977                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
 978                 };
 979
 980                 mem {
 981                         polling-delay-passive = <1000>;
 982                         polling-delay = <1000>;
 983
 984                         thermal-sensors =
 985                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
 986                 };
 987
 988                 gpu {
 989                         polling-delay-passive = <1000>;
 990                         polling-delay = <1000>;
 991
 992                         thermal-sensors =
 993                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
 994                 };
 995
 996                 pllx {
 997                         polling-delay-passive = <1000>;
 998                         polling-delay = <1000>;
 999
1000                         thermal-sensors =
1001                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
1002                 };
1003         };
1004
1005         timer {
1006                 compatible = "arm,armv7-timer";
1007                 interrupts = <GIC_PPI 13
1008                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1009                              <GIC_PPI 14
1010                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1011                              <GIC_PPI 11
1012                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1013                              <GIC_PPI 10
1014                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1015                 interrupt-parent = <&gic>;
1016         };
1017 };