1 #include <dt-bindings/clock/tegra20-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include "skeleton.dtsi"
8 compatible = "nvidia,tegra20";
9 interrupt-parent = <&intc>;
20 compatible = "nvidia,tegra20-host1x", "simple-bus";
21 reg = <0x50000000 0x00024000>;
22 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
23 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
24 clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
29 ranges = <0x54000000 0x54000000 0x04000000>;
32 compatible = "nvidia,tegra20-mpe";
33 reg = <0x54040000 0x00040000>;
34 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
35 clocks = <&tegra_car TEGRA20_CLK_MPE>;
39 compatible = "nvidia,tegra20-vi";
40 reg = <0x54080000 0x00040000>;
41 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
42 clocks = <&tegra_car TEGRA20_CLK_VI>;
46 compatible = "nvidia,tegra20-epp";
47 reg = <0x540c0000 0x00040000>;
48 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
49 clocks = <&tegra_car TEGRA20_CLK_EPP>;
53 compatible = "nvidia,tegra20-isp";
54 reg = <0x54100000 0x00040000>;
55 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
56 clocks = <&tegra_car TEGRA20_CLK_ISP>;
60 compatible = "nvidia,tegra20-gr2d";
61 reg = <0x54140000 0x00040000>;
62 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
63 clocks = <&tegra_car TEGRA20_CLK_GR2D>;
67 compatible = "nvidia,tegra20-gr3d";
68 reg = <0x54180000 0x00040000>;
69 clocks = <&tegra_car TEGRA20_CLK_GR3D>;
73 compatible = "nvidia,tegra20-dc";
74 reg = <0x54200000 0x00040000>;
75 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
76 clocks = <&tegra_car TEGRA20_CLK_DISP1>,
77 <&tegra_car TEGRA20_CLK_PLL_P>;
78 clock-names = "disp1", "parent";
86 compatible = "nvidia,tegra20-dc";
87 reg = <0x54240000 0x00040000>;
88 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
89 clocks = <&tegra_car TEGRA20_CLK_DISP2>,
90 <&tegra_car TEGRA20_CLK_PLL_P>;
91 clock-names = "disp2", "parent";
99 compatible = "nvidia,tegra20-hdmi";
100 reg = <0x54280000 0x00040000>;
101 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
102 clocks = <&tegra_car TEGRA20_CLK_HDMI>,
103 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
104 clock-names = "hdmi", "parent";
109 compatible = "nvidia,tegra20-tvo";
110 reg = <0x542c0000 0x00040000>;
111 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
112 clocks = <&tegra_car TEGRA20_CLK_TVO>;
117 compatible = "nvidia,tegra20-dsi";
118 reg = <0x54300000 0x00040000>;
119 clocks = <&tegra_car TEGRA20_CLK_DSI>;
125 compatible = "arm,cortex-a9-twd-timer";
126 reg = <0x50040600 0x20>;
127 interrupts = <GIC_PPI 13
128 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
129 clocks = <&tegra_car TEGRA20_CLK_TWD>;
132 intc: interrupt-controller {
133 compatible = "arm,cortex-a9-gic";
134 reg = <0x50041000 0x1000
136 interrupt-controller;
137 #interrupt-cells = <3>;
141 compatible = "arm,pl310-cache";
142 reg = <0x50043000 0x1000>;
143 arm,data-latency = <5 5 2>;
144 arm,tag-latency = <4 4 2>;
150 compatible = "nvidia,tegra20-timer";
151 reg = <0x60005000 0x60>;
152 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
153 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
154 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
155 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
156 clocks = <&tegra_car TEGRA20_CLK_TIMER>;
160 compatible = "nvidia,tegra20-car";
161 reg = <0x60006000 0x1000>;
166 compatible = "nvidia,tegra20-apbdma";
167 reg = <0x6000a000 0x1200>;
168 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
169 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
170 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
171 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
173 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
174 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
175 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
176 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
177 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
178 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
180 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
181 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
182 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
184 clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
188 compatible = "nvidia,tegra20-ahb";
189 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
193 compatible = "nvidia,tegra20-gpio";
194 reg = <0x6000d000 0x1000>;
195 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
196 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
204 #interrupt-cells = <2>;
205 interrupt-controller;
209 compatible = "nvidia,tegra20-pinmux";
210 reg = <0x70000014 0x10 /* Tri-state registers */
211 0x70000080 0x20 /* Mux registers */
212 0x700000a0 0x14 /* Pull-up/down registers */
213 0x70000868 0xa8>; /* Pad control registers */
217 compatible = "nvidia,tegra20-das";
218 reg = <0x70000c00 0x80>;
222 compatible = "nvidia,tegra20-ac97";
223 reg = <0x70002000 0x200>;
224 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
225 nvidia,dma-request-selector = <&apbdma 12>;
226 clocks = <&tegra_car TEGRA20_CLK_AC97>;
230 tegra_i2s1: i2s@70002800 {
231 compatible = "nvidia,tegra20-i2s";
232 reg = <0x70002800 0x200>;
233 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
234 nvidia,dma-request-selector = <&apbdma 2>;
235 clocks = <&tegra_car TEGRA20_CLK_I2S1>;
239 tegra_i2s2: i2s@70002a00 {
240 compatible = "nvidia,tegra20-i2s";
241 reg = <0x70002a00 0x200>;
242 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
243 nvidia,dma-request-selector = <&apbdma 1>;
244 clocks = <&tegra_car TEGRA20_CLK_I2S2>;
249 * There are two serial driver i.e. 8250 based simple serial
250 * driver and APB DMA based serial driver for higher baudrate
251 * and performace. To enable the 8250 based driver, the compatible
252 * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
253 * driver, the comptible is "nvidia,tegra20-hsuart".
255 uarta: serial@70006000 {
256 compatible = "nvidia,tegra20-uart";
257 reg = <0x70006000 0x40>;
259 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
260 nvidia,dma-request-selector = <&apbdma 8>;
261 clocks = <&tegra_car TEGRA20_CLK_UARTA>;
265 uartb: serial@70006040 {
266 compatible = "nvidia,tegra20-uart";
267 reg = <0x70006040 0x40>;
269 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
270 nvidia,dma-request-selector = <&apbdma 9>;
271 clocks = <&tegra_car TEGRA20_CLK_UARTB>;
275 uartc: serial@70006200 {
276 compatible = "nvidia,tegra20-uart";
277 reg = <0x70006200 0x100>;
279 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
280 nvidia,dma-request-selector = <&apbdma 10>;
281 clocks = <&tegra_car TEGRA20_CLK_UARTC>;
285 uartd: serial@70006300 {
286 compatible = "nvidia,tegra20-uart";
287 reg = <0x70006300 0x100>;
289 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
290 nvidia,dma-request-selector = <&apbdma 19>;
291 clocks = <&tegra_car TEGRA20_CLK_UARTD>;
295 uarte: serial@70006400 {
296 compatible = "nvidia,tegra20-uart";
297 reg = <0x70006400 0x100>;
299 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
300 nvidia,dma-request-selector = <&apbdma 20>;
301 clocks = <&tegra_car TEGRA20_CLK_UARTE>;
306 compatible = "nvidia,tegra20-pwm";
307 reg = <0x7000a000 0x100>;
309 clocks = <&tegra_car TEGRA20_CLK_PWM>;
314 compatible = "nvidia,tegra20-rtc";
315 reg = <0x7000e000 0x100>;
316 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
317 clocks = <&tegra_car TEGRA20_CLK_RTC>;
321 compatible = "nvidia,tegra20-i2c";
322 reg = <0x7000c000 0x100>;
323 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
324 #address-cells = <1>;
326 clocks = <&tegra_car TEGRA20_CLK_I2C1>,
327 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
328 clock-names = "div-clk", "fast-clk";
333 compatible = "nvidia,tegra20-sflash";
334 reg = <0x7000c380 0x80>;
335 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
336 nvidia,dma-request-selector = <&apbdma 11>;
337 #address-cells = <1>;
339 clocks = <&tegra_car TEGRA20_CLK_SPI>;
344 compatible = "nvidia,tegra20-i2c";
345 reg = <0x7000c400 0x100>;
346 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
347 #address-cells = <1>;
349 clocks = <&tegra_car TEGRA20_CLK_I2C2>,
350 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
351 clock-names = "div-clk", "fast-clk";
356 compatible = "nvidia,tegra20-i2c";
357 reg = <0x7000c500 0x100>;
358 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
359 #address-cells = <1>;
361 clocks = <&tegra_car TEGRA20_CLK_I2C3>,
362 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
363 clock-names = "div-clk", "fast-clk";
368 compatible = "nvidia,tegra20-i2c-dvc";
369 reg = <0x7000d000 0x200>;
370 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
371 #address-cells = <1>;
373 clocks = <&tegra_car TEGRA20_CLK_DVC>,
374 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
375 clock-names = "div-clk", "fast-clk";
380 compatible = "nvidia,tegra20-slink";
381 reg = <0x7000d400 0x200>;
382 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
383 nvidia,dma-request-selector = <&apbdma 15>;
384 #address-cells = <1>;
386 clocks = <&tegra_car TEGRA20_CLK_SBC1>;
391 compatible = "nvidia,tegra20-slink";
392 reg = <0x7000d600 0x200>;
393 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
394 nvidia,dma-request-selector = <&apbdma 16>;
395 #address-cells = <1>;
397 clocks = <&tegra_car TEGRA20_CLK_SBC2>;
402 compatible = "nvidia,tegra20-slink";
403 reg = <0x7000d800 0x200>;
404 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
405 nvidia,dma-request-selector = <&apbdma 17>;
406 #address-cells = <1>;
408 clocks = <&tegra_car TEGRA20_CLK_SBC3>;
413 compatible = "nvidia,tegra20-slink";
414 reg = <0x7000da00 0x200>;
415 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
416 nvidia,dma-request-selector = <&apbdma 18>;
417 #address-cells = <1>;
419 clocks = <&tegra_car TEGRA20_CLK_SBC4>;
424 compatible = "nvidia,tegra20-kbc";
425 reg = <0x7000e200 0x100>;
426 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
427 clocks = <&tegra_car TEGRA20_CLK_KBC>;
432 compatible = "nvidia,tegra20-pmc";
433 reg = <0x7000e400 0x400>;
434 clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
435 clock-names = "pclk", "clk32k_in";
438 memory-controller@7000f000 {
439 compatible = "nvidia,tegra20-mc";
440 reg = <0x7000f000 0x024
442 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
446 compatible = "nvidia,tegra20-gart";
447 reg = <0x7000f024 0x00000018 /* controller registers */
448 0x58000000 0x02000000>; /* GART aperture */
451 memory-controller@7000f400 {
452 compatible = "nvidia,tegra20-emc";
453 reg = <0x7000f400 0x200>;
454 #address-cells = <1>;
459 compatible = "nvidia,tegra20-ehci", "usb-ehci";
460 reg = <0xc5000000 0x4000>;
461 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
463 nvidia,has-legacy-mode;
464 clocks = <&tegra_car TEGRA20_CLK_USBD>;
465 nvidia,needs-double-reset;
466 nvidia,phy = <&phy1>;
470 phy1: usb-phy@c5000000 {
471 compatible = "nvidia,tegra20-usb-phy";
472 reg = <0xc5000000 0x4000 0xc5000000 0x4000>;
474 clocks = <&tegra_car TEGRA20_CLK_USBD>,
475 <&tegra_car TEGRA20_CLK_PLL_U>,
476 <&tegra_car TEGRA20_CLK_CLK_M>,
477 <&tegra_car TEGRA20_CLK_USBD>;
478 clock-names = "reg", "pll_u", "timer", "utmi-pads";
479 nvidia,has-legacy-mode;
480 hssync_start_delay = <9>;
481 idle_wait_delay = <17>;
482 elastic_limit = <16>;
483 term_range_adj = <6>;
491 compatible = "nvidia,tegra20-ehci", "usb-ehci";
492 reg = <0xc5004000 0x4000>;
493 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
495 clocks = <&tegra_car TEGRA20_CLK_USB2>;
496 nvidia,phy = <&phy2>;
500 phy2: usb-phy@c5004000 {
501 compatible = "nvidia,tegra20-usb-phy";
502 reg = <0xc5004000 0x4000>;
504 clocks = <&tegra_car TEGRA20_CLK_USB2>,
505 <&tegra_car TEGRA20_CLK_PLL_U>,
506 <&tegra_car TEGRA20_CLK_CDEV2>;
507 clock-names = "reg", "pll_u", "ulpi-link";
512 compatible = "nvidia,tegra20-ehci", "usb-ehci";
513 reg = <0xc5008000 0x4000>;
514 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
516 clocks = <&tegra_car TEGRA20_CLK_USB3>;
517 nvidia,phy = <&phy3>;
521 phy3: usb-phy@c5008000 {
522 compatible = "nvidia,tegra20-usb-phy";
523 reg = <0xc5008000 0x4000 0xc5000000 0x4000>;
525 clocks = <&tegra_car TEGRA20_CLK_USB3>,
526 <&tegra_car TEGRA20_CLK_PLL_U>,
527 <&tegra_car TEGRA20_CLK_CLK_M>,
528 <&tegra_car TEGRA20_CLK_USBD>;
529 clock-names = "reg", "pll_u", "timer", "utmi-pads";
530 hssync_start_delay = <9>;
531 idle_wait_delay = <17>;
532 elastic_limit = <16>;
533 term_range_adj = <6>;
541 compatible = "nvidia,tegra20-sdhci";
542 reg = <0xc8000000 0x200>;
543 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
544 clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
549 compatible = "nvidia,tegra20-sdhci";
550 reg = <0xc8000200 0x200>;
551 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
552 clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
557 compatible = "nvidia,tegra20-sdhci";
558 reg = <0xc8000400 0x200>;
559 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
560 clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
565 compatible = "nvidia,tegra20-sdhci";
566 reg = <0xc8000600 0x200>;
567 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
568 clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
573 #address-cells = <1>;
578 compatible = "arm,cortex-a9";
584 compatible = "arm,cortex-a9";
590 compatible = "arm,cortex-a9-pmu";
591 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
592 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;