1 /include/ "skeleton.dtsi"
4 compatible = "nvidia,tegra20";
5 interrupt-parent = <&intc>;
8 compatible = "nvidia,tegra20-host1x", "simple-bus";
9 reg = <0x50000000 0x00024000>;
10 interrupts = <0 65 0x04 /* mpcore syncpt */
11 0 67 0x04>; /* mpcore general */
16 ranges = <0x54000000 0x54000000 0x04000000>;
19 compatible = "nvidia,tegra20-mpe";
20 reg = <0x54040000 0x00040000>;
21 interrupts = <0 68 0x04>;
25 compatible = "nvidia,tegra20-vi";
26 reg = <0x54080000 0x00040000>;
27 interrupts = <0 69 0x04>;
31 compatible = "nvidia,tegra20-epp";
32 reg = <0x540c0000 0x00040000>;
33 interrupts = <0 70 0x04>;
37 compatible = "nvidia,tegra20-isp";
38 reg = <0x54100000 0x00040000>;
39 interrupts = <0 71 0x04>;
43 compatible = "nvidia,tegra20-gr2d";
44 reg = <0x54140000 0x00040000>;
45 interrupts = <0 72 0x04>;
49 compatible = "nvidia,tegra20-gr3d";
50 reg = <0x54180000 0x00040000>;
54 compatible = "nvidia,tegra20-dc";
55 reg = <0x54200000 0x00040000>;
56 interrupts = <0 73 0x04>;
64 compatible = "nvidia,tegra20-dc";
65 reg = <0x54240000 0x00040000>;
66 interrupts = <0 74 0x04>;
74 compatible = "nvidia,tegra20-hdmi";
75 reg = <0x54280000 0x00040000>;
76 interrupts = <0 75 0x04>;
81 compatible = "nvidia,tegra20-tvo";
82 reg = <0x542c0000 0x00040000>;
83 interrupts = <0 76 0x04>;
88 compatible = "nvidia,tegra20-dsi";
89 reg = <0x54300000 0x00040000>;
95 compatible = "arm,cortex-a9-twd-timer";
96 reg = <0x50040600 0x20>;
97 interrupts = <1 13 0x304>;
100 cache-controller@50043000 {
101 compatible = "arm,pl310-cache";
102 reg = <0x50043000 0x1000>;
103 arm,data-latency = <5 5 2>;
104 arm,tag-latency = <4 4 2>;
109 intc: interrupt-controller {
110 compatible = "arm,cortex-a9-gic";
111 reg = <0x50041000 0x1000
113 interrupt-controller;
114 #interrupt-cells = <3>;
118 compatible = "nvidia,tegra20-timer";
119 reg = <0x60005000 0x60>;
120 interrupts = <0 0 0x04
127 compatible = "nvidia,tegra20-apbdma";
128 reg = <0x6000a000 0x1200>;
129 interrupts = <0 104 0x04
148 compatible = "nvidia,tegra20-ahb";
149 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
153 compatible = "nvidia,tegra20-gpio";
154 reg = <0x6000d000 0x1000>;
155 interrupts = <0 32 0x04
164 #interrupt-cells = <2>;
165 interrupt-controller;
169 compatible = "nvidia,tegra20-pinmux";
170 reg = <0x70000014 0x10 /* Tri-state registers */
171 0x70000080 0x20 /* Mux registers */
172 0x700000a0 0x14 /* Pull-up/down registers */
173 0x70000868 0xa8>; /* Pad control registers */
177 compatible = "nvidia,tegra20-das";
178 reg = <0x70000c00 0x80>;
181 tegra_i2s1: i2s@70002800 {
182 compatible = "nvidia,tegra20-i2s";
183 reg = <0x70002800 0x200>;
184 interrupts = <0 13 0x04>;
185 nvidia,dma-request-selector = <&apbdma 2>;
189 tegra_i2s2: i2s@70002a00 {
190 compatible = "nvidia,tegra20-i2s";
191 reg = <0x70002a00 0x200>;
192 interrupts = <0 3 0x04>;
193 nvidia,dma-request-selector = <&apbdma 1>;
198 compatible = "nvidia,tegra20-uart";
199 reg = <0x70006000 0x40>;
201 interrupts = <0 36 0x04>;
206 compatible = "nvidia,tegra20-uart";
207 reg = <0x70006040 0x40>;
209 interrupts = <0 37 0x04>;
214 compatible = "nvidia,tegra20-uart";
215 reg = <0x70006200 0x100>;
217 interrupts = <0 46 0x04>;
222 compatible = "nvidia,tegra20-uart";
223 reg = <0x70006300 0x100>;
225 interrupts = <0 90 0x04>;
230 compatible = "nvidia,tegra20-uart";
231 reg = <0x70006400 0x100>;
233 interrupts = <0 91 0x04>;
238 compatible = "nvidia,tegra20-pwm";
239 reg = <0x7000a000 0x100>;
244 compatible = "nvidia,tegra20-rtc";
245 reg = <0x7000e000 0x100>;
246 interrupts = <0 2 0x04>;
250 compatible = "nvidia,tegra20-i2c";
251 reg = <0x7000c000 0x100>;
252 interrupts = <0 38 0x04>;
253 #address-cells = <1>;
259 compatible = "nvidia,tegra20-sflash";
260 reg = <0x7000c380 0x80>;
261 interrupts = <0 39 0x04>;
262 nvidia,dma-request-selector = <&apbdma 11>;
263 #address-cells = <1>;
269 compatible = "nvidia,tegra20-i2c";
270 reg = <0x7000c400 0x100>;
271 interrupts = <0 84 0x04>;
272 #address-cells = <1>;
278 compatible = "nvidia,tegra20-i2c";
279 reg = <0x7000c500 0x100>;
280 interrupts = <0 92 0x04>;
281 #address-cells = <1>;
287 compatible = "nvidia,tegra20-i2c-dvc";
288 reg = <0x7000d000 0x200>;
289 interrupts = <0 53 0x04>;
290 #address-cells = <1>;
296 compatible = "nvidia,tegra20-slink";
297 reg = <0x7000d400 0x200>;
298 interrupts = <0 59 0x04>;
299 nvidia,dma-request-selector = <&apbdma 15>;
300 #address-cells = <1>;
306 compatible = "nvidia,tegra20-slink";
307 reg = <0x7000d600 0x200>;
308 interrupts = <0 82 0x04>;
309 nvidia,dma-request-selector = <&apbdma 16>;
310 #address-cells = <1>;
316 compatible = "nvidia,tegra20-slink";
317 reg = <0x7000d480 0x200>;
318 interrupts = <0 83 0x04>;
319 nvidia,dma-request-selector = <&apbdma 17>;
320 #address-cells = <1>;
326 compatible = "nvidia,tegra20-slink";
327 reg = <0x7000da00 0x200>;
328 interrupts = <0 93 0x04>;
329 nvidia,dma-request-selector = <&apbdma 18>;
330 #address-cells = <1>;
336 compatible = "nvidia,tegra20-pmc";
337 reg = <0x7000e400 0x400>;
340 memory-controller@7000f000 {
341 compatible = "nvidia,tegra20-mc";
342 reg = <0x7000f000 0x024
344 interrupts = <0 77 0x04>;
348 compatible = "nvidia,tegra20-gart";
349 reg = <0x7000f024 0x00000018 /* controller registers */
350 0x58000000 0x02000000>; /* GART aperture */
353 memory-controller@7000f400 {
354 compatible = "nvidia,tegra20-emc";
355 reg = <0x7000f400 0x200>;
356 #address-cells = <1>;
361 compatible = "nvidia,tegra20-ehci", "usb-ehci";
362 reg = <0xc5000000 0x4000>;
363 interrupts = <0 20 0x04>;
365 nvidia,has-legacy-mode;
370 compatible = "nvidia,tegra20-ehci", "usb-ehci";
371 reg = <0xc5004000 0x4000>;
372 interrupts = <0 21 0x04>;
378 compatible = "nvidia,tegra20-ehci", "usb-ehci";
379 reg = <0xc5008000 0x4000>;
380 interrupts = <0 97 0x04>;
386 compatible = "nvidia,tegra20-sdhci";
387 reg = <0xc8000000 0x200>;
388 interrupts = <0 14 0x04>;
393 compatible = "nvidia,tegra20-sdhci";
394 reg = <0xc8000200 0x200>;
395 interrupts = <0 15 0x04>;
400 compatible = "nvidia,tegra20-sdhci";
401 reg = <0xc8000400 0x200>;
402 interrupts = <0 19 0x04>;
407 compatible = "nvidia,tegra20-sdhci";
408 reg = <0xc8000600 0x200>;
409 interrupts = <0 31 0x04>;
414 compatible = "arm,cortex-a9-pmu";
415 interrupts = <0 56 0x04