arch/arm/boot/dts/tegra20.dtsi

   1 /include/ "skeleton.dtsi"
   2
   3 / {
   4         compatible = "nvidia,tegra20";
   5         interrupt-parent = <&intc>;
   6
   7         intc: interrupt-controller@50041000 {
   8                 compatible = "arm,cortex-a9-gic";
   9                 interrupt-controller;
  10                 #interrupt-cells = <3>;
  11                 reg = < 0x50041000 0x1000 >,
  12                       < 0x50040100 0x0100 >;
  13         };
  14
  15         apbdma: dma@6000a000 {
  16                 compatible = "nvidia,tegra20-apbdma";
  17                 reg = <0x6000a000 0x1200>;
  18                 interrupts = < 0 104 0x04
  19                                0 105 0x04
  20                                0 106 0x04
  21                                0 107 0x04
  22                                0 108 0x04
  23                                0 109 0x04
  24                                0 110 0x04
  25                                0 111 0x04
  26                                0 112 0x04
  27                                0 113 0x04
  28                                0 114 0x04
  29                                0 115 0x04
  30                                0 116 0x04
  31                                0 117 0x04
  32                                0 118 0x04
  33                                0 119 0x04 >;
  34         };
  35
  36         i2c@7000c000 {
  37                 #address-cells = <1>;
  38                 #size-cells = <0>;
  39                 compatible = "nvidia,tegra20-i2c";
  40                 reg = <0x7000C000 0x100>;
  41                 interrupts = < 0 38 0x04 >;
  42         };
  43
  44         i2c@7000c400 {
  45                 #address-cells = <1>;
  46                 #size-cells = <0>;
  47                 compatible = "nvidia,tegra20-i2c";
  48                 reg = <0x7000C400 0x100>;
  49                 interrupts = < 0 84 0x04 >;
  50         };
  51
  52         i2c@7000c500 {
  53                 #address-cells = <1>;
  54                 #size-cells = <0>;
  55                 compatible = "nvidia,tegra20-i2c";
  56                 reg = <0x7000C500 0x100>;
  57                 interrupts = < 0 92 0x04 >;
  58         };
  59
  60         i2c@7000d000 {
  61                 #address-cells = <1>;
  62                 #size-cells = <0>;
  63                 compatible = "nvidia,tegra20-i2c-dvc";
  64                 reg = <0x7000D000 0x200>;
  65                 interrupts = < 0 53 0x04 >;
  66         };
  67
  68         i2s@70002800 {
  69                 compatible = "nvidia,tegra20-i2s";
  70                 reg = <0x70002800 0x200>;
  71                 interrupts = < 0 13 0x04 >;
  72                 dma-channel = < 2 >;
  73         };
  74
  75         i2s@70002a00 {
  76                 compatible = "nvidia,tegra20-i2s";
  77                 reg = <0x70002a00 0x200>;
  78                 interrupts = < 0 3 0x04 >;
  79                 dma-channel = < 1 >;
  80         };
  81
  82         das@70000c00 {
  83                 compatible = "nvidia,tegra20-das";
  84                 reg = <0x70000c00 0x80>;
  85         };
  86
  87         gpio: gpio@6000d000 {
  88                 compatible = "nvidia,tegra20-gpio";
  89                 reg = < 0x6000d000 0x1000 >;
  90                 interrupts = < 0 32 0x04
  91                                0 33 0x04
  92                                0 34 0x04
  93                                0 35 0x04
  94                                0 55 0x04
  95                                0 87 0x04
  96                                0 89 0x04 >;
  97                 #gpio-cells = <2>;
  98                 gpio-controller;
  99         };
 100
 101         pinmux: pinmux@70000000 {
 102                 compatible = "nvidia,tegra20-pinmux";
 103                 reg = < 0x70000014 0x10    /* Tri-state registers */
 104                         0x70000080 0x20    /* Mux registers */
 105                         0x700000a0 0x14    /* Pull-up/down registers */
 106                         0x70000868 0xa8 >; /* Pad control registers */
 107         };
 108
 109         serial@70006000 {
 110                 compatible = "nvidia,tegra20-uart";
 111                 reg = <0x70006000 0x40>;
 112                 reg-shift = <2>;
 113                 interrupts = < 0 36 0x04 >;
 114         };
 115
 116         serial@70006040 {
 117                 compatible = "nvidia,tegra20-uart";
 118                 reg = <0x70006040 0x40>;
 119                 reg-shift = <2>;
 120                 interrupts = < 0 37 0x04 >;
 121         };
 122
 123         serial@70006200 {
 124                 compatible = "nvidia,tegra20-uart";
 125                 reg = <0x70006200 0x100>;
 126                 reg-shift = <2>;
 127                 interrupts = < 0 46 0x04 >;
 128         };
 129
 130         serial@70006300 {
 131                 compatible = "nvidia,tegra20-uart";
 132                 reg = <0x70006300 0x100>;
 133                 reg-shift = <2>;
 134                 interrupts = < 0 90 0x04 >;
 135         };
 136
 137         serial@70006400 {
 138                 compatible = "nvidia,tegra20-uart";
 139                 reg = <0x70006400 0x100>;
 140                 reg-shift = <2>;
 141                 interrupts = < 0 91 0x04 >;
 142         };
 143
 144         emc@7000f400 {
 145                 #address-cells = <1>;
 146                 #size-cells = <0>;
 147                 compatible = "nvidia,tegra20-emc";
 148                 reg = <0x7000f400 0x200>;
 149         };
 150
 151         sdhci@c8000000 {
 152                 compatible = "nvidia,tegra20-sdhci";
 153                 reg = <0xc8000000 0x200>;
 154                 interrupts = < 0 14 0x04 >;
 155         };
 156
 157         sdhci@c8000200 {
 158                 compatible = "nvidia,tegra20-sdhci";
 159                 reg = <0xc8000200 0x200>;
 160                 interrupts = < 0 15 0x04 >;
 161         };
 162
 163         sdhci@c8000400 {
 164                 compatible = "nvidia,tegra20-sdhci";
 165                 reg = <0xc8000400 0x200>;
 166                 interrupts = < 0 19 0x04 >;
 167         };
 168
 169         sdhci@c8000600 {
 170                 compatible = "nvidia,tegra20-sdhci";
 171                 reg = <0xc8000600 0x200>;
 172                 interrupts = < 0 31 0x04 >;
 173         };
 174
 175         usb@c5000000 {
 176                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 177                 reg = <0xc5000000 0x4000>;
 178                 interrupts = < 0 20 0x04 >;
 179                 phy_type = "utmi";
 180         };
 181
 182         usb@c5004000 {
 183                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 184                 reg = <0xc5004000 0x4000>;
 185                 interrupts = < 0 21 0x04 >;
 186                 phy_type = "ulpi";
 187         };
 188
 189         usb@c5008000 {
 190                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 191                 reg = <0xc5008000 0x4000>;
 192                 interrupts = < 0 97 0x04 >;
 193                 phy_type = "utmi";
 194         };
 195 };
 196