1 #include <dt-bindings/clock/tegra30-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include "skeleton.dtsi"
9 compatible = "nvidia,tegra30";
10 interrupt-parent = <&intc>;
20 pcie-controller@00003000 {
21 compatible = "nvidia,tegra30-pcie";
23 reg = <0x00003000 0x00000800 /* PADS registers */
24 0x00003800 0x00000200 /* AFI registers */
25 0x10000000 0x10000000>; /* configuration space */
26 reg-names = "pads", "afi", "cs";
27 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
28 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
29 interrupt-names = "intr", "msi";
31 #interrupt-cells = <1>;
32 interrupt-map-mask = <0 0 0 0>;
33 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
35 bus-range = <0x00 0xff>;
39 ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */
40 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */
41 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */
42 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */
43 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */
44 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
46 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
47 <&tegra_car TEGRA30_CLK_AFI>,
48 <&tegra_car TEGRA30_CLK_PLL_E>,
49 <&tegra_car TEGRA30_CLK_CML0>;
50 clock-names = "pex", "afi", "pll_e", "cml";
51 resets = <&tegra_car 70>,
54 reset-names = "pex", "afi", "pcie_x";
59 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
60 reg = <0x000800 0 0 0 0>;
67 nvidia,num-lanes = <2>;
72 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
73 reg = <0x001000 0 0 0 0>;
80 nvidia,num-lanes = <2>;
85 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
86 reg = <0x001800 0 0 0 0>;
93 nvidia,num-lanes = <2>;
98 compatible = "nvidia,tegra30-host1x", "simple-bus";
99 reg = <0x50000000 0x00024000>;
100 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
101 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
102 clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
103 resets = <&tegra_car 28>;
104 reset-names = "host1x";
106 #address-cells = <1>;
109 ranges = <0x54000000 0x54000000 0x04000000>;
112 compatible = "nvidia,tegra30-mpe";
113 reg = <0x54040000 0x00040000>;
114 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
115 clocks = <&tegra_car TEGRA30_CLK_MPE>;
116 resets = <&tegra_car 60>;
121 compatible = "nvidia,tegra30-vi";
122 reg = <0x54080000 0x00040000>;
123 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
124 clocks = <&tegra_car TEGRA30_CLK_VI>;
125 resets = <&tegra_car 20>;
130 compatible = "nvidia,tegra30-epp";
131 reg = <0x540c0000 0x00040000>;
132 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
133 clocks = <&tegra_car TEGRA30_CLK_EPP>;
134 resets = <&tegra_car 19>;
139 compatible = "nvidia,tegra30-isp";
140 reg = <0x54100000 0x00040000>;
141 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
142 clocks = <&tegra_car TEGRA30_CLK_ISP>;
143 resets = <&tegra_car 23>;
148 compatible = "nvidia,tegra30-gr2d";
149 reg = <0x54140000 0x00040000>;
150 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
151 clocks = <&tegra_car TEGRA30_CLK_GR2D>;
152 resets = <&tegra_car 21>;
157 compatible = "nvidia,tegra30-gr3d";
158 reg = <0x54180000 0x00040000>;
159 clocks = <&tegra_car TEGRA30_CLK_GR3D
160 &tegra_car TEGRA30_CLK_GR3D2>;
161 clock-names = "3d", "3d2";
162 resets = <&tegra_car 24>,
164 reset-names = "3d", "3d2";
168 compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc";
169 reg = <0x54200000 0x00040000>;
170 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
171 clocks = <&tegra_car TEGRA30_CLK_DISP1>,
172 <&tegra_car TEGRA30_CLK_PLL_P>;
173 clock-names = "dc", "parent";
174 resets = <&tegra_car 27>;
185 compatible = "nvidia,tegra30-dc";
186 reg = <0x54240000 0x00040000>;
187 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
188 clocks = <&tegra_car TEGRA30_CLK_DISP2>,
189 <&tegra_car TEGRA30_CLK_PLL_P>;
190 clock-names = "dc", "parent";
191 resets = <&tegra_car 26>;
202 compatible = "nvidia,tegra30-hdmi";
203 reg = <0x54280000 0x00040000>;
204 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
205 clocks = <&tegra_car TEGRA30_CLK_HDMI>,
206 <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
207 clock-names = "hdmi", "parent";
208 resets = <&tegra_car 51>;
209 reset-names = "hdmi";
214 compatible = "nvidia,tegra30-tvo";
215 reg = <0x542c0000 0x00040000>;
216 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&tegra_car TEGRA30_CLK_TVO>;
222 compatible = "nvidia,tegra30-dsi";
223 reg = <0x54300000 0x00040000>;
224 clocks = <&tegra_car TEGRA30_CLK_DSIA>;
225 resets = <&tegra_car 48>;
232 compatible = "arm,cortex-a9-twd-timer";
233 reg = <0x50040600 0x20>;
234 interrupts = <GIC_PPI 13
235 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
236 clocks = <&tegra_car TEGRA30_CLK_TWD>;
239 intc: interrupt-controller@50041000 {
240 compatible = "arm,cortex-a9-gic";
241 reg = <0x50041000 0x1000
243 interrupt-controller;
244 #interrupt-cells = <3>;
247 cache-controller@50043000 {
248 compatible = "arm,pl310-cache";
249 reg = <0x50043000 0x1000>;
250 arm,data-latency = <6 6 2>;
251 arm,tag-latency = <5 5 2>;
257 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
258 reg = <0x60005000 0x400>;
259 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
260 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
261 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
262 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
263 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
264 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
265 clocks = <&tegra_car TEGRA30_CLK_TIMER>;
268 tegra_car: clock@60006000 {
269 compatible = "nvidia,tegra30-car";
270 reg = <0x60006000 0x1000>;
275 apbdma: dma@6000a000 {
276 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
277 reg = <0x6000a000 0x1400>;
278 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
279 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
287 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
288 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
290 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
297 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
298 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
299 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
300 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
301 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
302 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
303 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
304 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
306 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
307 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
308 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
309 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
311 resets = <&tegra_car 34>;
317 compatible = "nvidia,tegra30-ahb";
318 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
321 gpio: gpio@6000d000 {
322 compatible = "nvidia,tegra30-gpio";
323 reg = <0x6000d000 0x1000>;
324 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
325 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
326 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
327 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
328 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
329 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
331 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
334 #interrupt-cells = <2>;
335 interrupt-controller;
338 pinmux: pinmux@70000868 {
339 compatible = "nvidia,tegra30-pinmux";
340 reg = <0x70000868 0xd4 /* Pad control registers */
341 0x70003000 0x3e4>; /* Mux registers */
345 * There are two serial driver i.e. 8250 based simple serial
346 * driver and APB DMA based serial driver for higher baudrate
347 * and performace. To enable the 8250 based driver, the compatible
348 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
349 * the APB DMA based serial driver, the comptible is
350 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
352 uarta: serial@70006000 {
353 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
354 reg = <0x70006000 0x40>;
356 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
357 clocks = <&tegra_car TEGRA30_CLK_UARTA>;
358 resets = <&tegra_car 6>;
359 reset-names = "serial";
360 dmas = <&apbdma 8>, <&apbdma 8>;
361 dma-names = "rx", "tx";
365 uartb: serial@70006040 {
366 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
367 reg = <0x70006040 0x40>;
369 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
370 clocks = <&tegra_car TEGRA30_CLK_UARTB>;
371 resets = <&tegra_car 7>;
372 reset-names = "serial";
373 dmas = <&apbdma 9>, <&apbdma 9>;
374 dma-names = "rx", "tx";
378 uartc: serial@70006200 {
379 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
380 reg = <0x70006200 0x100>;
382 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
383 clocks = <&tegra_car TEGRA30_CLK_UARTC>;
384 resets = <&tegra_car 55>;
385 reset-names = "serial";
386 dmas = <&apbdma 10>, <&apbdma 10>;
387 dma-names = "rx", "tx";
391 uartd: serial@70006300 {
392 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
393 reg = <0x70006300 0x100>;
395 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
396 clocks = <&tegra_car TEGRA30_CLK_UARTD>;
397 resets = <&tegra_car 65>;
398 reset-names = "serial";
399 dmas = <&apbdma 19>, <&apbdma 19>;
400 dma-names = "rx", "tx";
404 uarte: serial@70006400 {
405 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
406 reg = <0x70006400 0x100>;
408 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
409 clocks = <&tegra_car TEGRA30_CLK_UARTE>;
410 resets = <&tegra_car 66>;
411 reset-names = "serial";
412 dmas = <&apbdma 20>, <&apbdma 20>;
413 dma-names = "rx", "tx";
418 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
419 reg = <0x7000a000 0x100>;
421 clocks = <&tegra_car TEGRA30_CLK_PWM>;
422 resets = <&tegra_car 17>;
428 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
429 reg = <0x7000e000 0x100>;
430 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
431 clocks = <&tegra_car TEGRA30_CLK_RTC>;
435 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
436 reg = <0x7000c000 0x100>;
437 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
438 #address-cells = <1>;
440 clocks = <&tegra_car TEGRA30_CLK_I2C1>,
441 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
442 clock-names = "div-clk", "fast-clk";
443 resets = <&tegra_car 12>;
445 dmas = <&apbdma 21>, <&apbdma 21>;
446 dma-names = "rx", "tx";
451 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
452 reg = <0x7000c400 0x100>;
453 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
454 #address-cells = <1>;
456 clocks = <&tegra_car TEGRA30_CLK_I2C2>,
457 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
458 clock-names = "div-clk", "fast-clk";
459 resets = <&tegra_car 54>;
461 dmas = <&apbdma 22>, <&apbdma 22>;
462 dma-names = "rx", "tx";
467 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
468 reg = <0x7000c500 0x100>;
469 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
470 #address-cells = <1>;
472 clocks = <&tegra_car TEGRA30_CLK_I2C3>,
473 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
474 clock-names = "div-clk", "fast-clk";
475 resets = <&tegra_car 67>;
477 dmas = <&apbdma 23>, <&apbdma 23>;
478 dma-names = "rx", "tx";
483 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
484 reg = <0x7000c700 0x100>;
485 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
486 #address-cells = <1>;
488 clocks = <&tegra_car TEGRA30_CLK_I2C4>,
489 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
490 resets = <&tegra_car 103>;
492 clock-names = "div-clk", "fast-clk";
493 dmas = <&apbdma 26>, <&apbdma 26>;
494 dma-names = "rx", "tx";
499 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
500 reg = <0x7000d000 0x100>;
501 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
502 #address-cells = <1>;
504 clocks = <&tegra_car TEGRA30_CLK_I2C5>,
505 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
506 clock-names = "div-clk", "fast-clk";
507 resets = <&tegra_car 47>;
509 dmas = <&apbdma 24>, <&apbdma 24>;
510 dma-names = "rx", "tx";
515 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
516 reg = <0x7000d400 0x200>;
517 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
518 #address-cells = <1>;
520 clocks = <&tegra_car TEGRA30_CLK_SBC1>;
521 resets = <&tegra_car 41>;
523 dmas = <&apbdma 15>, <&apbdma 15>;
524 dma-names = "rx", "tx";
529 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
530 reg = <0x7000d600 0x200>;
531 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
532 #address-cells = <1>;
534 clocks = <&tegra_car TEGRA30_CLK_SBC2>;
535 resets = <&tegra_car 44>;
537 dmas = <&apbdma 16>, <&apbdma 16>;
538 dma-names = "rx", "tx";
543 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
544 reg = <0x7000d800 0x200>;
545 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
546 #address-cells = <1>;
548 clocks = <&tegra_car TEGRA30_CLK_SBC3>;
549 resets = <&tegra_car 46>;
551 dmas = <&apbdma 17>, <&apbdma 17>;
552 dma-names = "rx", "tx";
557 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
558 reg = <0x7000da00 0x200>;
559 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
560 #address-cells = <1>;
562 clocks = <&tegra_car TEGRA30_CLK_SBC4>;
563 resets = <&tegra_car 68>;
565 dmas = <&apbdma 18>, <&apbdma 18>;
566 dma-names = "rx", "tx";
571 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
572 reg = <0x7000dc00 0x200>;
573 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
574 #address-cells = <1>;
576 clocks = <&tegra_car TEGRA30_CLK_SBC5>;
577 resets = <&tegra_car 104>;
579 dmas = <&apbdma 27>, <&apbdma 27>;
580 dma-names = "rx", "tx";
585 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
586 reg = <0x7000de00 0x200>;
587 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
588 #address-cells = <1>;
590 clocks = <&tegra_car TEGRA30_CLK_SBC6>;
591 resets = <&tegra_car 106>;
593 dmas = <&apbdma 28>, <&apbdma 28>;
594 dma-names = "rx", "tx";
599 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
600 reg = <0x7000e200 0x100>;
601 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
602 clocks = <&tegra_car TEGRA30_CLK_KBC>;
603 resets = <&tegra_car 36>;
609 compatible = "nvidia,tegra30-pmc";
610 reg = <0x7000e400 0x400>;
611 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
612 clock-names = "pclk", "clk32k_in";
615 memory-controller@7000f000 {
616 compatible = "nvidia,tegra30-mc";
617 reg = <0x7000f000 0x010
621 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
625 compatible = "nvidia,tegra30-smmu";
626 reg = <0x7000f010 0x02c
629 nvidia,#asids = <4>; /* # of ASIDs */
630 dma-window = <0 0x40000000>; /* IOVA start & length */
635 compatible = "nvidia,tegra30-ahub";
636 reg = <0x70080000 0x200
638 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
639 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
640 <&tegra_car TEGRA30_CLK_APBIF>;
641 clock-names = "d_audio", "apbif";
642 resets = <&tegra_car 106>, /* d_audio */
643 <&tegra_car 107>, /* apbif */
644 <&tegra_car 30>, /* i2s0 */
645 <&tegra_car 11>, /* i2s1 */
646 <&tegra_car 18>, /* i2s2 */
647 <&tegra_car 101>, /* i2s3 */
648 <&tegra_car 102>, /* i2s4 */
649 <&tegra_car 108>, /* dam0 */
650 <&tegra_car 109>, /* dam1 */
651 <&tegra_car 110>, /* dam2 */
652 <&tegra_car 10>; /* spdif */
653 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
654 "i2s3", "i2s4", "dam0", "dam1", "dam2",
656 dmas = <&apbdma 1>, <&apbdma 1>,
657 <&apbdma 2>, <&apbdma 2>,
658 <&apbdma 3>, <&apbdma 3>,
659 <&apbdma 4>, <&apbdma 4>;
660 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
663 #address-cells = <1>;
666 tegra_i2s0: i2s@70080300 {
667 compatible = "nvidia,tegra30-i2s";
668 reg = <0x70080300 0x100>;
669 nvidia,ahub-cif-ids = <4 4>;
670 clocks = <&tegra_car TEGRA30_CLK_I2S0>;
671 resets = <&tegra_car 30>;
676 tegra_i2s1: i2s@70080400 {
677 compatible = "nvidia,tegra30-i2s";
678 reg = <0x70080400 0x100>;
679 nvidia,ahub-cif-ids = <5 5>;
680 clocks = <&tegra_car TEGRA30_CLK_I2S1>;
681 resets = <&tegra_car 11>;
686 tegra_i2s2: i2s@70080500 {
687 compatible = "nvidia,tegra30-i2s";
688 reg = <0x70080500 0x100>;
689 nvidia,ahub-cif-ids = <6 6>;
690 clocks = <&tegra_car TEGRA30_CLK_I2S2>;
691 resets = <&tegra_car 18>;
696 tegra_i2s3: i2s@70080600 {
697 compatible = "nvidia,tegra30-i2s";
698 reg = <0x70080600 0x100>;
699 nvidia,ahub-cif-ids = <7 7>;
700 clocks = <&tegra_car TEGRA30_CLK_I2S3>;
701 resets = <&tegra_car 101>;
706 tegra_i2s4: i2s@70080700 {
707 compatible = "nvidia,tegra30-i2s";
708 reg = <0x70080700 0x100>;
709 nvidia,ahub-cif-ids = <8 8>;
710 clocks = <&tegra_car TEGRA30_CLK_I2S4>;
711 resets = <&tegra_car 102>;
718 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
719 reg = <0x78000000 0x200>;
720 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
721 clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
722 resets = <&tegra_car 14>;
723 reset-names = "sdhci";
728 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
729 reg = <0x78000200 0x200>;
730 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
731 clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
732 resets = <&tegra_car 9>;
733 reset-names = "sdhci";
738 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
739 reg = <0x78000400 0x200>;
740 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
741 clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
742 resets = <&tegra_car 69>;
743 reset-names = "sdhci";
748 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
749 reg = <0x78000600 0x200>;
750 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
751 clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
752 resets = <&tegra_car 15>;
753 reset-names = "sdhci";
758 compatible = "nvidia,tegra30-ehci", "usb-ehci";
759 reg = <0x7d000000 0x4000>;
760 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
762 clocks = <&tegra_car TEGRA30_CLK_USBD>;
763 resets = <&tegra_car 22>;
765 nvidia,needs-double-reset;
766 nvidia,phy = <&phy1>;
770 phy1: usb-phy@7d000000 {
771 compatible = "nvidia,tegra30-usb-phy";
772 reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
774 clocks = <&tegra_car TEGRA30_CLK_USBD>,
775 <&tegra_car TEGRA30_CLK_PLL_U>,
776 <&tegra_car TEGRA30_CLK_USBD>;
777 clock-names = "reg", "pll_u", "utmi-pads";
778 nvidia,hssync-start-delay = <9>;
779 nvidia,idle-wait-delay = <17>;
780 nvidia,elastic-limit = <16>;
781 nvidia,term-range-adj = <6>;
782 nvidia,xcvr-setup = <51>;
783 nvidia.xcvr-setup-use-fuses;
784 nvidia,xcvr-lsfslew = <1>;
785 nvidia,xcvr-lsrslew = <1>;
786 nvidia,xcvr-hsslew = <32>;
787 nvidia,hssquelch-level = <2>;
788 nvidia,hsdiscon-level = <5>;
793 compatible = "nvidia,tegra30-ehci", "usb-ehci";
794 reg = <0x7d004000 0x4000>;
795 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
797 clocks = <&tegra_car TEGRA30_CLK_USB2>;
798 resets = <&tegra_car 58>;
800 nvidia,phy = <&phy2>;
804 phy2: usb-phy@7d004000 {
805 compatible = "nvidia,tegra30-usb-phy";
806 reg = <0x7d004000 0x4000 0x7d000000 0x4000>;
808 clocks = <&tegra_car TEGRA30_CLK_USB2>,
809 <&tegra_car TEGRA30_CLK_PLL_U>,
810 <&tegra_car TEGRA30_CLK_USBD>;
811 clock-names = "reg", "pll_u", "utmi-pads";
812 nvidia,hssync-start-delay = <9>;
813 nvidia,idle-wait-delay = <17>;
814 nvidia,elastic-limit = <16>;
815 nvidia,term-range-adj = <6>;
816 nvidia,xcvr-setup = <51>;
817 nvidia.xcvr-setup-use-fuses;
818 nvidia,xcvr-lsfslew = <2>;
819 nvidia,xcvr-lsrslew = <2>;
820 nvidia,xcvr-hsslew = <32>;
821 nvidia,hssquelch-level = <2>;
822 nvidia,hsdiscon-level = <5>;
827 compatible = "nvidia,tegra30-ehci", "usb-ehci";
828 reg = <0x7d008000 0x4000>;
829 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
831 clocks = <&tegra_car TEGRA30_CLK_USB3>;
832 resets = <&tegra_car 59>;
834 nvidia,phy = <&phy3>;
838 phy3: usb-phy@7d008000 {
839 compatible = "nvidia,tegra30-usb-phy";
840 reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
842 clocks = <&tegra_car TEGRA30_CLK_USB3>,
843 <&tegra_car TEGRA30_CLK_PLL_U>,
844 <&tegra_car TEGRA30_CLK_USBD>;
845 clock-names = "reg", "pll_u", "utmi-pads";
846 nvidia,hssync-start-delay = <0>;
847 nvidia,idle-wait-delay = <17>;
848 nvidia,elastic-limit = <16>;
849 nvidia,term-range-adj = <6>;
850 nvidia,xcvr-setup = <51>;
851 nvidia.xcvr-setup-use-fuses;
852 nvidia,xcvr-lsfslew = <2>;
853 nvidia,xcvr-lsrslew = <2>;
854 nvidia,xcvr-hsslew = <32>;
855 nvidia,hssquelch-level = <2>;
856 nvidia,hsdiscon-level = <5>;
861 #address-cells = <1>;
866 compatible = "arm,cortex-a9";
872 compatible = "arm,cortex-a9";
878 compatible = "arm,cortex-a9";
884 compatible = "arm,cortex-a9";
890 compatible = "arm,cortex-a9-pmu";
891 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
892 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
893 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
894 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;