1 #include <dt-bindings/clock/tegra30-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include "skeleton.dtsi"
8 compatible = "nvidia,tegra30";
9 interrupt-parent = <&intc>;
20 compatible = "nvidia,tegra30-host1x", "simple-bus";
21 reg = <0x50000000 0x00024000>;
22 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
23 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
24 clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
29 ranges = <0x54000000 0x54000000 0x04000000>;
32 compatible = "nvidia,tegra30-mpe";
33 reg = <0x54040000 0x00040000>;
34 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
35 clocks = <&tegra_car TEGRA30_CLK_MPE>;
39 compatible = "nvidia,tegra30-vi";
40 reg = <0x54080000 0x00040000>;
41 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
42 clocks = <&tegra_car TEGRA30_CLK_VI>;
46 compatible = "nvidia,tegra30-epp";
47 reg = <0x540c0000 0x00040000>;
48 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
49 clocks = <&tegra_car TEGRA30_CLK_EPP>;
53 compatible = "nvidia,tegra30-isp";
54 reg = <0x54100000 0x00040000>;
55 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
56 clocks = <&tegra_car TEGRA30_CLK_ISP>;
60 compatible = "nvidia,tegra30-gr2d";
61 reg = <0x54140000 0x00040000>;
62 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
63 clocks = <&tegra_car TEGRA30_CLK_GR2D>;
67 compatible = "nvidia,tegra30-gr3d";
68 reg = <0x54180000 0x00040000>;
69 clocks = <&tegra_car 24 &tegra_car 98>;
70 clock-names = "3d", "3d2";
74 compatible = "nvidia,tegra30-dc";
75 reg = <0x54200000 0x00040000>;
76 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
77 clocks = <&tegra_car TEGRA30_CLK_DISP1>,
78 <&tegra_car TEGRA30_CLK_PLL_P>;
79 clock-names = "disp1", "parent";
87 compatible = "nvidia,tegra30-dc";
88 reg = <0x54240000 0x00040000>;
89 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
90 clocks = <&tegra_car TEGRA30_CLK_DISP2>,
91 <&tegra_car TEGRA30_CLK_PLL_P>;
92 clock-names = "disp2", "parent";
100 compatible = "nvidia,tegra30-hdmi";
101 reg = <0x54280000 0x00040000>;
102 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
103 clocks = <&tegra_car TEGRA30_CLK_HDMI>,
104 <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
105 clock-names = "hdmi", "parent";
110 compatible = "nvidia,tegra30-tvo";
111 reg = <0x542c0000 0x00040000>;
112 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
113 clocks = <&tegra_car TEGRA30_CLK_TVO>;
118 compatible = "nvidia,tegra30-dsi";
119 reg = <0x54300000 0x00040000>;
120 clocks = <&tegra_car TEGRA30_CLK_DSIA>;
126 compatible = "arm,cortex-a9-twd-timer";
127 reg = <0x50040600 0x20>;
128 interrupts = <GIC_PPI 13
129 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
130 clocks = <&tegra_car TEGRA30_CLK_TWD>;
133 intc: interrupt-controller {
134 compatible = "arm,cortex-a9-gic";
135 reg = <0x50041000 0x1000
137 interrupt-controller;
138 #interrupt-cells = <3>;
142 compatible = "arm,pl310-cache";
143 reg = <0x50043000 0x1000>;
144 arm,data-latency = <6 6 2>;
145 arm,tag-latency = <5 5 2>;
151 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
152 reg = <0x60005000 0x400>;
153 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
154 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
155 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
156 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
157 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
158 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
159 clocks = <&tegra_car TEGRA30_CLK_TIMER>;
163 compatible = "nvidia,tegra30-car";
164 reg = <0x60006000 0x1000>;
169 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
170 reg = <0x6000a000 0x1400>;
171 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
173 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
174 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
175 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
176 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
177 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
178 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
180 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
181 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
182 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
184 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
185 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
186 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
187 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
188 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
189 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
190 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
191 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
192 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
193 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
194 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
196 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
202 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
203 clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
207 compatible = "nvidia,tegra30-ahb";
208 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
212 compatible = "nvidia,tegra30-gpio";
213 reg = <0x6000d000 0x1000>;
214 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
220 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
221 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
224 #interrupt-cells = <2>;
225 interrupt-controller;
229 compatible = "nvidia,tegra30-pinmux";
230 reg = <0x70000868 0xd4 /* Pad control registers */
231 0x70003000 0x3e4>; /* Mux registers */
235 * There are two serial driver i.e. 8250 based simple serial
236 * driver and APB DMA based serial driver for higher baudrate
237 * and performace. To enable the 8250 based driver, the compatible
238 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
239 * the APB DMA based serial driver, the comptible is
240 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
242 uarta: serial@70006000 {
243 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
244 reg = <0x70006000 0x40>;
246 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
247 nvidia,dma-request-selector = <&apbdma 8>;
248 clocks = <&tegra_car TEGRA30_CLK_UARTA>;
252 uartb: serial@70006040 {
253 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
254 reg = <0x70006040 0x40>;
256 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
257 nvidia,dma-request-selector = <&apbdma 9>;
258 clocks = <&tegra_car TEGRA30_CLK_UARTB>;
262 uartc: serial@70006200 {
263 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
264 reg = <0x70006200 0x100>;
266 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
267 nvidia,dma-request-selector = <&apbdma 10>;
268 clocks = <&tegra_car TEGRA30_CLK_UARTC>;
272 uartd: serial@70006300 {
273 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
274 reg = <0x70006300 0x100>;
276 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
277 nvidia,dma-request-selector = <&apbdma 19>;
278 clocks = <&tegra_car TEGRA30_CLK_UARTD>;
282 uarte: serial@70006400 {
283 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
284 reg = <0x70006400 0x100>;
286 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
287 nvidia,dma-request-selector = <&apbdma 20>;
288 clocks = <&tegra_car TEGRA30_CLK_UARTE>;
293 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
294 reg = <0x7000a000 0x100>;
296 clocks = <&tegra_car TEGRA30_CLK_PWM>;
301 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
302 reg = <0x7000e000 0x100>;
303 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&tegra_car TEGRA30_CLK_RTC>;
308 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
309 reg = <0x7000c000 0x100>;
310 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
311 #address-cells = <1>;
313 clocks = <&tegra_car TEGRA30_CLK_I2C1>,
314 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
315 clock-names = "div-clk", "fast-clk";
320 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
321 reg = <0x7000c400 0x100>;
322 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
323 #address-cells = <1>;
325 clocks = <&tegra_car TEGRA30_CLK_I2C2>,
326 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
327 clock-names = "div-clk", "fast-clk";
332 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
333 reg = <0x7000c500 0x100>;
334 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
335 #address-cells = <1>;
337 clocks = <&tegra_car TEGRA30_CLK_I2C3>,
338 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
339 clock-names = "div-clk", "fast-clk";
344 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
345 reg = <0x7000c700 0x100>;
346 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
347 #address-cells = <1>;
349 clocks = <&tegra_car TEGRA30_CLK_I2C4>,
350 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
351 clock-names = "div-clk", "fast-clk";
356 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
357 reg = <0x7000d000 0x100>;
358 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
359 #address-cells = <1>;
361 clocks = <&tegra_car TEGRA30_CLK_I2C5>,
362 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
363 clock-names = "div-clk", "fast-clk";
368 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
369 reg = <0x7000d400 0x200>;
370 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
371 nvidia,dma-request-selector = <&apbdma 15>;
372 #address-cells = <1>;
374 clocks = <&tegra_car TEGRA30_CLK_SBC1>;
379 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
380 reg = <0x7000d600 0x200>;
381 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
382 nvidia,dma-request-selector = <&apbdma 16>;
383 #address-cells = <1>;
385 clocks = <&tegra_car TEGRA30_CLK_SBC2>;
390 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
391 reg = <0x7000d800 0x200>;
392 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
393 nvidia,dma-request-selector = <&apbdma 17>;
394 #address-cells = <1>;
396 clocks = <&tegra_car TEGRA30_CLK_SBC3>;
401 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
402 reg = <0x7000da00 0x200>;
403 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
404 nvidia,dma-request-selector = <&apbdma 18>;
405 #address-cells = <1>;
407 clocks = <&tegra_car TEGRA30_CLK_SBC4>;
412 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
413 reg = <0x7000dc00 0x200>;
414 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
415 nvidia,dma-request-selector = <&apbdma 27>;
416 #address-cells = <1>;
418 clocks = <&tegra_car TEGRA30_CLK_SBC5>;
423 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
424 reg = <0x7000de00 0x200>;
425 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
426 nvidia,dma-request-selector = <&apbdma 28>;
427 #address-cells = <1>;
429 clocks = <&tegra_car TEGRA30_CLK_SBC6>;
434 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
435 reg = <0x7000e200 0x100>;
436 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
437 clocks = <&tegra_car TEGRA30_CLK_KBC>;
442 compatible = "nvidia,tegra30-pmc";
443 reg = <0x7000e400 0x400>;
444 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
445 clock-names = "pclk", "clk32k_in";
449 compatible = "nvidia,tegra30-mc";
450 reg = <0x7000f000 0x010
454 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
458 compatible = "nvidia,tegra30-smmu";
459 reg = <0x7000f010 0x02c
462 nvidia,#asids = <4>; /* # of ASIDs */
463 dma-window = <0 0x40000000>; /* IOVA start & length */
468 compatible = "nvidia,tegra30-ahub";
469 reg = <0x70080000 0x200
471 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
472 nvidia,dma-request-selector = <&apbdma 1>;
473 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
474 <&tegra_car TEGRA30_CLK_APBIF>,
475 <&tegra_car TEGRA30_CLK_I2S0>,
476 <&tegra_car TEGRA30_CLK_I2S1>,
477 <&tegra_car TEGRA30_CLK_I2S2>,
478 <&tegra_car TEGRA30_CLK_I2S3>,
479 <&tegra_car TEGRA30_CLK_I2S4>,
480 <&tegra_car TEGRA30_CLK_DAM0>,
481 <&tegra_car TEGRA30_CLK_DAM1>,
482 <&tegra_car TEGRA30_CLK_DAM2>,
483 <&tegra_car TEGRA30_CLK_SPDIF_IN>;
484 clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
485 "i2s3", "i2s4", "dam0", "dam1", "dam2",
488 #address-cells = <1>;
491 tegra_i2s0: i2s@70080300 {
492 compatible = "nvidia,tegra30-i2s";
493 reg = <0x70080300 0x100>;
494 nvidia,ahub-cif-ids = <4 4>;
495 clocks = <&tegra_car TEGRA30_CLK_I2S0>;
499 tegra_i2s1: i2s@70080400 {
500 compatible = "nvidia,tegra30-i2s";
501 reg = <0x70080400 0x100>;
502 nvidia,ahub-cif-ids = <5 5>;
503 clocks = <&tegra_car TEGRA30_CLK_I2S1>;
507 tegra_i2s2: i2s@70080500 {
508 compatible = "nvidia,tegra30-i2s";
509 reg = <0x70080500 0x100>;
510 nvidia,ahub-cif-ids = <6 6>;
511 clocks = <&tegra_car TEGRA30_CLK_I2S2>;
515 tegra_i2s3: i2s@70080600 {
516 compatible = "nvidia,tegra30-i2s";
517 reg = <0x70080600 0x100>;
518 nvidia,ahub-cif-ids = <7 7>;
519 clocks = <&tegra_car TEGRA30_CLK_I2S3>;
523 tegra_i2s4: i2s@70080700 {
524 compatible = "nvidia,tegra30-i2s";
525 reg = <0x70080700 0x100>;
526 nvidia,ahub-cif-ids = <8 8>;
527 clocks = <&tegra_car TEGRA30_CLK_I2S4>;
533 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
534 reg = <0x78000000 0x200>;
535 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
536 clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
541 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
542 reg = <0x78000200 0x200>;
543 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
544 clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
549 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
550 reg = <0x78000400 0x200>;
551 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
552 clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
557 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
558 reg = <0x78000600 0x200>;
559 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
560 clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
565 #address-cells = <1>;
570 compatible = "arm,cortex-a9";
576 compatible = "arm,cortex-a9";
582 compatible = "arm,cortex-a9";
588 compatible = "arm,cortex-a9";
594 compatible = "arm,cortex-a9-pmu";
595 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
596 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
597 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
598 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;