1 /include/ "skeleton.dtsi"
4 compatible = "nvidia,tegra30";
5 interrupt-parent = <&intc>;
16 compatible = "nvidia,tegra30-host1x", "simple-bus";
17 reg = <0x50000000 0x00024000>;
18 interrupts = <0 65 0x04 /* mpcore syncpt */
19 0 67 0x04>; /* mpcore general */
20 clocks = <&tegra_car 28>;
25 ranges = <0x54000000 0x54000000 0x04000000>;
28 compatible = "nvidia,tegra30-mpe";
29 reg = <0x54040000 0x00040000>;
30 interrupts = <0 68 0x04>;
31 clocks = <&tegra_car 60>;
35 compatible = "nvidia,tegra30-vi";
36 reg = <0x54080000 0x00040000>;
37 interrupts = <0 69 0x04>;
38 clocks = <&tegra_car 164>;
42 compatible = "nvidia,tegra30-epp";
43 reg = <0x540c0000 0x00040000>;
44 interrupts = <0 70 0x04>;
45 clocks = <&tegra_car 19>;
49 compatible = "nvidia,tegra30-isp";
50 reg = <0x54100000 0x00040000>;
51 interrupts = <0 71 0x04>;
52 clocks = <&tegra_car 23>;
56 compatible = "nvidia,tegra30-gr2d";
57 reg = <0x54140000 0x00040000>;
58 interrupts = <0 72 0x04>;
59 clocks = <&tegra_car 21>;
63 compatible = "nvidia,tegra30-gr3d";
64 reg = <0x54180000 0x00040000>;
65 clocks = <&tegra_car 24 &tegra_car 98>;
66 clock-names = "3d", "3d2";
70 compatible = "nvidia,tegra30-dc";
71 reg = <0x54200000 0x00040000>;
72 interrupts = <0 73 0x04>;
73 clocks = <&tegra_car 27>, <&tegra_car 179>;
74 clock-names = "disp1", "parent";
82 compatible = "nvidia,tegra30-dc";
83 reg = <0x54240000 0x00040000>;
84 interrupts = <0 74 0x04>;
85 clocks = <&tegra_car 26>, <&tegra_car 179>;
86 clock-names = "disp2", "parent";
94 compatible = "nvidia,tegra30-hdmi";
95 reg = <0x54280000 0x00040000>;
96 interrupts = <0 75 0x04>;
97 clocks = <&tegra_car 51>, <&tegra_car 189>;
98 clock-names = "hdmi", "parent";
103 compatible = "nvidia,tegra30-tvo";
104 reg = <0x542c0000 0x00040000>;
105 interrupts = <0 76 0x04>;
106 clocks = <&tegra_car 169>;
111 compatible = "nvidia,tegra30-dsi";
112 reg = <0x54300000 0x00040000>;
113 clocks = <&tegra_car 48>;
119 compatible = "arm,cortex-a9-twd-timer";
120 reg = <0x50040600 0x20>;
121 interrupts = <1 13 0xf04>;
122 clocks = <&tegra_car 214>;
125 intc: interrupt-controller {
126 compatible = "arm,cortex-a9-gic";
127 reg = <0x50041000 0x1000
129 interrupt-controller;
130 #interrupt-cells = <3>;
134 compatible = "arm,pl310-cache";
135 reg = <0x50043000 0x1000>;
136 arm,data-latency = <6 6 2>;
137 arm,tag-latency = <5 5 2>;
143 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
144 reg = <0x60005000 0x400>;
145 interrupts = <0 0 0x04
151 clocks = <&tegra_car 5>;
155 compatible = "nvidia,tegra30-car";
156 reg = <0x60006000 0x1000>;
161 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
162 reg = <0x6000a000 0x1400>;
163 interrupts = <0 104 0x04
195 clocks = <&tegra_car 34>;
199 compatible = "nvidia,tegra30-ahb";
200 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
204 compatible = "nvidia,tegra30-gpio";
205 reg = <0x6000d000 0x1000>;
206 interrupts = <0 32 0x04
216 #interrupt-cells = <2>;
217 interrupt-controller;
221 compatible = "nvidia,tegra30-pinmux";
222 reg = <0x70000868 0xd4 /* Pad control registers */
223 0x70003000 0x3e4>; /* Mux registers */
227 * There are two serial driver i.e. 8250 based simple serial
228 * driver and APB DMA based serial driver for higher baudrate
229 * and performace. To enable the 8250 based driver, the compatible
230 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
231 * the APB DMA based serial driver, the comptible is
232 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
234 uarta: serial@70006000 {
235 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
236 reg = <0x70006000 0x40>;
238 interrupts = <0 36 0x04>;
239 nvidia,dma-request-selector = <&apbdma 8>;
240 clocks = <&tegra_car 6>;
244 uartb: serial@70006040 {
245 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
246 reg = <0x70006040 0x40>;
248 interrupts = <0 37 0x04>;
249 nvidia,dma-request-selector = <&apbdma 9>;
250 clocks = <&tegra_car 160>;
254 uartc: serial@70006200 {
255 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
256 reg = <0x70006200 0x100>;
258 interrupts = <0 46 0x04>;
259 nvidia,dma-request-selector = <&apbdma 10>;
260 clocks = <&tegra_car 55>;
264 uartd: serial@70006300 {
265 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
266 reg = <0x70006300 0x100>;
268 interrupts = <0 90 0x04>;
269 nvidia,dma-request-selector = <&apbdma 19>;
270 clocks = <&tegra_car 65>;
274 uarte: serial@70006400 {
275 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
276 reg = <0x70006400 0x100>;
278 interrupts = <0 91 0x04>;
279 nvidia,dma-request-selector = <&apbdma 20>;
280 clocks = <&tegra_car 66>;
285 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
286 reg = <0x7000a000 0x100>;
288 clocks = <&tegra_car 17>;
292 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
293 reg = <0x7000e000 0x100>;
294 interrupts = <0 2 0x04>;
295 clocks = <&tegra_car 4>;
299 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
300 reg = <0x7000c000 0x100>;
301 interrupts = <0 38 0x04>;
302 #address-cells = <1>;
304 clocks = <&tegra_car 12>, <&tegra_car 182>;
305 clock-names = "div-clk", "fast-clk";
310 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
311 reg = <0x7000c400 0x100>;
312 interrupts = <0 84 0x04>;
313 #address-cells = <1>;
315 clocks = <&tegra_car 54>, <&tegra_car 182>;
316 clock-names = "div-clk", "fast-clk";
321 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
322 reg = <0x7000c500 0x100>;
323 interrupts = <0 92 0x04>;
324 #address-cells = <1>;
326 clocks = <&tegra_car 67>, <&tegra_car 182>;
327 clock-names = "div-clk", "fast-clk";
332 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
333 reg = <0x7000c700 0x100>;
334 interrupts = <0 120 0x04>;
335 #address-cells = <1>;
337 clocks = <&tegra_car 103>, <&tegra_car 182>;
338 clock-names = "div-clk", "fast-clk";
343 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
344 reg = <0x7000d000 0x100>;
345 interrupts = <0 53 0x04>;
346 #address-cells = <1>;
348 clocks = <&tegra_car 47>, <&tegra_car 182>;
349 clock-names = "div-clk", "fast-clk";
354 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
355 reg = <0x7000d400 0x200>;
356 interrupts = <0 59 0x04>;
357 nvidia,dma-request-selector = <&apbdma 15>;
358 #address-cells = <1>;
360 clocks = <&tegra_car 41>;
365 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
366 reg = <0x7000d600 0x200>;
367 interrupts = <0 82 0x04>;
368 nvidia,dma-request-selector = <&apbdma 16>;
369 #address-cells = <1>;
371 clocks = <&tegra_car 44>;
376 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
377 reg = <0x7000d800 0x200>;
378 interrupts = <0 83 0x04>;
379 nvidia,dma-request-selector = <&apbdma 17>;
380 #address-cells = <1>;
382 clocks = <&tegra_car 46>;
387 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
388 reg = <0x7000da00 0x200>;
389 interrupts = <0 93 0x04>;
390 nvidia,dma-request-selector = <&apbdma 18>;
391 #address-cells = <1>;
393 clocks = <&tegra_car 68>;
398 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
399 reg = <0x7000dc00 0x200>;
400 interrupts = <0 94 0x04>;
401 nvidia,dma-request-selector = <&apbdma 27>;
402 #address-cells = <1>;
404 clocks = <&tegra_car 104>;
409 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
410 reg = <0x7000de00 0x200>;
411 interrupts = <0 79 0x04>;
412 nvidia,dma-request-selector = <&apbdma 28>;
413 #address-cells = <1>;
415 clocks = <&tegra_car 105>;
420 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
421 reg = <0x7000e200 0x100>;
422 interrupts = <0 85 0x04>;
423 clocks = <&tegra_car 36>;
428 compatible = "nvidia,tegra30-pmc";
429 reg = <0x7000e400 0x400>;
430 clocks = <&tegra_car 218>, <&clk32k_in>;
431 clock-names = "pclk", "clk32k_in";
435 compatible = "nvidia,tegra30-mc";
436 reg = <0x7000f000 0x010
440 interrupts = <0 77 0x04>;
444 compatible = "nvidia,tegra30-smmu";
445 reg = <0x7000f010 0x02c
448 nvidia,#asids = <4>; /* # of ASIDs */
449 dma-window = <0 0x40000000>; /* IOVA start & length */
454 compatible = "nvidia,tegra30-ahub";
455 reg = <0x70080000 0x200
457 interrupts = <0 103 0x04>;
458 nvidia,dma-request-selector = <&apbdma 1>;
459 clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
460 <&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>,
461 <&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>,
462 <&tegra_car 110>, <&tegra_car 162>;
463 clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
464 "i2s3", "i2s4", "dam0", "dam1", "dam2",
467 #address-cells = <1>;
470 tegra_i2s0: i2s@70080300 {
471 compatible = "nvidia,tegra30-i2s";
472 reg = <0x70080300 0x100>;
473 nvidia,ahub-cif-ids = <4 4>;
474 clocks = <&tegra_car 30>;
478 tegra_i2s1: i2s@70080400 {
479 compatible = "nvidia,tegra30-i2s";
480 reg = <0x70080400 0x100>;
481 nvidia,ahub-cif-ids = <5 5>;
482 clocks = <&tegra_car 11>;
486 tegra_i2s2: i2s@70080500 {
487 compatible = "nvidia,tegra30-i2s";
488 reg = <0x70080500 0x100>;
489 nvidia,ahub-cif-ids = <6 6>;
490 clocks = <&tegra_car 18>;
494 tegra_i2s3: i2s@70080600 {
495 compatible = "nvidia,tegra30-i2s";
496 reg = <0x70080600 0x100>;
497 nvidia,ahub-cif-ids = <7 7>;
498 clocks = <&tegra_car 101>;
502 tegra_i2s4: i2s@70080700 {
503 compatible = "nvidia,tegra30-i2s";
504 reg = <0x70080700 0x100>;
505 nvidia,ahub-cif-ids = <8 8>;
506 clocks = <&tegra_car 102>;
512 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
513 reg = <0x78000000 0x200>;
514 interrupts = <0 14 0x04>;
515 clocks = <&tegra_car 14>;
520 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
521 reg = <0x78000200 0x200>;
522 interrupts = <0 15 0x04>;
523 clocks = <&tegra_car 9>;
528 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
529 reg = <0x78000400 0x200>;
530 interrupts = <0 19 0x04>;
531 clocks = <&tegra_car 69>;
536 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
537 reg = <0x78000600 0x200>;
538 interrupts = <0 31 0x04>;
539 clocks = <&tegra_car 15>;
544 #address-cells = <1>;
549 compatible = "arm,cortex-a9";
555 compatible = "arm,cortex-a9";
561 compatible = "arm,cortex-a9";
567 compatible = "arm,cortex-a9";
573 compatible = "arm,cortex-a9-pmu";
574 interrupts = <0 144 0x04