2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #include "skeleton.dtsi"
11 #include "vf610-pinfunc.h"
12 #include <dt-bindings/clock/vf610-clock.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
35 compatible = "arm,cortex-a5";
38 next-level-cache = <&L2>;
47 compatible = "fixed-clock";
49 clock-frequency = <32768>;
53 compatible = "fixed-clock";
55 clock-frequency = <24000000>;
62 compatible = "simple-bus";
63 interrupt-parent = <&intc>;
66 aips0: aips-bus@40000000 {
67 compatible = "fsl,aips-bus", "simple-bus";
70 interrupt-parent = <&intc>;
71 reg = <0x40000000 0x70000>;
74 intc: interrupt-controller@40002000 {
75 compatible = "arm,cortex-a9-gic";
76 #interrupt-cells = <3>;
78 reg = <0x40003000 0x1000>,
82 L2: l2-cache@40006000 {
83 compatible = "arm,pl310-cache";
84 reg = <0x40006000 0x1000>;
87 arm,data-latency = <1 1 1>;
88 arm,tag-latency = <2 2 2>;
91 edma0: dma-controller@40018000 {
93 compatible = "fsl,vf610-edma";
94 reg = <0x40018000 0x2000>,
97 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
98 <0 9 IRQ_TYPE_LEVEL_HIGH>;
99 interrupt-names = "edma-tx", "edma-err";
101 clock-names = "dmamux0", "dmamux1";
102 clocks = <&clks VF610_CLK_DMAMUX0>,
103 <&clks VF610_CLK_DMAMUX1>;
106 uart0: serial@40027000 {
107 compatible = "fsl,vf610-lpuart";
108 reg = <0x40027000 0x1000>;
109 interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
110 clocks = <&clks VF610_CLK_UART0>;
114 dma-names = "rx","tx";
118 uart1: serial@40028000 {
119 compatible = "fsl,vf610-lpuart";
120 reg = <0x40028000 0x1000>;
121 interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
122 clocks = <&clks VF610_CLK_UART1>;
126 dma-names = "rx","tx";
130 uart2: serial@40029000 {
131 compatible = "fsl,vf610-lpuart";
132 reg = <0x40029000 0x1000>;
133 interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
134 clocks = <&clks VF610_CLK_UART2>;
138 dma-names = "rx","tx";
142 uart3: serial@4002a000 {
143 compatible = "fsl,vf610-lpuart";
144 reg = <0x4002a000 0x1000>;
145 interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>;
146 clocks = <&clks VF610_CLK_UART3>;
150 dma-names = "rx","tx";
154 dspi0: dspi0@4002c000 {
155 #address-cells = <1>;
157 compatible = "fsl,vf610-dspi";
158 reg = <0x4002c000 0x1000>;
159 interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
160 clocks = <&clks VF610_CLK_DSPI0>;
161 clock-names = "dspi";
162 spi-num-chipselects = <5>;
167 compatible = "fsl,vf610-sai";
168 reg = <0x40031000 0x1000>;
169 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
170 clocks = <&clks VF610_CLK_SAI2>;
172 dma-names = "tx", "rx";
173 dmas = <&edma0 0 21>,
179 compatible = "fsl,vf610-pit";
180 reg = <0x40037000 0x1000>;
181 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
182 clocks = <&clks VF610_CLK_PIT>;
187 compatible = "fsl,vf610-ftm-pwm";
189 reg = <0x40038000 0x1000>;
190 clock-names = "ftm_sys", "ftm_ext",
191 "ftm_fix", "ftm_cnt_clk_en";
192 clocks = <&clks VF610_CLK_FTM0>,
193 <&clks VF610_CLK_FTM0_EXT_SEL>,
194 <&clks VF610_CLK_FTM0_FIX_SEL>,
195 <&clks VF610_CLK_FTM0_EXT_FIX_EN>;
200 compatible = "fsl,vf610-adc";
201 reg = <0x4003b000 0x1000>;
202 interrupts = <0 53 0x04>;
203 clocks = <&clks VF610_CLK_ADC0>;
209 compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
210 reg = <0x4003e000 0x1000>;
211 clocks = <&clks VF610_CLK_WDT>;
212 clock-names = "wdog";
215 qspi0: quadspi@40044000 {
216 #address-cells = <1>;
218 compatible = "fsl,vf610-qspi";
219 reg = <0x40044000 0x1000>;
220 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
221 clocks = <&clks VF610_CLK_QSPI0_EN>,
222 <&clks VF610_CLK_QSPI0>;
223 clock-names = "qspi_en", "qspi";
227 iomuxc: iomuxc@40048000 {
228 compatible = "fsl,vf610-iomuxc";
229 reg = <0x40048000 0x1000>;
230 #gpio-range-cells = <3>;
233 gpio1: gpio@40049000 {
234 compatible = "fsl,vf610-gpio";
235 reg = <0x40049000 0x1000 0x400ff000 0x40>;
236 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
239 interrupt-controller;
240 #interrupt-cells = <2>;
241 gpio-ranges = <&iomuxc 0 0 32>;
244 gpio2: gpio@4004a000 {
245 compatible = "fsl,vf610-gpio";
246 reg = <0x4004a000 0x1000 0x400ff040 0x40>;
247 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
250 interrupt-controller;
251 #interrupt-cells = <2>;
252 gpio-ranges = <&iomuxc 0 32 32>;
255 gpio3: gpio@4004b000 {
256 compatible = "fsl,vf610-gpio";
257 reg = <0x4004b000 0x1000 0x400ff080 0x40>;
258 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
261 interrupt-controller;
262 #interrupt-cells = <2>;
263 gpio-ranges = <&iomuxc 0 64 32>;
266 gpio4: gpio@4004c000 {
267 compatible = "fsl,vf610-gpio";
268 reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
269 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
272 interrupt-controller;
273 #interrupt-cells = <2>;
274 gpio-ranges = <&iomuxc 0 96 32>;
277 gpio5: gpio@4004d000 {
278 compatible = "fsl,vf610-gpio";
279 reg = <0x4004d000 0x1000 0x400ff100 0x40>;
280 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
283 interrupt-controller;
284 #interrupt-cells = <2>;
285 gpio-ranges = <&iomuxc 0 128 7>;
289 compatible = "fsl,vf610-anatop";
290 reg = <0x40050000 0x1000>;
294 #address-cells = <1>;
296 compatible = "fsl,vf610-i2c";
297 reg = <0x40066000 0x1000>;
298 interrupts =<0 71 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&clks VF610_CLK_I2C0>;
301 dmas = <&edma0 0 50>,
303 dma-names = "rx","tx";
308 compatible = "fsl,vf610-ccm";
309 reg = <0x4006b000 0x1000>;
314 aips1: aips-bus@40080000 {
315 compatible = "fsl,aips-bus", "simple-bus";
316 #address-cells = <1>;
318 reg = <0x40080000 0x80000>;
321 edma1: dma-controller@40098000 {
323 compatible = "fsl,vf610-edma";
324 reg = <0x40098000 0x2000>,
327 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>,
328 <0 11 IRQ_TYPE_LEVEL_HIGH>;
329 interrupt-names = "edma-tx", "edma-err";
331 clock-names = "dmamux0", "dmamux1";
332 clocks = <&clks VF610_CLK_DMAMUX2>,
333 <&clks VF610_CLK_DMAMUX3>;
336 uart4: serial@400a9000 {
337 compatible = "fsl,vf610-lpuart";
338 reg = <0x400a9000 0x1000>;
339 interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
340 clocks = <&clks VF610_CLK_UART4>;
345 uart5: serial@400aa000 {
346 compatible = "fsl,vf610-lpuart";
347 reg = <0x400aa000 0x1000>;
348 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
349 clocks = <&clks VF610_CLK_UART5>;
355 compatible = "fsl,vf610-adc";
356 reg = <0x400bb000 0x1000>;
357 interrupts = <0 54 0x04>;
358 clocks = <&clks VF610_CLK_ADC1>;
363 esdhc1: esdhc@400b2000 {
364 compatible = "fsl,imx53-esdhc";
365 reg = <0x400b2000 0x4000>;
366 interrupts = <0 28 0x04>;
367 clocks = <&clks VF610_CLK_IPG_BUS>,
368 <&clks VF610_CLK_PLATFORM_BUS>,
369 <&clks VF610_CLK_ESDHC1>;
370 clock-names = "ipg", "ahb", "per";
375 compatible = "fsl,ftm-timer";
376 reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
377 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
378 clock-names = "ftm-evt", "ftm-src",
379 "ftm-evt-counter-en", "ftm-src-counter-en";
380 clocks = <&clks VF610_CLK_FTM2>,
381 <&clks VF610_CLK_FTM3>,
382 <&clks VF610_CLK_FTM2_EXT_FIX_EN>,
383 <&clks VF610_CLK_FTM3_EXT_FIX_EN>;
387 fec0: ethernet@400d0000 {
388 compatible = "fsl,mvf600-fec";
389 reg = <0x400d0000 0x1000>;
390 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
391 clocks = <&clks VF610_CLK_ENET0>,
392 <&clks VF610_CLK_ENET0>,
393 <&clks VF610_CLK_ENET>;
394 clock-names = "ipg", "ahb", "ptp";
398 fec1: ethernet@400d1000 {
399 compatible = "fsl,mvf600-fec";
400 reg = <0x400d1000 0x1000>;
401 interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
402 clocks = <&clks VF610_CLK_ENET1>,
403 <&clks VF610_CLK_ENET1>,
404 <&clks VF610_CLK_ENET>;
405 clock-names = "ipg", "ahb", "ptp";