2 * Copyright (C) 2011 - 2014 Xilinx
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 /include/ "skeleton.dtsi"
16 compatible = "xlnx,zynq-7000";
23 compatible = "arm,cortex-a9";
27 clock-latency = <1000>;
28 cpu0-supply = <®ulator_vccpint>;
38 compatible = "arm,cortex-a9";
46 compatible = "arm,cortex-a9-pmu";
47 interrupts = <0 5 4>, <0 6 4>;
48 interrupt-parent = <&intc>;
49 reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
52 regulator_vccpint: fixedregulator@0 {
53 compatible = "regulator-fixed";
54 regulator-name = "VCCPINT";
55 regulator-min-microvolt = <1000000>;
56 regulator-max-microvolt = <1000000>;
62 compatible = "simple-bus";
65 interrupt-parent = <&intc>;
69 compatible = "xlnx,zynq-xadc-1.00.a";
70 reg = <0xf8007100 0x20>;
72 interrupt-parent = <&intc>;
77 compatible = "xlnx,zynq-can-1.0";
79 clocks = <&clkc 19>, <&clkc 36>;
80 clock-names = "can_clk", "pclk";
81 reg = <0xe0008000 0x1000>;
82 interrupts = <0 28 4>;
83 interrupt-parent = <&intc>;
84 tx-fifo-depth = <0x40>;
85 rx-fifo-depth = <0x40>;
89 compatible = "xlnx,zynq-can-1.0";
91 clocks = <&clkc 20>, <&clkc 37>;
92 clock-names = "can_clk", "pclk";
93 reg = <0xe0009000 0x1000>;
94 interrupts = <0 51 4>;
95 interrupt-parent = <&intc>;
96 tx-fifo-depth = <0x40>;
97 rx-fifo-depth = <0x40>;
100 gpio0: gpio@e000a000 {
101 compatible = "xlnx,zynq-gpio-1.0";
105 interrupt-parent = <&intc>;
106 interrupts = <0 20 4>;
107 reg = <0xe000a000 0x1000>;
111 compatible = "cdns,i2c-r1p10";
114 interrupt-parent = <&intc>;
115 interrupts = <0 25 4>;
116 reg = <0xe0004000 0x1000>;
117 #address-cells = <1>;
122 compatible = "cdns,i2c-r1p10";
125 interrupt-parent = <&intc>;
126 interrupts = <0 48 4>;
127 reg = <0xe0005000 0x1000>;
128 #address-cells = <1>;
132 intc: interrupt-controller@f8f01000 {
133 compatible = "arm,cortex-a9-gic";
134 #interrupt-cells = <3>;
135 interrupt-controller;
136 reg = <0xF8F01000 0x1000>,
140 L2: cache-controller {
141 compatible = "arm,pl310-cache";
142 reg = <0xF8F02000 0x1000>;
143 arm,data-latency = <3 2 2>;
144 arm,tag-latency = <2 2 2>;
149 memory-controller@f8006000 {
150 compatible = "xlnx,zynq-ddrc-a05";
151 reg = <0xf8006000 0x1000>;
154 uart0: serial@e0000000 {
155 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
157 clocks = <&clkc 23>, <&clkc 40>;
158 clock-names = "uart_clk", "pclk";
159 reg = <0xE0000000 0x1000>;
160 interrupts = <0 27 4>;
163 uart1: serial@e0001000 {
164 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
166 clocks = <&clkc 24>, <&clkc 41>;
167 clock-names = "uart_clk", "pclk";
168 reg = <0xE0001000 0x1000>;
169 interrupts = <0 50 4>;
173 compatible = "xlnx,zynq-spi-r1p6";
174 reg = <0xe0006000 0x1000>;
176 interrupt-parent = <&intc>;
177 interrupts = <0 26 4>;
178 clocks = <&clkc 25>, <&clkc 34>;
179 clock-names = "ref_clk", "pclk";
180 #address-cells = <1>;
185 compatible = "xlnx,zynq-spi-r1p6";
186 reg = <0xe0007000 0x1000>;
188 interrupt-parent = <&intc>;
189 interrupts = <0 49 4>;
190 clocks = <&clkc 26>, <&clkc 35>;
191 clock-names = "ref_clk", "pclk";
192 #address-cells = <1>;
196 gem0: ethernet@e000b000 {
197 compatible = "cdns,gem";
198 reg = <0xe000b000 0x4000>;
200 interrupts = <0 22 4>;
201 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
202 clock-names = "pclk", "hclk", "tx_clk";
203 #address-cells = <1>;
207 gem1: ethernet@e000c000 {
208 compatible = "cdns,gem";
209 reg = <0xe000c000 0x4000>;
211 interrupts = <0 45 4>;
212 clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
213 clock-names = "pclk", "hclk", "tx_clk";
214 #address-cells = <1>;
218 sdhci0: sdhci@e0100000 {
219 compatible = "arasan,sdhci-8.9a";
221 clock-names = "clk_xin", "clk_ahb";
222 clocks = <&clkc 21>, <&clkc 32>;
223 interrupt-parent = <&intc>;
224 interrupts = <0 24 4>;
225 reg = <0xe0100000 0x1000>;
228 sdhci1: sdhci@e0101000 {
229 compatible = "arasan,sdhci-8.9a";
231 clock-names = "clk_xin", "clk_ahb";
232 clocks = <&clkc 22>, <&clkc 33>;
233 interrupt-parent = <&intc>;
234 interrupts = <0 47 4>;
235 reg = <0xe0101000 0x1000>;
238 slcr: slcr@f8000000 {
239 #address-cells = <1>;
241 compatible = "xlnx,zynq-slcr", "syscon";
242 reg = <0xF8000000 0x1000>;
246 compatible = "xlnx,ps7-clkc";
247 ps-clk-frequency = <33333333>;
249 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
250 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
251 "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
252 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
253 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
254 "dma", "usb0_aper", "usb1_aper", "gem0_aper",
255 "gem1_aper", "sdio0_aper", "sdio1_aper",
256 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
257 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
258 "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
259 "dbg_trc", "dbg_apb";
264 dmac_s: dmac@f8003000 {
265 compatible = "arm,pl330", "arm,primecell";
266 reg = <0xf8003000 0x1000>;
267 interrupt-parent = <&intc>;
268 interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
269 "dma4", "dma5", "dma6", "dma7";
270 interrupts = <0 13 4>,
279 clock-names = "apb_pclk";
282 devcfg: devcfg@f8007000 {
283 compatible = "xlnx,zynq-devcfg-1.0";
284 reg = <0xf8007000 0x100>;
287 global_timer: timer@f8f00200 {
288 compatible = "arm,cortex-a9-global-timer";
289 reg = <0xf8f00200 0x20>;
290 interrupts = <1 11 0x301>;
291 interrupt-parent = <&intc>;
295 ttc0: timer@f8001000 {
296 interrupt-parent = <&intc>;
297 interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
298 compatible = "cdns,ttc";
300 reg = <0xF8001000 0x1000>;
303 ttc1: timer@f8002000 {
304 interrupt-parent = <&intc>;
305 interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
306 compatible = "cdns,ttc";
308 reg = <0xF8002000 0x1000>;
311 scutimer: timer@f8f00600 {
312 interrupt-parent = <&intc>;
313 interrupts = <1 13 0x301>;
314 compatible = "arm,cortex-a9-twd-timer";
315 reg = <0xf8f00600 0x20>;