2 * arch/arm/include/asm/assembler.h
4 * Copyright (C) 1996-2000 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This file contains arm architecture specific defines
11 * for the different processors.
13 * Do not include any C declarations in this file - it is included by
16 #ifndef __ASM_ASSEMBLER_H__
17 #define __ASM_ASSEMBLER_H__
20 #error "Only include this from assembly code"
23 #include <asm/ptrace.h>
24 #include <asm/domain.h>
25 #include <asm/opcodes-virt.h>
30 * Endian independent macros for shifting bytes within registers.
35 #define get_byte_0 lsl #0
36 #define get_byte_1 lsr #8
37 #define get_byte_2 lsr #16
38 #define get_byte_3 lsr #24
39 #define put_byte_0 lsl #0
40 #define put_byte_1 lsl #8
41 #define put_byte_2 lsl #16
42 #define put_byte_3 lsl #24
46 #define get_byte_0 lsr #24
47 #define get_byte_1 lsr #16
48 #define get_byte_2 lsr #8
49 #define get_byte_3 lsl #0
50 #define put_byte_0 lsl #24
51 #define put_byte_1 lsl #16
52 #define put_byte_2 lsl #8
53 #define put_byte_3 lsl #0
56 /* Select code for any configuration running in BE8 mode */
57 #ifdef CONFIG_CPU_ENDIAN_BE8
58 #define ARM_BE8(code...) code
60 #define ARM_BE8(code...)
64 * Data preload for architectures that support it
66 #if __LINUX_ARM_ARCH__ >= 5
67 #define PLD(code...) code
73 * This can be used to enable code to cacheline align the destination
74 * pointer when bulk writing to memory. Experiments on StrongARM and
75 * XScale didn't show this a worthwhile thing to do when the cache is not
76 * set to write-allocate (this would need further testing on XScale when WA
79 * On Feroceon there is much to gain however, regardless of cache mode.
81 #ifdef CONFIG_CPU_FEROCEON
82 #define CALGN(code...) code
84 #define CALGN(code...)
88 * Enable and disable interrupts
90 #if __LINUX_ARM_ARCH__ >= 6
91 .macro disable_irq_notrace
95 .macro enable_irq_notrace
99 .macro disable_irq_notrace
100 msr cpsr_c, #PSR_I_BIT | SVC_MODE
103 .macro enable_irq_notrace
104 msr cpsr_c, #SVC_MODE
108 .macro asm_trace_hardirqs_off
109 #if defined(CONFIG_TRACE_IRQFLAGS)
110 stmdb sp!, {r0-r3, ip, lr}
111 bl trace_hardirqs_off
112 ldmia sp!, {r0-r3, ip, lr}
116 .macro asm_trace_hardirqs_on_cond, cond
117 #if defined(CONFIG_TRACE_IRQFLAGS)
119 * actually the registers should be pushed and pop'd conditionally, but
120 * after bl the flags are certainly clobbered
122 stmdb sp!, {r0-r3, ip, lr}
123 bl\cond trace_hardirqs_on
124 ldmia sp!, {r0-r3, ip, lr}
128 .macro asm_trace_hardirqs_on
129 asm_trace_hardirqs_on_cond al
134 asm_trace_hardirqs_off
138 asm_trace_hardirqs_on
142 * Save the current IRQ state and disable IRQs. Note that this macro
143 * assumes FIQs are enabled, and that the processor is in SVC mode.
145 .macro save_and_disable_irqs, oldcpsr
150 .macro save_and_disable_irqs_notrace, oldcpsr
156 * Restore interrupt state previously stored in a register. We don't
157 * guarantee that this will preserve the flags.
159 .macro restore_irqs_notrace, oldcpsr
163 .macro restore_irqs, oldcpsr
164 tst \oldcpsr, #PSR_I_BIT
165 asm_trace_hardirqs_on_cond eq
166 restore_irqs_notrace \oldcpsr
171 .pushsection __ex_table,"a"; \
177 #define ALT_SMP(instr...) \
180 * Note: if you get assembler errors from ALT_UP() when building with
181 * CONFIG_THUMB2_KERNEL, you almost certainly need to use
182 * ALT_SMP( W(instr) ... )
184 #define ALT_UP(instr...) \
185 .pushsection ".alt.smp.init", "a" ;\
188 .if . - 9997b != 4 ;\
189 .error "ALT_UP() content must assemble to exactly 4 bytes";\
192 #define ALT_UP_B(label) \
193 .equ up_b_offset, label - 9998b ;\
194 .pushsection ".alt.smp.init", "a" ;\
196 W(b) . + up_b_offset ;\
199 #define ALT_SMP(instr...)
200 #define ALT_UP(instr...) instr
201 #define ALT_UP_B(label) b label
205 * Instruction barrier
208 #if __LINUX_ARM_ARCH__ >= 7
210 #elif __LINUX_ARM_ARCH__ == 6
211 mcr p15, 0, r0, c7, c5, 4
216 * SMP data memory barrier
220 #if __LINUX_ARM_ARCH__ >= 7
226 #elif __LINUX_ARM_ARCH__ == 6
227 ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb
229 #error Incompatible SMP platform
239 #ifdef CONFIG_THUMB2_KERNEL
240 .macro setmode, mode, reg
245 .macro setmode, mode, reg
251 * Helper macro to enter SVC mode cleanly and mask interrupts. reg is
252 * a scratch register for the macro to overwrite.
254 * This macro is intended for forcing the CPU into SVC mode at boot time.
255 * you cannot return to the original mode.
257 .macro safe_svcmode_maskall reg:req
258 #if __LINUX_ARM_ARCH__ >= 6
260 eor \reg, \reg, #HYP_MODE
262 bic \reg , \reg , #MODE_MASK
263 orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE
264 THUMB( orr \reg , \reg , #PSR_T_BIT )
266 orr \reg, \reg, #PSR_A_BIT
275 * workaround for possibly broken pre-v6 hardware
276 * (akita, Sharp Zaurus C-1000, PXA270-based)
278 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, \reg
283 * STRT/LDRT access macros with ARM and Thumb-2 variants
285 #ifdef CONFIG_THUMB2_KERNEL
287 .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER()
290 \instr\cond\()b\()\t\().w \reg, [\ptr, #\off]
292 \instr\cond\()\t\().w \reg, [\ptr, #\off]
294 .error "Unsupported inc macro argument"
297 .pushsection __ex_table,"a"
303 .macro usracc, instr, reg, ptr, inc, cond, rept, abort
304 @ explicit IT instruction needed because of the label
305 @ introduced by the USER macro
312 .error "Unsupported rept macro argument"
316 @ Slightly optimised to avoid incrementing the pointer twice
317 usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort
319 usraccoff \instr, \reg, \ptr, \inc, \inc, \cond, \abort
322 add\cond \ptr, #\rept * \inc
325 #else /* !CONFIG_THUMB2_KERNEL */
327 .macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER()
331 \instr\cond\()b\()\t \reg, [\ptr], #\inc
333 \instr\cond\()\t \reg, [\ptr], #\inc
335 .error "Unsupported inc macro argument"
338 .pushsection __ex_table,"a"
345 #endif /* CONFIG_THUMB2_KERNEL */
347 .macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
348 usracc str, \reg, \ptr, \inc, \cond, \rept, \abort
351 .macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
352 usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort
355 /* Utility macro for declaring string literals */
356 .macro string name:req, string
357 .type \name , #object
360 .size \name , . - \name
363 .macro check_uaccess, addr:req, size:req, limit:req, tmp:req, bad:req
364 #ifndef CONFIG_CPU_USE_DOMAINS
365 adds \tmp, \addr, #\size - 1
366 sbcccs \tmp, \tmp, \limit
371 #endif /* __ASM_ASSEMBLER_H__ */