2 * arch/arm/include/asm/assembler.h
4 * Copyright (C) 1996-2000 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This file contains arm architecture specific defines
11 * for the different processors.
13 * Do not include any C declarations in this file - it is included by
16 #ifndef __ASM_ASSEMBLER_H__
17 #define __ASM_ASSEMBLER_H__
20 #error "Only include this from assembly code"
23 #include <asm/ptrace.h>
24 #include <asm/domain.h>
25 #include <asm/opcodes-virt.h>
30 * Endian independent macros for shifting bytes within registers.
35 #define get_byte_0 lsl #0
36 #define get_byte_1 lsr #8
37 #define get_byte_2 lsr #16
38 #define get_byte_3 lsr #24
39 #define put_byte_0 lsl #0
40 #define put_byte_1 lsl #8
41 #define put_byte_2 lsl #16
42 #define put_byte_3 lsl #24
46 #define get_byte_0 lsr #24
47 #define get_byte_1 lsr #16
48 #define get_byte_2 lsr #8
49 #define get_byte_3 lsl #0
50 #define put_byte_0 lsl #24
51 #define put_byte_1 lsl #16
52 #define put_byte_2 lsl #8
53 #define put_byte_3 lsl #0
56 /* Select code for any configuration running in BE8 mode */
57 #ifdef CONFIG_CPU_ENDIAN_BE8
58 #define ARM_BE8(code...) code
60 #define ARM_BE8(code...)
64 * Data preload for architectures that support it
66 #if __LINUX_ARM_ARCH__ >= 5
67 #define PLD(code...) code
73 * This can be used to enable code to cacheline align the destination
74 * pointer when bulk writing to memory. Experiments on StrongARM and
75 * XScale didn't show this a worthwhile thing to do when the cache is not
76 * set to write-allocate (this would need further testing on XScale when WA
79 * On Feroceon there is much to gain however, regardless of cache mode.
81 #ifdef CONFIG_CPU_FEROCEON
82 #define CALGN(code...) code
84 #define CALGN(code...)
88 * Enable and disable interrupts
90 #if __LINUX_ARM_ARCH__ >= 6
91 .macro disable_irq_notrace
95 .macro enable_irq_notrace
99 .macro disable_irq_notrace
100 msr cpsr_c, #PSR_I_BIT | SVC_MODE
103 .macro enable_irq_notrace
104 msr cpsr_c, #SVC_MODE
108 .macro asm_trace_hardirqs_off
109 #if defined(CONFIG_TRACE_IRQFLAGS)
110 stmdb sp!, {r0-r3, ip, lr}
111 bl trace_hardirqs_off
112 ldmia sp!, {r0-r3, ip, lr}
116 .macro asm_trace_hardirqs_on_cond, cond
117 #if defined(CONFIG_TRACE_IRQFLAGS)
119 * actually the registers should be pushed and pop'd conditionally, but
120 * after bl the flags are certainly clobbered
122 stmdb sp!, {r0-r3, ip, lr}
123 bl\cond trace_hardirqs_on
124 ldmia sp!, {r0-r3, ip, lr}
128 .macro asm_trace_hardirqs_on
129 asm_trace_hardirqs_on_cond al
134 asm_trace_hardirqs_off
138 asm_trace_hardirqs_on
142 * Save the current IRQ state and disable IRQs. Note that this macro
143 * assumes FIQs are enabled, and that the processor is in SVC mode.
145 .macro save_and_disable_irqs, oldcpsr
146 #ifdef CONFIG_CPU_V7M
147 mrs \oldcpsr, primask
154 .macro save_and_disable_irqs_notrace, oldcpsr
160 * Restore interrupt state previously stored in a register. We don't
161 * guarantee that this will preserve the flags.
163 .macro restore_irqs_notrace, oldcpsr
164 #ifdef CONFIG_CPU_V7M
165 msr primask, \oldcpsr
171 .macro restore_irqs, oldcpsr
172 tst \oldcpsr, #PSR_I_BIT
173 asm_trace_hardirqs_on_cond eq
174 restore_irqs_notrace \oldcpsr
179 .pushsection __ex_table,"a"; \
185 #define ALT_SMP(instr...) \
188 * Note: if you get assembler errors from ALT_UP() when building with
189 * CONFIG_THUMB2_KERNEL, you almost certainly need to use
190 * ALT_SMP( W(instr) ... )
192 #define ALT_UP(instr...) \
193 .pushsection ".alt.smp.init", "a" ;\
196 .if . - 9997b != 4 ;\
197 .error "ALT_UP() content must assemble to exactly 4 bytes";\
200 #define ALT_UP_B(label) \
201 .equ up_b_offset, label - 9998b ;\
202 .pushsection ".alt.smp.init", "a" ;\
204 W(b) . + up_b_offset ;\
207 #define ALT_SMP(instr...)
208 #define ALT_UP(instr...) instr
209 #define ALT_UP_B(label) b label
213 * Instruction barrier
216 #if __LINUX_ARM_ARCH__ >= 7
218 #elif __LINUX_ARM_ARCH__ == 6
219 mcr p15, 0, r0, c7, c5, 4
224 * SMP data memory barrier
228 #if __LINUX_ARM_ARCH__ >= 7
234 #elif __LINUX_ARM_ARCH__ == 6
235 ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb
237 #error Incompatible SMP platform
247 #if defined(CONFIG_CPU_V7M)
249 * setmode is used to assert to be in svc mode during boot. For v7-M
250 * this is done in __v7m_setup, so setmode can be empty here.
252 .macro setmode, mode, reg
254 #elif defined(CONFIG_THUMB2_KERNEL)
255 .macro setmode, mode, reg
260 .macro setmode, mode, reg
266 * Helper macro to enter SVC mode cleanly and mask interrupts. reg is
267 * a scratch register for the macro to overwrite.
269 * This macro is intended for forcing the CPU into SVC mode at boot time.
270 * you cannot return to the original mode.
272 .macro safe_svcmode_maskall reg:req
273 #if __LINUX_ARM_ARCH__ >= 6
275 eor \reg, \reg, #HYP_MODE
277 bic \reg , \reg , #MODE_MASK
278 orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE
279 THUMB( orr \reg , \reg , #PSR_T_BIT )
281 orr \reg, \reg, #PSR_A_BIT
290 * workaround for possibly broken pre-v6 hardware
291 * (akita, Sharp Zaurus C-1000, PXA270-based)
293 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, \reg
298 * STRT/LDRT access macros with ARM and Thumb-2 variants
300 #ifdef CONFIG_THUMB2_KERNEL
302 .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER()
305 \instr\cond\()b\()\t\().w \reg, [\ptr, #\off]
307 \instr\cond\()\t\().w \reg, [\ptr, #\off]
309 .error "Unsupported inc macro argument"
312 .pushsection __ex_table,"a"
318 .macro usracc, instr, reg, ptr, inc, cond, rept, abort
319 @ explicit IT instruction needed because of the label
320 @ introduced by the USER macro
327 .error "Unsupported rept macro argument"
331 @ Slightly optimised to avoid incrementing the pointer twice
332 usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort
334 usraccoff \instr, \reg, \ptr, \inc, \inc, \cond, \abort
337 add\cond \ptr, #\rept * \inc
340 #else /* !CONFIG_THUMB2_KERNEL */
342 .macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER()
346 \instr\cond\()b\()\t \reg, [\ptr], #\inc
348 \instr\cond\()\t \reg, [\ptr], #\inc
350 .error "Unsupported inc macro argument"
353 .pushsection __ex_table,"a"
360 #endif /* CONFIG_THUMB2_KERNEL */
362 .macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
363 usracc str, \reg, \ptr, \inc, \cond, \rept, \abort
366 .macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
367 usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort
370 /* Utility macro for declaring string literals */
371 .macro string name:req, string
372 .type \name , #object
375 .size \name , . - \name
378 .macro check_uaccess, addr:req, size:req, limit:req, tmp:req, bad:req
379 #ifndef CONFIG_CPU_USE_DOMAINS
380 adds \tmp, \addr, #\size - 1
381 sbcccs \tmp, \tmp, \limit
386 #endif /* __ASM_ASSEMBLER_H__ */