2 * arch/arm/include/asm/assembler.h
4 * Copyright (C) 1996-2000 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This file contains arm architecture specific defines
11 * for the different processors.
13 * Do not include any C declarations in this file - it is included by
16 #ifndef __ASM_ASSEMBLER_H__
17 #define __ASM_ASSEMBLER_H__
20 #error "Only include this from assembly code"
23 #include <asm/ptrace.h>
24 #include <asm/domain.h>
25 #include <asm/opcodes-virt.h>
26 #include <asm/asm-offsets.h>
28 #include <asm/thread_info.h>
33 * Endian independent macros for shifting bytes within registers.
38 #define get_byte_0 lsl #0
39 #define get_byte_1 lsr #8
40 #define get_byte_2 lsr #16
41 #define get_byte_3 lsr #24
42 #define put_byte_0 lsl #0
43 #define put_byte_1 lsl #8
44 #define put_byte_2 lsl #16
45 #define put_byte_3 lsl #24
49 #define get_byte_0 lsr #24
50 #define get_byte_1 lsr #16
51 #define get_byte_2 lsr #8
52 #define get_byte_3 lsl #0
53 #define put_byte_0 lsl #24
54 #define put_byte_1 lsl #16
55 #define put_byte_2 lsl #8
56 #define put_byte_3 lsl #0
59 /* Select code for any configuration running in BE8 mode */
60 #ifdef CONFIG_CPU_ENDIAN_BE8
61 #define ARM_BE8(code...) code
63 #define ARM_BE8(code...)
67 * Data preload for architectures that support it
69 #if __LINUX_ARM_ARCH__ >= 5
70 #define PLD(code...) code
76 * This can be used to enable code to cacheline align the destination
77 * pointer when bulk writing to memory. Experiments on StrongARM and
78 * XScale didn't show this a worthwhile thing to do when the cache is not
79 * set to write-allocate (this would need further testing on XScale when WA
82 * On Feroceon there is much to gain however, regardless of cache mode.
84 #ifdef CONFIG_CPU_FEROCEON
85 #define CALGN(code...) code
87 #define CALGN(code...)
91 * Enable and disable interrupts
93 #if __LINUX_ARM_ARCH__ >= 6
94 .macro disable_irq_notrace
98 .macro enable_irq_notrace
102 .macro disable_irq_notrace
103 msr cpsr_c, #PSR_I_BIT | SVC_MODE
106 .macro enable_irq_notrace
107 msr cpsr_c, #SVC_MODE
111 .macro asm_trace_hardirqs_off, save=1
112 #if defined(CONFIG_TRACE_IRQFLAGS)
114 stmdb sp!, {r0-r3, ip, lr}
116 bl trace_hardirqs_off
118 ldmia sp!, {r0-r3, ip, lr}
123 .macro asm_trace_hardirqs_on, cond=al, save=1
124 #if defined(CONFIG_TRACE_IRQFLAGS)
126 * actually the registers should be pushed and pop'd conditionally, but
127 * after bl the flags are certainly clobbered
130 stmdb sp!, {r0-r3, ip, lr}
132 bl\cond trace_hardirqs_on
134 ldmia sp!, {r0-r3, ip, lr}
139 .macro disable_irq, save=1
141 asm_trace_hardirqs_off \save
145 asm_trace_hardirqs_on
149 * Save the current IRQ state and disable IRQs. Note that this macro
150 * assumes FIQs are enabled, and that the processor is in SVC mode.
152 .macro save_and_disable_irqs, oldcpsr
153 #ifdef CONFIG_CPU_V7M
154 mrs \oldcpsr, primask
161 .macro save_and_disable_irqs_notrace, oldcpsr
167 * Restore interrupt state previously stored in a register. We don't
168 * guarantee that this will preserve the flags.
170 .macro restore_irqs_notrace, oldcpsr
171 #ifdef CONFIG_CPU_V7M
172 msr primask, \oldcpsr
178 .macro restore_irqs, oldcpsr
179 tst \oldcpsr, #PSR_I_BIT
180 asm_trace_hardirqs_on cond=eq
181 restore_irqs_notrace \oldcpsr
185 * Assembly version of "adr rd, BSYM(sym)". This should only be used to
186 * reference local symbols in the same assembly file which are to be
187 * resolved by the assembler. Other usage is undefined.
189 .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
190 .macro badr\c, rd, sym
191 #ifdef CONFIG_THUMB2_KERNEL
200 * Get current thread_info.
202 .macro get_thread_info, rd
203 ARM( mov \rd, sp, lsr #THREAD_SIZE_ORDER + PAGE_SHIFT )
205 THUMB( lsr \rd, \rd, #THREAD_SIZE_ORDER + PAGE_SHIFT )
206 mov \rd, \rd, lsl #THREAD_SIZE_ORDER + PAGE_SHIFT
210 * Increment/decrement the preempt count.
212 #ifdef CONFIG_PREEMPT_COUNT
213 .macro inc_preempt_count, ti, tmp
214 ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count
215 add \tmp, \tmp, #1 @ increment it
216 str \tmp, [\ti, #TI_PREEMPT]
219 .macro dec_preempt_count, ti, tmp
220 ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count
221 sub \tmp, \tmp, #1 @ decrement it
222 str \tmp, [\ti, #TI_PREEMPT]
225 .macro dec_preempt_count_ti, ti, tmp
227 dec_preempt_count \ti, \tmp
230 .macro inc_preempt_count, ti, tmp
233 .macro dec_preempt_count, ti, tmp
236 .macro dec_preempt_count_ti, ti, tmp
242 .pushsection __ex_table,"a"; \
248 #define ALT_SMP(instr...) \
251 * Note: if you get assembler errors from ALT_UP() when building with
252 * CONFIG_THUMB2_KERNEL, you almost certainly need to use
253 * ALT_SMP( W(instr) ... )
255 #define ALT_UP(instr...) \
256 .pushsection ".alt.smp.init", "a" ;\
259 .if . - 9997b == 2 ;\
262 .if . - 9997b != 4 ;\
263 .error "ALT_UP() content must assemble to exactly 4 bytes";\
266 #define ALT_UP_B(label) \
267 .equ up_b_offset, label - 9998b ;\
268 .pushsection ".alt.smp.init", "a" ;\
270 W(b) . + up_b_offset ;\
273 #define ALT_SMP(instr...)
274 #define ALT_UP(instr...) instr
275 #define ALT_UP_B(label) b label
279 * Instruction barrier
282 #if __LINUX_ARM_ARCH__ >= 7
284 #elif __LINUX_ARM_ARCH__ == 6
285 mcr p15, 0, r0, c7, c5, 4
290 * SMP data memory barrier
294 #if __LINUX_ARM_ARCH__ >= 7
300 #elif __LINUX_ARM_ARCH__ == 6
301 ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb
303 #error Incompatible SMP platform
313 #if defined(CONFIG_CPU_V7M)
315 * setmode is used to assert to be in svc mode during boot. For v7-M
316 * this is done in __v7m_setup, so setmode can be empty here.
318 .macro setmode, mode, reg
320 #elif defined(CONFIG_THUMB2_KERNEL)
321 .macro setmode, mode, reg
326 .macro setmode, mode, reg
332 * Helper macro to enter SVC mode cleanly and mask interrupts. reg is
333 * a scratch register for the macro to overwrite.
335 * This macro is intended for forcing the CPU into SVC mode at boot time.
336 * you cannot return to the original mode.
338 .macro safe_svcmode_maskall reg:req
339 #if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_V7M)
341 eor \reg, \reg, #HYP_MODE
343 bic \reg , \reg , #MODE_MASK
344 orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE
345 THUMB( orr \reg , \reg , #PSR_T_BIT )
347 orr \reg, \reg, #PSR_A_BIT
356 * workaround for possibly broken pre-v6 hardware
357 * (akita, Sharp Zaurus C-1000, PXA270-based)
359 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, \reg
364 * STRT/LDRT access macros with ARM and Thumb-2 variants
366 #ifdef CONFIG_THUMB2_KERNEL
368 .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER()
371 \instr\cond\()b\()\t\().w \reg, [\ptr, #\off]
373 \instr\cond\()\t\().w \reg, [\ptr, #\off]
375 .error "Unsupported inc macro argument"
378 .pushsection __ex_table,"a"
384 .macro usracc, instr, reg, ptr, inc, cond, rept, abort
385 @ explicit IT instruction needed because of the label
386 @ introduced by the USER macro
393 .error "Unsupported rept macro argument"
397 @ Slightly optimised to avoid incrementing the pointer twice
398 usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort
400 usraccoff \instr, \reg, \ptr, \inc, \inc, \cond, \abort
403 add\cond \ptr, #\rept * \inc
406 #else /* !CONFIG_THUMB2_KERNEL */
408 .macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER()
412 \instr\cond\()b\()\t \reg, [\ptr], #\inc
414 \instr\cond\()\t \reg, [\ptr], #\inc
416 .error "Unsupported inc macro argument"
419 .pushsection __ex_table,"a"
426 #endif /* CONFIG_THUMB2_KERNEL */
428 .macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
429 usracc str, \reg, \ptr, \inc, \cond, \rept, \abort
432 .macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
433 usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort
436 /* Utility macro for declaring string literals */
437 .macro string name:req, string
438 .type \name , #object
441 .size \name , . - \name
444 .macro check_uaccess, addr:req, size:req, limit:req, tmp:req, bad:req
445 #ifndef CONFIG_CPU_USE_DOMAINS
446 adds \tmp, \addr, #\size - 1
447 sbcccs \tmp, \tmp, \limit
452 .macro uaccess_disable, tmp, isb=1
453 #ifdef CONFIG_CPU_SW_DOMAIN_PAN
455 * Whenever we re-enter userspace, the domains should always be
458 mov \tmp, #DACR_UACCESS_DISABLE
459 mcr p15, 0, \tmp, c3, c0, 0 @ Set domain register
466 .macro uaccess_enable, tmp, isb=1
467 #ifdef CONFIG_CPU_SW_DOMAIN_PAN
469 * Whenever we re-enter userspace, the domains should always be
472 mov \tmp, #DACR_UACCESS_ENABLE
473 mcr p15, 0, \tmp, c3, c0, 0
480 .macro uaccess_save, tmp
481 #ifdef CONFIG_CPU_SW_DOMAIN_PAN
482 mrc p15, 0, \tmp, c3, c0, 0
483 str \tmp, [sp, #S_FRAME_SIZE]
487 .macro uaccess_restore
488 #ifdef CONFIG_CPU_SW_DOMAIN_PAN
489 ldr r0, [sp, #S_FRAME_SIZE]
490 mcr p15, 0, r0, c3, c0, 0
494 .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
496 #if __LINUX_ARM_ARCH__ < 6
510 #ifdef CONFIG_THUMB2_KERNEL
515 #endif /* __ASM_ASSEMBLER_H__ */