2 * arch/arm/include/asm/atomic.h
4 * Copyright (C) 1996 Russell King.
5 * Copyright (C) 2002 Deep Blue Solutions Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #ifndef __ASM_ARM_ATOMIC_H
12 #define __ASM_ARM_ATOMIC_H
14 #include <linux/compiler.h>
15 #include <linux/types.h>
16 #include <linux/irqflags.h>
17 #include <asm/barrier.h>
18 #include <asm/cmpxchg.h>
20 #define ATOMIC_INIT(i) { (i) }
25 * On ARM, ordinary assignment (str instruction) doesn't clear the local
26 * strex/ldrex monitor on some implementations. The reason we can use it for
27 * atomic_set() is the clrex or dummy strex done on every exception return.
29 #define atomic_read(v) (*(volatile int *)&(v)->counter)
30 #define atomic_set(v,i) (((v)->counter) = (i))
32 #if __LINUX_ARM_ARCH__ >= 6
35 * ARMv6 UP and SMP safe atomic ops. We use load exclusive and
36 * store exclusive to ensure that these are atomic. We may loop
37 * to ensure that the update happens.
39 static inline void atomic_add(int i, atomic_t *v)
44 __asm__ __volatile__("@ atomic_add\n"
47 " strex %1, %0, [%3]\n"
50 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
51 : "r" (&v->counter), "Ir" (i)
55 static inline int atomic_add_return(int i, atomic_t *v)
62 __asm__ __volatile__("@ atomic_add_return\n"
65 " strex %1, %0, [%3]\n"
68 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
69 : "r" (&v->counter), "Ir" (i)
77 static inline void atomic_sub(int i, atomic_t *v)
82 __asm__ __volatile__("@ atomic_sub\n"
85 " strex %1, %0, [%3]\n"
88 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
89 : "r" (&v->counter), "Ir" (i)
93 static inline int atomic_sub_return(int i, atomic_t *v)
100 __asm__ __volatile__("@ atomic_sub_return\n"
101 "1: ldrex %0, [%3]\n"
103 " strex %1, %0, [%3]\n"
106 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
107 : "r" (&v->counter), "Ir" (i)
115 static inline int atomic_cmpxchg(atomic_t *ptr, int old, int new)
123 __asm__ __volatile__("@ atomic_cmpxchg\n"
127 "strexeq %0, %5, [%3]\n"
128 : "=&r" (res), "=&r" (oldval), "+Qo" (ptr->counter)
129 : "r" (&ptr->counter), "Ir" (old), "r" (new)
138 static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
140 unsigned long tmp, tmp2;
142 __asm__ __volatile__("@ atomic_clear_mask\n"
143 "1: ldrex %0, [%3]\n"
145 " strex %1, %0, [%3]\n"
148 : "=&r" (tmp), "=&r" (tmp2), "+Qo" (*addr)
149 : "r" (addr), "Ir" (mask)
153 #else /* ARM_ARCH_6 */
156 #error SMP not supported on pre-ARMv6 CPUs
159 static inline int atomic_add_return(int i, atomic_t *v)
164 raw_local_irq_save(flags);
166 v->counter = val += i;
167 raw_local_irq_restore(flags);
171 #define atomic_add(i, v) (void) atomic_add_return(i, v)
173 static inline int atomic_sub_return(int i, atomic_t *v)
178 raw_local_irq_save(flags);
180 v->counter = val -= i;
181 raw_local_irq_restore(flags);
185 #define atomic_sub(i, v) (void) atomic_sub_return(i, v)
187 static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
192 raw_local_irq_save(flags);
194 if (likely(ret == old))
196 raw_local_irq_restore(flags);
201 static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
205 raw_local_irq_save(flags);
207 raw_local_irq_restore(flags);
210 #endif /* __LINUX_ARM_ARCH__ */
212 #define atomic_xchg(v, new) (xchg(&((v)->counter), new))
214 static inline int __atomic_add_unless(atomic_t *v, int a, int u)
219 while (c != u && (old = atomic_cmpxchg((v), c, c + a)) != c)
224 #define atomic_inc(v) atomic_add(1, v)
225 #define atomic_dec(v) atomic_sub(1, v)
227 #define atomic_inc_and_test(v) (atomic_add_return(1, v) == 0)
228 #define atomic_dec_and_test(v) (atomic_sub_return(1, v) == 0)
229 #define atomic_inc_return(v) (atomic_add_return(1, v))
230 #define atomic_dec_return(v) (atomic_sub_return(1, v))
231 #define atomic_sub_and_test(i, v) (atomic_sub_return(i, v) == 0)
233 #define atomic_add_negative(i,v) (atomic_add_return(i, v) < 0)
235 #define smp_mb__before_atomic_dec() smp_mb()
236 #define smp_mb__after_atomic_dec() smp_mb()
237 #define smp_mb__before_atomic_inc() smp_mb()
238 #define smp_mb__after_atomic_inc() smp_mb()
240 #ifndef CONFIG_GENERIC_ATOMIC64
245 #define ATOMIC64_INIT(i) { (i) }
247 #ifdef CONFIG_ARM_LPAE
248 static inline long long atomic64_read(const atomic64_t *v)
252 __asm__ __volatile__("@ atomic64_read\n"
253 " ldrd %0, %H0, [%1]"
255 : "r" (&v->counter), "Qo" (v->counter)
261 static inline void atomic64_set(atomic64_t *v, long long i)
263 __asm__ __volatile__("@ atomic64_set\n"
264 " strd %2, %H2, [%1]"
266 : "r" (&v->counter), "r" (i)
270 static inline long long atomic64_read(const atomic64_t *v)
274 __asm__ __volatile__("@ atomic64_read\n"
275 " ldrexd %0, %H0, [%1]"
277 : "r" (&v->counter), "Qo" (v->counter)
283 static inline void atomic64_set(atomic64_t *v, long long i)
287 __asm__ __volatile__("@ atomic64_set\n"
288 "1: ldrexd %0, %H0, [%2]\n"
289 " strexd %0, %3, %H3, [%2]\n"
292 : "=&r" (tmp), "=Qo" (v->counter)
293 : "r" (&v->counter), "r" (i)
298 static inline void atomic64_add(long long i, atomic64_t *v)
303 __asm__ __volatile__("@ atomic64_add\n"
304 "1: ldrexd %0, %H0, [%3]\n"
306 " adc %H0, %H0, %H4\n"
307 " strexd %1, %0, %H0, [%3]\n"
310 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
311 : "r" (&v->counter), "r" (i)
315 static inline long long atomic64_add_return(long long i, atomic64_t *v)
322 __asm__ __volatile__("@ atomic64_add_return\n"
323 "1: ldrexd %0, %H0, [%3]\n"
325 " adc %H0, %H0, %H4\n"
326 " strexd %1, %0, %H0, [%3]\n"
329 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
330 : "r" (&v->counter), "r" (i)
338 static inline void atomic64_sub(long long i, atomic64_t *v)
343 __asm__ __volatile__("@ atomic64_sub\n"
344 "1: ldrexd %0, %H0, [%3]\n"
346 " sbc %H0, %H0, %H4\n"
347 " strexd %1, %0, %H0, [%3]\n"
350 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
351 : "r" (&v->counter), "r" (i)
355 static inline long long atomic64_sub_return(long long i, atomic64_t *v)
362 __asm__ __volatile__("@ atomic64_sub_return\n"
363 "1: ldrexd %0, %H0, [%3]\n"
365 " sbc %H0, %H0, %H4\n"
366 " strexd %1, %0, %H0, [%3]\n"
369 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
370 : "r" (&v->counter), "r" (i)
378 static inline long long atomic64_cmpxchg(atomic64_t *ptr, long long old,
387 __asm__ __volatile__("@ atomic64_cmpxchg\n"
388 "ldrexd %1, %H1, [%3]\n"
392 "strexdeq %0, %5, %H5, [%3]"
393 : "=&r" (res), "=&r" (oldval), "+Qo" (ptr->counter)
394 : "r" (&ptr->counter), "r" (old), "r" (new)
403 static inline long long atomic64_xchg(atomic64_t *ptr, long long new)
410 __asm__ __volatile__("@ atomic64_xchg\n"
411 "1: ldrexd %0, %H0, [%3]\n"
412 " strexd %1, %4, %H4, [%3]\n"
415 : "=&r" (result), "=&r" (tmp), "+Qo" (ptr->counter)
416 : "r" (&ptr->counter), "r" (new)
424 static inline long long atomic64_dec_if_positive(atomic64_t *v)
431 __asm__ __volatile__("@ atomic64_dec_if_positive\n"
432 "1: ldrexd %0, %H0, [%3]\n"
434 " sbc %H0, %H0, #0\n"
437 " strexd %1, %0, %H0, [%3]\n"
441 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
450 static inline int atomic64_add_unless(atomic64_t *v, long long a, long long u)
458 __asm__ __volatile__("@ atomic64_add_unless\n"
459 "1: ldrexd %0, %H0, [%4]\n"
465 " adc %H0, %H0, %H6\n"
466 " strexd %2, %0, %H0, [%4]\n"
470 : "=&r" (val), "+r" (ret), "=&r" (tmp), "+Qo" (v->counter)
471 : "r" (&v->counter), "r" (u), "r" (a)
480 #define atomic64_add_negative(a, v) (atomic64_add_return((a), (v)) < 0)
481 #define atomic64_inc(v) atomic64_add(1LL, (v))
482 #define atomic64_inc_return(v) atomic64_add_return(1LL, (v))
483 #define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
484 #define atomic64_sub_and_test(a, v) (atomic64_sub_return((a), (v)) == 0)
485 #define atomic64_dec(v) atomic64_sub(1LL, (v))
486 #define atomic64_dec_return(v) atomic64_sub_return(1LL, (v))
487 #define atomic64_dec_and_test(v) (atomic64_dec_return((v)) == 0)
488 #define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1LL, 0LL)
490 #endif /* !CONFIG_GENERIC_ATOMIC64 */