5 #include <asm-generic/pci-dma-compat.h>
6 #include <asm-generic/pci-bridge.h>
8 #include <asm/mach/pci.h> /* for pci_sys_data */
10 extern unsigned long pcibios_min_io;
11 #define PCIBIOS_MIN_IO pcibios_min_io
12 extern unsigned long pcibios_min_mem;
13 #define PCIBIOS_MIN_MEM pcibios_min_mem
15 static inline int pcibios_assign_all_busses(void)
17 return pci_has_flag(PCI_REASSIGN_ALL_RSRC);
20 #ifdef CONFIG_PCI_DOMAINS
21 static inline int pci_domain_nr(struct pci_bus *bus)
23 struct pci_sys_data *root = bus->sysdata;
28 static inline int pci_proc_domain(struct pci_bus *bus)
30 return pci_domain_nr(bus);
32 #endif /* CONFIG_PCI_DOMAINS */
34 #ifdef CONFIG_PCI_HOST_ITE8152
35 /* ITE bridge requires setting latency timer to avoid early bus access
36 termination by PIC bus mater devices
38 extern void pcibios_set_master(struct pci_dev *dev);
40 static inline void pcibios_set_master(struct pci_dev *dev)
42 /* No special bus mastering setup handling */
46 static inline void pcibios_penalize_isa_irq(int irq, int active)
48 /* We don't do dynamic PCI IRQ allocation */
52 * The PCI address space does equal the physical memory address space.
53 * The networking and block device layers use this boolean for bounce
56 #define PCI_DMA_BUS_IS_PHYS (1)
59 static inline void pci_dma_burst_advice(struct pci_dev *pdev,
60 enum pci_dma_burst_strategy *strat,
61 unsigned long *strategy_parameter)
63 *strat = PCI_DMA_BURST_INFINITY;
64 *strategy_parameter = ~0UL;
69 extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
70 enum pci_mmap_state mmap_state, int write_combine);
73 pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
74 struct resource *res);
77 pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
78 struct pci_bus_region *region);
81 * Dummy implementation; always return 0.
83 static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
88 #endif /* __KERNEL__ */