2 * linux/arch/arm/kernel/bios32.c
4 * PCI bios-type initialisation for PCI machines
6 * Bits taken from various places.
8 #include <linux/export.h>
9 #include <linux/kernel.h>
10 #include <linux/pci.h>
11 #include <linux/slab.h>
12 #include <linux/init.h>
15 #include <asm/mach-types.h>
16 #include <asm/mach/map.h>
17 #include <asm/mach/pci.h>
20 static resource_size_t (*align_resource)(struct pci_dev *dev,
21 const struct resource *res,
22 resource_size_t start,
24 resource_size_t align) = NULL;
27 * We can't use pci_get_device() here since we are
28 * called from interrupt context.
30 static void pcibios_bus_report_status(struct pci_bus *bus, u_int status_mask, int warn)
34 list_for_each_entry(dev, &bus->devices, bus_list) {
38 * ignore host bridge - we handle
41 if (dev->bus->number == 0 && dev->devfn == 0)
44 pci_read_config_word(dev, PCI_STATUS, &status);
48 if ((status & status_mask) == 0)
51 /* clear the status errors */
52 pci_write_config_word(dev, PCI_STATUS, status & status_mask);
55 printk("(%s: %04X) ", pci_name(dev), status);
58 list_for_each_entry(dev, &bus->devices, bus_list)
60 pcibios_bus_report_status(dev->subordinate, status_mask, warn);
63 void pcibios_report_status(u_int status_mask, int warn)
67 list_for_each_entry(bus, &pci_root_buses, node)
68 pcibios_bus_report_status(bus, status_mask, warn);
72 * We don't use this to fix the device, but initialisation of it.
73 * It's not the correct use for this, but it works.
74 * Note that the arbiter/ISA bridge appears to be buggy, specifically in
77 * 2. ISA bridge ping-pong
78 * 3. ISA bridge master handling of target RETRY
80 * Bug 3 is responsible for the sound DMA grinding to a halt. We now
83 static void pci_fixup_83c553(struct pci_dev *dev)
86 * Set memory region to start at address 0, and enable IO
88 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_SPACE_MEMORY);
89 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO);
91 dev->resource[0].end -= dev->resource[0].start;
92 dev->resource[0].start = 0;
95 * All memory requests from ISA to be channelled to PCI
97 pci_write_config_byte(dev, 0x48, 0xff);
100 * Enable ping-pong on bus master to ISA bridge transactions.
101 * This improves the sound DMA substantially. The fixed
102 * priority arbiter also helps (see below).
104 pci_write_config_byte(dev, 0x42, 0x01);
109 pci_write_config_byte(dev, 0x40, 0x22);
112 * We used to set the arbiter to "park on last master" (bit
113 * 1 set), but unfortunately the CyberPro does not park the
114 * bus. We must therefore park on CPU. Unfortunately, this
115 * may trigger yet another bug in the 553.
117 pci_write_config_byte(dev, 0x83, 0x02);
120 * Make the ISA DMA request lowest priority, and disable
121 * rotating priorities completely.
123 pci_write_config_byte(dev, 0x80, 0x11);
124 pci_write_config_byte(dev, 0x81, 0x00);
127 * Route INTA input to IRQ 11, and set IRQ11 to be level
130 pci_write_config_word(dev, 0x44, 0xb000);
133 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_83C553, pci_fixup_83c553);
135 static void pci_fixup_unassign(struct pci_dev *dev)
137 dev->resource[0].end -= dev->resource[0].start;
138 dev->resource[0].start = 0;
140 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND2, PCI_DEVICE_ID_WINBOND2_89C940F, pci_fixup_unassign);
143 * Prevent the PCI layer from seeing the resources allocated to this device
144 * if it is the host bridge by marking it as such. These resources are of
145 * no consequence to the PCI layer (they are handled elsewhere).
147 static void pci_fixup_dec21285(struct pci_dev *dev)
151 if (dev->devfn == 0) {
153 dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
154 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
155 dev->resource[i].start = 0;
156 dev->resource[i].end = 0;
157 dev->resource[i].flags = 0;
161 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21285, pci_fixup_dec21285);
164 * PCI IDE controllers use non-standard I/O port decoding, respect it.
166 static void pci_fixup_ide_bases(struct pci_dev *dev)
171 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
174 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
175 r = dev->resource + i;
176 if ((r->start & ~0x80) == 0x374) {
182 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
185 * Put the DEC21142 to sleep
187 static void pci_fixup_dec21142(struct pci_dev *dev)
189 pci_write_config_dword(dev, 0x40, 0x80000000);
191 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142, pci_fixup_dec21142);
194 * The CY82C693 needs some rather major fixups to ensure that it does
195 * the right thing. Idea from the Alpha people, with a few additions.
197 * We ensure that the IDE base registers are set to 1f0/3f4 for the
198 * primary bus, and 170/374 for the secondary bus. Also, hide them
199 * from the PCI subsystem view as well so we won't try to perform
200 * our own auto-configuration on them.
202 * In addition, we ensure that the PCI IDE interrupts are routed to
203 * IRQ 14 and IRQ 15 respectively.
205 * The above gets us to a point where the IDE on this device is
206 * functional. However, The CY82C693U _does not work_ in bus
207 * master mode without locking the PCI bus solid.
209 static void pci_fixup_cy82c693(struct pci_dev *dev)
211 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
214 if (dev->class & 0x80) { /* primary */
217 } else { /* secondary */
222 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
223 base0 | PCI_BASE_ADDRESS_SPACE_IO);
224 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1,
225 base1 | PCI_BASE_ADDRESS_SPACE_IO);
227 dev->resource[0].start = 0;
228 dev->resource[0].end = 0;
229 dev->resource[0].flags = 0;
231 dev->resource[1].start = 0;
232 dev->resource[1].end = 0;
233 dev->resource[1].flags = 0;
234 } else if (PCI_FUNC(dev->devfn) == 0) {
236 * Setup IDE IRQ routing.
238 pci_write_config_byte(dev, 0x4b, 14);
239 pci_write_config_byte(dev, 0x4c, 15);
242 * Disable FREQACK handshake, enable USB.
244 pci_write_config_byte(dev, 0x4d, 0x41);
247 * Enable PCI retry, and PCI post-write buffer.
249 pci_write_config_byte(dev, 0x44, 0x17);
252 * Enable ISA master and DMA post write buffering.
254 pci_write_config_byte(dev, 0x45, 0x03);
257 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_fixup_cy82c693);
259 static void pci_fixup_it8152(struct pci_dev *dev)
262 /* fixup for ITE 8152 devices */
263 /* FIXME: add defines for class 0x68000 and 0x80103 */
264 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST ||
265 dev->class == 0x68000 ||
266 dev->class == 0x80103) {
267 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
268 dev->resource[i].start = 0;
269 dev->resource[i].end = 0;
270 dev->resource[i].flags = 0;
274 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8152, pci_fixup_it8152);
277 * If the bus contains any of these devices, then we must not turn on
278 * parity checking of any kind. Currently this is CyberPro 20x0 only.
280 static inline int pdev_bad_for_parity(struct pci_dev *dev)
282 return ((dev->vendor == PCI_VENDOR_ID_INTERG &&
283 (dev->device == PCI_DEVICE_ID_INTERG_2000 ||
284 dev->device == PCI_DEVICE_ID_INTERG_2010)) ||
285 (dev->vendor == PCI_VENDOR_ID_ITE &&
286 dev->device == PCI_DEVICE_ID_ITE_8152));
291 * pcibios_fixup_bus - Called after each bus is probed,
292 * but before its children are examined.
294 void pcibios_fixup_bus(struct pci_bus *bus)
297 u16 features = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_FAST_BACK;
300 * Walk the devices on this bus, working out what we can
303 list_for_each_entry(dev, &bus->devices, bus_list) {
306 pci_read_config_word(dev, PCI_STATUS, &status);
309 * If any device on this bus does not support fast back
310 * to back transfers, then the bus as a whole is not able
311 * to support them. Having fast back to back transfers
312 * on saves us one PCI cycle per transaction.
314 if (!(status & PCI_STATUS_FAST_BACK))
315 features &= ~PCI_COMMAND_FAST_BACK;
317 if (pdev_bad_for_parity(dev))
318 features &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
320 switch (dev->class >> 8) {
321 case PCI_CLASS_BRIDGE_PCI:
322 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &status);
323 status |= PCI_BRIDGE_CTL_PARITY|PCI_BRIDGE_CTL_MASTER_ABORT;
324 status &= ~(PCI_BRIDGE_CTL_BUS_RESET|PCI_BRIDGE_CTL_FAST_BACK);
325 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, status);
328 case PCI_CLASS_BRIDGE_CARDBUS:
329 pci_read_config_word(dev, PCI_CB_BRIDGE_CONTROL, &status);
330 status |= PCI_CB_BRIDGE_CTL_PARITY|PCI_CB_BRIDGE_CTL_MASTER_ABORT;
331 pci_write_config_word(dev, PCI_CB_BRIDGE_CONTROL, status);
337 * Now walk the devices again, this time setting them up.
339 list_for_each_entry(dev, &bus->devices, bus_list) {
342 pci_read_config_word(dev, PCI_COMMAND, &cmd);
344 pci_write_config_word(dev, PCI_COMMAND, cmd);
346 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
347 L1_CACHE_BYTES >> 2);
351 * Propagate the flags to the PCI bridge.
353 if (bus->self && bus->self->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
354 if (features & PCI_COMMAND_FAST_BACK)
355 bus->bridge_ctl |= PCI_BRIDGE_CTL_FAST_BACK;
356 if (features & PCI_COMMAND_PARITY)
357 bus->bridge_ctl |= PCI_BRIDGE_CTL_PARITY;
361 * Report what we did for this bus
363 pr_info("PCI: bus%d: Fast back to back transfers %sabled\n",
364 bus->number, (features & PCI_COMMAND_FAST_BACK) ? "en" : "dis");
366 EXPORT_SYMBOL(pcibios_fixup_bus);
369 * Swizzle the device pin each time we cross a bridge. If a platform does
370 * not provide a swizzle function, we perform the standard PCI swizzling.
372 * The default swizzling walks up the bus tree one level at a time, applying
373 * the standard swizzle function at each step, stopping when it finds the PCI
374 * root bus. This will return the slot number of the bridge device on the
375 * root bus and the interrupt pin on that device which should correspond
376 * with the downstream device interrupt.
378 * Platforms may override this, in which case the slot and pin returned
379 * depend entirely on the platform code. However, please note that the
380 * PCI standard swizzle is implemented on plug-in cards and Cardbus based
381 * PCI extenders, so it can not be ignored.
383 static u8 pcibios_swizzle(struct pci_dev *dev, u8 *pin)
385 struct pci_sys_data *sys = dev->sysdata;
386 int slot, oldpin = *pin;
389 slot = sys->swizzle(dev, pin);
391 slot = pci_common_swizzle(dev, pin);
394 printk("PCI: %s swizzling pin %d => pin %d slot %d\n",
395 pci_name(dev), oldpin, *pin, slot);
401 * Map a slot/pin to an IRQ.
403 static int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
405 struct pci_sys_data *sys = dev->sysdata;
409 irq = sys->map_irq(dev, slot, pin);
412 printk("PCI: %s mapping slot %d pin %d => irq %d\n",
413 pci_name(dev), slot, pin, irq);
418 static int pcibios_init_resources(int busnr, struct pci_sys_data *sys)
421 struct resource_entry *window;
423 if (list_empty(&sys->resources)) {
424 pci_add_resource_offset(&sys->resources,
425 &iomem_resource, sys->mem_offset);
428 resource_list_for_each_entry(window, &sys->resources)
429 if (resource_type(window->res) == IORESOURCE_IO)
432 sys->io_res.start = (busnr * SZ_64K) ? : pcibios_min_io;
433 sys->io_res.end = (busnr + 1) * SZ_64K - 1;
434 sys->io_res.flags = IORESOURCE_IO;
435 sys->io_res.name = sys->io_res_name;
436 sprintf(sys->io_res_name, "PCI%d I/O", busnr);
438 ret = request_resource(&ioport_resource, &sys->io_res);
440 pr_err("PCI: unable to allocate I/O port region (%d)\n", ret);
443 pci_add_resource_offset(&sys->resources, &sys->io_res,
449 static void pcibios_init_hw(struct device *parent, struct hw_pci *hw,
450 struct list_head *head)
452 struct pci_sys_data *sys = NULL;
456 for (nr = busnr = 0; nr < hw->nr_controllers; nr++) {
457 sys = kzalloc(sizeof(struct pci_sys_data), GFP_KERNEL);
458 if (WARN(!sys, "PCI: unable to allocate sys data!"))
462 sys->swizzle = hw->swizzle;
463 sys->map_irq = hw->map_irq;
464 align_resource = hw->align_resource;
465 INIT_LIST_HEAD(&sys->resources);
467 if (hw->private_data)
468 sys->private_data = hw->private_data[nr];
470 ret = hw->setup(nr, sys);
473 ret = pcibios_init_resources(nr, sys);
480 sys->bus = hw->scan(nr, sys);
482 sys->bus = pci_scan_root_bus_msi(parent,
483 sys->busnr, hw->ops, sys,
484 &sys->resources, hw->msi_ctrl);
486 if (WARN(!sys->bus, "PCI: unable to scan bus!")) {
491 busnr = sys->bus->busn_res.end + 1;
493 list_add(&sys->node, head);
502 void pci_common_init_dev(struct device *parent, struct hw_pci *hw)
504 struct pci_sys_data *sys;
507 pci_add_flags(PCI_REASSIGN_ALL_RSRC);
510 pcibios_init_hw(parent, hw, &head);
514 pci_fixup_irqs(pcibios_swizzle, pcibios_map_irq);
516 list_for_each_entry(sys, &head, node) {
517 struct pci_bus *bus = sys->bus;
519 if (!pci_has_flag(PCI_PROBE_ONLY)) {
520 struct pci_bus *child;
523 * Size the bridge windows.
525 pci_bus_size_bridges(bus);
530 pci_bus_assign_resources(bus);
532 list_for_each_entry(child, &bus->children, node)
533 pcie_bus_configure_settings(child);
536 * Tell drivers about devices found.
538 pci_bus_add_devices(bus);
542 #ifndef CONFIG_PCI_HOST_ITE8152
543 void pcibios_set_master(struct pci_dev *dev)
545 /* No special bus mastering setup handling */
549 char * __init pcibios_setup(char *str)
551 if (!strcmp(str, "debug")) {
554 } else if (!strcmp(str, "firmware")) {
555 pci_add_flags(PCI_PROBE_ONLY);
562 * From arch/i386/kernel/pci-i386.c:
564 * We need to avoid collisions with `mirrored' VGA ports
565 * and other strange ISA hardware, so we always want the
566 * addresses to be allocated in the 0x000-0x0ff region
569 * Why? Because some silly external IO cards only decode
570 * the low 10 bits of the IO address. The 0x00-0xff region
571 * is reserved for motherboard devices that decode all 16
572 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
573 * but we want to try to avoid allocating at 0x2900-0x2bff
574 * which might be mirrored at 0x0100-0x03ff..
576 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
577 resource_size_t size, resource_size_t align)
579 struct pci_dev *dev = data;
580 resource_size_t start = res->start;
582 if (res->flags & IORESOURCE_IO && start & 0x300)
583 start = (start + 0x3ff) & ~0x3ff;
585 start = (start + align - 1) & ~(align - 1);
588 return align_resource(dev, res, start, size, align);
594 * pcibios_enable_device - Enable I/O and memory.
595 * @dev: PCI device to be enabled
597 int pcibios_enable_device(struct pci_dev *dev, int mask)
599 if (pci_has_flag(PCI_PROBE_ONLY))
602 return pci_enable_resources(dev, mask);
605 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
606 enum pci_mmap_state mmap_state, int write_combine)
608 if (mmap_state == pci_mmap_io)
614 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
616 if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
617 vma->vm_end - vma->vm_start,
624 void __init pci_map_io_early(unsigned long pfn)
626 struct map_desc pci_io_desc = {
627 .virtual = PCI_IO_VIRT_BASE,
632 pci_io_desc.pfn = pfn;
633 iotable_init(&pci_io_desc, 1);