2 * linux/arch/arm/kernel/entry-armv.S
4 * Copyright (C) 1996,1997,1998 Russell King.
5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
6 * nommu support by Hyok S. Choi (hyok.choi@samsung.com)
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * Low-level vector interface routines
14 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction
15 * that causes it to save wrong values... Be aware!
18 #include <asm/assembler.h>
19 #include <asm/memory.h>
20 #include <asm/glue-df.h>
21 #include <asm/glue-pf.h>
22 #include <asm/vfpmacros.h>
23 #ifndef CONFIG_MULTI_IRQ_HANDLER
24 #include <mach/entry-macro.S>
26 #include <asm/thread_notify.h>
27 #include <asm/unwind.h>
28 #include <asm/unistd.h>
30 #include <asm/system_info.h>
32 #include "entry-header.S"
33 #include <asm/entry-macro-multi.S>
39 #ifdef CONFIG_MULTI_IRQ_HANDLER
40 ldr r1, =handle_arch_irq
45 arch_irq_handler_default
51 @ PABORT handler takes pt_regs in r2, fault address in r4 and psr in r5
55 ldr pc, [ip, #PROCESSOR_PABT_FUNC]
64 @ Call the processor-specific abort handler:
67 @ r4 - aborted context pc
68 @ r5 - aborted context psr
70 @ The abort handler must return the aborted address in r0, and
71 @ the fault status register in r1. r9 must be preserved.
76 ldr pc, [ip, #PROCESSOR_DABT_FUNC]
83 .section .kprobes.text,"ax",%progbits
89 * Invalid mode handlers
91 .macro inv_entry, reason
92 sub sp, sp, #S_FRAME_SIZE
93 ARM( stmib sp, {r1 - lr} )
94 THUMB( stmia sp, {r0 - r12} )
95 THUMB( str sp, [sp, #S_SP] )
96 THUMB( str lr, [sp, #S_LR] )
101 inv_entry BAD_PREFETCH
103 ENDPROC(__pabt_invalid)
108 ENDPROC(__dabt_invalid)
113 ENDPROC(__irq_invalid)
116 inv_entry BAD_UNDEFINSTR
119 @ XXX fall through to common_invalid
123 @ common_invalid - generic code for failed exception (re-entrant version of handlers)
129 add r0, sp, #S_PC @ here for interlock avoidance
130 mov r7, #-1 @ "" "" "" ""
131 str r4, [sp] @ save preserved r0
132 stmia r0, {r5 - r7} @ lr_<exception>,
133 @ cpsr_<exception>, "old_r0"
137 ENDPROC(__und_invalid)
143 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
144 #define SPFIX(code...) code
146 #define SPFIX(code...)
149 .macro svc_entry, stack_hole=0, trace=1
151 UNWIND(.save {r0 - pc} )
152 sub sp, sp, #(S_FRAME_SIZE + \stack_hole - 4)
153 #ifdef CONFIG_THUMB2_KERNEL
154 SPFIX( str r0, [sp] ) @ temporarily saved
156 SPFIX( tst r0, #4 ) @ test original stack alignment
157 SPFIX( ldr r0, [sp] ) @ restored
161 SPFIX( subeq sp, sp, #4 )
165 add r7, sp, #S_SP - 4 @ here for interlock avoidance
166 mov r6, #-1 @ "" "" "" ""
167 add r2, sp, #(S_FRAME_SIZE + \stack_hole - 4)
168 SPFIX( addeq r2, r2, #4 )
169 str r3, [sp, #-4]! @ save the "real" r0 copied
170 @ from the exception stack
175 @ We are now ready to fill in the remaining blanks on the stack:
179 @ r4 - lr_<exception>, already fixed up for correct return/restart
180 @ r5 - spsr_<exception>
181 @ r6 - orig_r0 (see pt_regs definition in ptrace.h)
186 #ifdef CONFIG_TRACE_IRQFLAGS
187 bl trace_hardirqs_off
197 THUMB( ldr r5, [sp, #S_PSR] ) @ potentially updated CPSR
198 svc_exit r5 @ return from exception
207 #ifdef CONFIG_PREEMPT
209 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
210 ldr r0, [tsk, #TI_FLAGS] @ get flags
211 teq r8, #0 @ if preempt count != 0
212 movne r0, #0 @ force flags to 0
213 tst r0, #_TIF_NEED_RESCHED
217 svc_exit r5, irq = 1 @ return from exception
223 #ifdef CONFIG_PREEMPT
226 1: bl preempt_schedule_irq @ irq en/disable is done inside
227 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS
228 tst r0, #_TIF_NEED_RESCHED
234 @ Correct the PC such that it is pointing at the instruction
235 @ which caused the fault. If the faulting instruction was ARM
236 @ the PC will be pointing at the next instruction, and have to
237 @ subtract 4. Otherwise, it is Thumb, and the PC will be
238 @ pointing at the second half of the Thumb instruction. We
239 @ have to subtract 2.
248 #ifdef CONFIG_KPROBES
249 @ If a kprobe is about to simulate a "stmdb sp..." instruction,
250 @ it obviously needs free stack space which then will belong to
257 @ call emulation code, which returns using r9 if it has emulated
258 @ the instruction, or the more conventional lr if we are to treat
259 @ this as a real undefined instruction
263 #ifndef CONFIG_THUMB2_KERNEL
267 ldrh r0, [r4, #-2] @ Thumb instruction at LR - 2
268 cmp r0, #0xe800 @ 32-bit instruction if xx >= 0
270 ldrh r9, [r4] @ bottom 16 bits
273 orr r0, r9, r0, lsl #16
275 adr r9, BSYM(__und_svc_finish)
279 mov r1, #4 @ PC correction to apply
281 mov r0, sp @ struct pt_regs *regs
285 ldr r5, [sp, #S_PSR] @ Get SVC cpsr
286 svc_exit r5 @ return from exception
295 svc_exit r5 @ return from exception
302 mov r0, sp @ struct pt_regs *regs
319 * Abort mode handlers
323 @ Taking a FIQ in abort mode is similar to taking a FIQ in SVC mode
324 @ and reuses the same macros. However in abort mode we must also
325 @ save/restore lr_abt and spsr_abt to make nested aborts safe.
331 ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
332 THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
333 THUMB( msr cpsr_c, r0 )
334 mov r1, lr @ Save lr_abt
335 mrs r2, spsr @ Save spsr_abt, abort is now safe
336 ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
337 THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
338 THUMB( msr cpsr_c, r0 )
341 add r0, sp, #8 @ struct pt_regs *regs
345 ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
346 THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
347 THUMB( msr cpsr_c, r0 )
348 mov lr, r1 @ Restore lr_abt, abort is unsafe
349 msr spsr_cxsf, r2 @ Restore spsr_abt
350 ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
351 THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
352 THUMB( msr cpsr_c, r0 )
361 * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE
364 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7)
365 #error "sizeof(struct pt_regs) must be a multiple of 8"
368 .macro usr_entry, trace=1
370 UNWIND(.cantunwind ) @ don't unwind the user space
371 sub sp, sp, #S_FRAME_SIZE
372 ARM( stmib sp, {r1 - r12} )
373 THUMB( stmia sp, {r0 - r12} )
375 ATRAP( mrc p15, 0, r7, c1, c0, 0)
376 ATRAP( ldr r8, .LCcralign)
379 add r0, sp, #S_PC @ here for interlock avoidance
380 mov r6, #-1 @ "" "" "" ""
382 str r3, [sp] @ save the "real" r0 copied
383 @ from the exception stack
385 ATRAP( ldr r8, [r8, #0])
388 @ We are now ready to fill in the remaining blanks on the stack:
390 @ r4 - lr_<exception>, already fixed up for correct return/restart
391 @ r5 - spsr_<exception>
392 @ r6 - orig_r0 (see pt_regs definition in ptrace.h)
394 @ Also, separately save sp_usr and lr_usr
397 ARM( stmdb r0, {sp, lr}^ )
398 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC )
400 @ Enable the alignment trap while in kernel mode
402 ATRAP( mcrne p15, 0, r8, c1, c0, 0)
405 @ Clear FP to mark the first stack frame
410 #ifdef CONFIG_IRQSOFF_TRACER
411 bl trace_hardirqs_off
413 ct_user_exit save = 0
417 .macro kuser_cmpxchg_check
418 #if !defined(CONFIG_CPU_32v6K) && defined(CONFIG_KUSER_HELPERS) && \
419 !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
421 #warning "NPTL on non MMU needs fixing"
423 @ Make sure our user space atomic helper is restarted
424 @ if it was interrupted in a critical region. Here we
425 @ perform a quick test inline since it should be false
426 @ 99.9999% of the time. The rest is done out of line.
428 blhs kuser_cmpxchg64_fixup
450 b ret_to_user_from_irq
463 @ r2 = regs->ARM_pc, which is either 2 or 4 bytes ahead of the
464 @ faulting instruction depending on Thumb mode.
465 @ r3 = regs->ARM_cpsr
467 @ The emulation code returns using r9 if it has emulated the
468 @ instruction, or the more conventional lr if we are to treat
469 @ this as a real undefined instruction
471 adr r9, BSYM(ret_from_exception)
473 @ IRQs must be enabled before attempting to read the instruction from
474 @ user space since that could cause a page/translation fault if the
475 @ page table was modified by another CPU.
478 tst r3, #PSR_T_BIT @ Thumb mode?
480 sub r4, r2, #4 @ ARM instr at LR - 4
482 ARM_BE8(rev r0, r0) @ little endian instruction
484 @ r0 = 32-bit ARM instruction which caused the exception
485 @ r2 = PC value for the following instruction (:= regs->ARM_pc)
486 @ r4 = PC value for the faulting instruction
487 @ lr = 32-bit undefined instruction function
488 adr lr, BSYM(__und_usr_fault_32)
493 sub r4, r2, #2 @ First half of thumb instr at LR - 2
494 #if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7
496 * Thumb-2 instruction handling. Note that because pre-v6 and >= v6 platforms
497 * can never be supported in a single kernel, this code is not applicable at
498 * all when __LINUX_ARM_ARCH__ < 6. This allows simplifying assumptions to be
499 * made about .arch directives.
501 #if __LINUX_ARM_ARCH__ < 7
502 /* If the target CPU may not be Thumb-2-capable, a run-time check is needed: */
503 #define NEED_CPU_ARCHITECTURE
504 ldr r5, .LCcpu_architecture
506 cmp r5, #CPU_ARCH_ARMv7
507 blo __und_usr_fault_16 @ 16bit undefined instruction
509 * The following code won't get run unless the running CPU really is v7, so
510 * coding round the lack of ldrht on older arches is pointless. Temporarily
511 * override the assembler target arch with the minimum required instead:
516 ARM_BE8(rev16 r5, r5) @ little endian instruction
517 cmp r5, #0xe800 @ 32bit instruction if xx != 0
518 blo __und_usr_fault_16 @ 16bit undefined instruction
520 ARM_BE8(rev16 r0, r0) @ little endian instruction
521 add r2, r2, #2 @ r2 is PC + 2, make it PC + 4
522 str r2, [sp, #S_PC] @ it's a 2x16bit instr, update
523 orr r0, r0, r5, lsl #16
524 adr lr, BSYM(__und_usr_fault_32)
525 @ r0 = the two 16-bit Thumb instructions which caused the exception
526 @ r2 = PC value for the following Thumb instruction (:= regs->ARM_pc)
527 @ r4 = PC value for the first 16-bit Thumb instruction
528 @ lr = 32bit undefined instruction function
530 #if __LINUX_ARM_ARCH__ < 7
531 /* If the target arch was overridden, change it back: */
532 #ifdef CONFIG_CPU_32v6K
537 #endif /* __LINUX_ARM_ARCH__ < 7 */
538 #else /* !(CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7) */
545 * The out of line fixup for the ldrt instructions above.
547 .pushsection .fixup, "ax"
549 4: str r4, [sp, #S_PC] @ retry current instruction
552 .pushsection __ex_table,"a"
554 #if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7
561 * Check whether the instruction is a co-processor instruction.
562 * If yes, we need to call the relevant co-processor handler.
564 * Note that we don't do a full check here for the co-processor
565 * instructions; all instructions with bit 27 set are well
566 * defined. The only instructions that should fault are the
567 * co-processor instructions. However, we have to watch out
568 * for the ARM6/ARM7 SWI bug.
570 * NEON is a special case that has to be handled here. Not all
571 * NEON instructions are co-processor instructions, so we have
572 * to make a special case of checking for them. Plus, there's
573 * five groups of them, so we have a table of mask/opcode pairs
574 * to check against, and if any match then we branch off into the
577 * Emulators may wish to make use of the following registers:
578 * r0 = instruction opcode (32-bit ARM or two 16-bit Thumb)
579 * r2 = PC value to resume execution after successful emulation
580 * r9 = normal "successful" return address
581 * r10 = this threads thread_info structure
582 * lr = unrecognised instruction return address
583 * IRQs enabled, FIQs enabled.
586 @ Fall-through from Thumb-2 __und_usr
589 get_thread_info r10 @ get current thread
590 adr r6, .LCneon_thumb_opcodes
594 get_thread_info r10 @ get current thread
596 adr r6, .LCneon_arm_opcodes
597 2: ldr r5, [r6], #4 @ mask value
598 ldr r7, [r6], #4 @ opcode bits matching in mask
599 cmp r5, #0 @ end mask?
602 cmp r8, r7 @ NEON instruction?
605 strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used
606 strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used
607 b do_vfp @ let VFP handler handle this
610 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
611 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2
613 and r8, r0, #0x00000f00 @ mask out CP number
614 THUMB( lsr r8, r8, #8 )
616 add r6, r10, #TI_USED_CP
617 ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[]
618 THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[]
620 @ Test if we need to give access to iWMMXt coprocessors
621 ldr r5, [r10, #TI_FLAGS]
622 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
623 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1)
624 bcs iwmmxt_task_enable
626 ARM( add pc, pc, r8, lsr #6 )
627 THUMB( lsl r8, r8, #2 )
632 W(b) do_fpe @ CP#1 (FPE)
633 W(b) do_fpe @ CP#2 (FPE)
636 b crunch_task_enable @ CP#4 (MaverickCrunch)
637 b crunch_task_enable @ CP#5 (MaverickCrunch)
638 b crunch_task_enable @ CP#6 (MaverickCrunch)
648 W(b) do_vfp @ CP#10 (VFP)
649 W(b) do_vfp @ CP#11 (VFP)
651 ret.w lr @ CP#10 (VFP)
652 ret.w lr @ CP#11 (VFP)
656 ret.w lr @ CP#14 (Debug)
657 ret.w lr @ CP#15 (Control)
659 #ifdef NEED_CPU_ARCHITECTURE
662 .word __cpu_architecture
669 .word 0xfe000000 @ mask
670 .word 0xf2000000 @ opcode
672 .word 0xff100000 @ mask
673 .word 0xf4000000 @ opcode
675 .word 0x00000000 @ mask
676 .word 0x00000000 @ opcode
678 .LCneon_thumb_opcodes:
679 .word 0xef000000 @ mask
680 .word 0xef000000 @ opcode
682 .word 0xff100000 @ mask
683 .word 0xf9000000 @ opcode
685 .word 0x00000000 @ mask
686 .word 0x00000000 @ opcode
691 add r10, r10, #TI_FPSTATE @ r10 = workspace
692 ldr pc, [r4] @ Call FP module USR entry point
695 * The FP module is called with these registers set:
698 * r9 = normal "successful" return address
700 * lr = unrecognised FP instruction return address
718 adr lr, BSYM(ret_from_exception)
720 ENDPROC(__und_usr_fault_32)
721 ENDPROC(__und_usr_fault_16)
731 * This is the return code to user mode for abort handlers
733 ENTRY(ret_from_exception)
741 ENDPROC(ret_from_exception)
747 mov r0, sp @ struct pt_regs *regs
750 restore_user_regs fast = 0, offset = 0
755 * Register switch for ARMv3 and ARMv4 processors
756 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
757 * previous and next are guaranteed not to be the same.
762 add ip, r1, #TI_CPU_SAVE
763 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack
764 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack
765 THUMB( str sp, [ip], #4 )
766 THUMB( str lr, [ip], #4 )
767 ldr r4, [r2, #TI_TP_VALUE]
768 ldr r5, [r2, #TI_TP_VALUE + 4]
769 #ifdef CONFIG_CPU_USE_DOMAINS
770 ldr r6, [r2, #TI_CPU_DOMAIN]
772 switch_tls r1, r4, r5, r3, r7
773 #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
774 ldr r7, [r2, #TI_TASK]
775 ldr r8, =__stack_chk_guard
776 ldr r7, [r7, #TSK_STACK_CANARY]
778 #ifdef CONFIG_CPU_USE_DOMAINS
779 mcr p15, 0, r6, c3, c0, 0 @ Set domain register
782 add r4, r2, #TI_CPU_SAVE
783 ldr r0, =thread_notify_head
784 mov r1, #THREAD_NOTIFY_SWITCH
785 bl atomic_notifier_call_chain
786 #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
791 ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously
792 THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously
793 THUMB( ldr sp, [ip], #4 )
794 THUMB( ldr pc, [ip] )
803 * Each segment is 32-byte aligned and will be moved to the top of the high
804 * vector page. New segments (if ever needed) must be added in front of
805 * existing ones. This mechanism should be used only for things that are
806 * really small and justified, and not be abused freely.
808 * See Documentation/arm/kernel_user_helpers.txt for formal definitions.
813 #ifdef CONFIG_ARM_THUMB
820 .macro kuser_pad, sym, size
822 .rept 4 - (. - \sym) & 3
826 .rept (\size - (. - \sym)) / 4
831 #ifdef CONFIG_KUSER_HELPERS
833 .globl __kuser_helper_start
834 __kuser_helper_start:
837 * Due to the length of some sequences, __kuser_cmpxchg64 spans 2 regular
838 * kuser "slots", therefore 0xffff0f80 is not used as a valid entry point.
841 __kuser_cmpxchg64: @ 0xffff0f60
843 #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
846 * Poor you. No fast solution possible...
847 * The kernel itself must perform the operation.
848 * A special ghost syscall is used for that (see traps.c).
851 ldr r7, 1f @ it's 20 bits
852 swi __ARM_NR_cmpxchg64
854 1: .word __ARM_NR_cmpxchg64
856 #elif defined(CONFIG_CPU_32v6K)
858 stmfd sp!, {r4, r5, r6, r7}
859 ldrd r4, r5, [r0] @ load old val
860 ldrd r6, r7, [r1] @ load new val
862 1: ldrexd r0, r1, [r2] @ load current val
863 eors r3, r0, r4 @ compare with oldval (1)
864 eoreqs r3, r1, r5 @ compare with oldval (2)
865 strexdeq r3, r6, r7, [r2] @ store newval if eq
866 teqeq r3, #1 @ success?
867 beq 1b @ if no then retry
869 rsbs r0, r3, #0 @ set returned val and C flag
870 ldmfd sp!, {r4, r5, r6, r7}
873 #elif !defined(CONFIG_SMP)
878 * The only thing that can break atomicity in this cmpxchg64
879 * implementation is either an IRQ or a data abort exception
880 * causing another process/thread to be scheduled in the middle of
881 * the critical sequence. The same strategy as for cmpxchg is used.
883 stmfd sp!, {r4, r5, r6, lr}
884 ldmia r0, {r4, r5} @ load old val
885 ldmia r1, {r6, lr} @ load new val
886 1: ldmia r2, {r0, r1} @ load current val
887 eors r3, r0, r4 @ compare with oldval (1)
888 eoreqs r3, r1, r5 @ compare with oldval (2)
889 2: stmeqia r2, {r6, lr} @ store newval if eq
890 rsbs r0, r3, #0 @ set return val and C flag
891 ldmfd sp!, {r4, r5, r6, pc}
894 kuser_cmpxchg64_fixup:
895 @ Called from kuser_cmpxchg_fixup.
896 @ r4 = address of interrupted insn (must be preserved).
897 @ sp = saved regs. r7 and r8 are clobbered.
898 @ 1b = first critical insn, 2b = last critical insn.
899 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b.
901 sub r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64)))
903 rsbcss r8, r8, #(2b - 1b)
904 strcs r7, [sp, #S_PC]
905 #if __LINUX_ARM_ARCH__ < 6
906 bcc kuser_cmpxchg32_fixup
912 #warning "NPTL on non MMU needs fixing"
919 #error "incoherent kernel configuration"
922 kuser_pad __kuser_cmpxchg64, 64
924 __kuser_memory_barrier: @ 0xffff0fa0
928 kuser_pad __kuser_memory_barrier, 32
930 __kuser_cmpxchg: @ 0xffff0fc0
932 #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
935 * Poor you. No fast solution possible...
936 * The kernel itself must perform the operation.
937 * A special ghost syscall is used for that (see traps.c).
940 ldr r7, 1f @ it's 20 bits
943 1: .word __ARM_NR_cmpxchg
945 #elif __LINUX_ARM_ARCH__ < 6
950 * The only thing that can break atomicity in this cmpxchg
951 * implementation is either an IRQ or a data abort exception
952 * causing another process/thread to be scheduled in the middle
953 * of the critical sequence. To prevent this, code is added to
954 * the IRQ and data abort exception handlers to set the pc back
955 * to the beginning of the critical section if it is found to be
956 * within that critical section (see kuser_cmpxchg_fixup).
958 1: ldr r3, [r2] @ load current val
959 subs r3, r3, r0 @ compare with oldval
960 2: streq r1, [r2] @ store newval if eq
961 rsbs r0, r3, #0 @ set return val and C flag
965 kuser_cmpxchg32_fixup:
966 @ Called from kuser_cmpxchg_check macro.
967 @ r4 = address of interrupted insn (must be preserved).
968 @ sp = saved regs. r7 and r8 are clobbered.
969 @ 1b = first critical insn, 2b = last critical insn.
970 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b.
972 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg)))
974 rsbcss r8, r8, #(2b - 1b)
975 strcs r7, [sp, #S_PC]
980 #warning "NPTL on non MMU needs fixing"
995 /* beware -- each __kuser slot must be 8 instructions max */
996 ALT_SMP(b __kuser_memory_barrier)
1001 kuser_pad __kuser_cmpxchg, 32
1003 __kuser_get_tls: @ 0xffff0fe0
1004 ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init
1006 mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code
1007 kuser_pad __kuser_get_tls, 16
1009 .word 0 @ 0xffff0ff0 software TLS value, then
1010 .endr @ pad up to __kuser_helper_version
1012 __kuser_helper_version: @ 0xffff0ffc
1013 .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
1015 .globl __kuser_helper_end
1025 * This code is copied to 0xffff1000 so we can use branches in the
1026 * vectors, rather than ldr's. Note that this code must not exceed
1029 * Common stub entry macro:
1030 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1032 * SP points to a minimal amount of processor-private memory, the address
1033 * of which is copied into r0 for the mode specific abort handler.
1035 .macro vector_stub, name, mode, correction=0
1040 sub lr, lr, #\correction
1044 @ Save r0, lr_<exception> (parent PC) and spsr_<exception>
1047 stmia sp, {r0, lr} @ save r0, lr
1049 str lr, [sp, #8] @ save spsr
1052 @ Prepare for SVC32 mode. IRQs remain disabled.
1055 eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE)
1059 @ the branch table must immediately follow this code
1063 THUMB( ldr lr, [r0, lr, lsl #2] )
1065 ARM( ldr lr, [pc, lr, lsl #2] )
1066 movs pc, lr @ branch to handler in SVC mode
1067 ENDPROC(vector_\name)
1070 @ handler addresses follow this label
1074 .section .stubs, "ax", %progbits
1076 @ This must be the first word
1080 ARM( swi SYS_ERROR0 )
1086 * Interrupt dispatcher
1088 vector_stub irq, IRQ_MODE, 4
1090 .long __irq_usr @ 0 (USR_26 / USR_32)
1091 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32)
1092 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32)
1093 .long __irq_svc @ 3 (SVC_26 / SVC_32)
1094 .long __irq_invalid @ 4
1095 .long __irq_invalid @ 5
1096 .long __irq_invalid @ 6
1097 .long __irq_invalid @ 7
1098 .long __irq_invalid @ 8
1099 .long __irq_invalid @ 9
1100 .long __irq_invalid @ a
1101 .long __irq_invalid @ b
1102 .long __irq_invalid @ c
1103 .long __irq_invalid @ d
1104 .long __irq_invalid @ e
1105 .long __irq_invalid @ f
1108 * Data abort dispatcher
1109 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1111 vector_stub dabt, ABT_MODE, 8
1113 .long __dabt_usr @ 0 (USR_26 / USR_32)
1114 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32)
1115 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32)
1116 .long __dabt_svc @ 3 (SVC_26 / SVC_32)
1117 .long __dabt_invalid @ 4
1118 .long __dabt_invalid @ 5
1119 .long __dabt_invalid @ 6
1120 .long __dabt_invalid @ 7
1121 .long __dabt_invalid @ 8
1122 .long __dabt_invalid @ 9
1123 .long __dabt_invalid @ a
1124 .long __dabt_invalid @ b
1125 .long __dabt_invalid @ c
1126 .long __dabt_invalid @ d
1127 .long __dabt_invalid @ e
1128 .long __dabt_invalid @ f
1131 * Prefetch abort dispatcher
1132 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1134 vector_stub pabt, ABT_MODE, 4
1136 .long __pabt_usr @ 0 (USR_26 / USR_32)
1137 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32)
1138 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32)
1139 .long __pabt_svc @ 3 (SVC_26 / SVC_32)
1140 .long __pabt_invalid @ 4
1141 .long __pabt_invalid @ 5
1142 .long __pabt_invalid @ 6
1143 .long __pabt_invalid @ 7
1144 .long __pabt_invalid @ 8
1145 .long __pabt_invalid @ 9
1146 .long __pabt_invalid @ a
1147 .long __pabt_invalid @ b
1148 .long __pabt_invalid @ c
1149 .long __pabt_invalid @ d
1150 .long __pabt_invalid @ e
1151 .long __pabt_invalid @ f
1154 * Undef instr entry dispatcher
1155 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1157 vector_stub und, UND_MODE
1159 .long __und_usr @ 0 (USR_26 / USR_32)
1160 .long __und_invalid @ 1 (FIQ_26 / FIQ_32)
1161 .long __und_invalid @ 2 (IRQ_26 / IRQ_32)
1162 .long __und_svc @ 3 (SVC_26 / SVC_32)
1163 .long __und_invalid @ 4
1164 .long __und_invalid @ 5
1165 .long __und_invalid @ 6
1166 .long __und_invalid @ 7
1167 .long __und_invalid @ 8
1168 .long __und_invalid @ 9
1169 .long __und_invalid @ a
1170 .long __und_invalid @ b
1171 .long __und_invalid @ c
1172 .long __und_invalid @ d
1173 .long __und_invalid @ e
1174 .long __und_invalid @ f
1178 /*=============================================================================
1179 * Address exception handler
1180 *-----------------------------------------------------------------------------
1181 * These aren't too critical.
1182 * (they're not supposed to happen, and won't happen in 32-bit data mode).
1188 /*=============================================================================
1190 *-----------------------------------------------------------------------------
1191 * Handle a FIQ using the SVC stack allowing FIQ act like NMI on x86
1194 vector_stub fiq, FIQ_MODE, 4
1196 .long __fiq_usr @ 0 (USR_26 / USR_32)
1197 .long __fiq_svc @ 1 (FIQ_26 / FIQ_32)
1198 .long __fiq_svc @ 2 (IRQ_26 / IRQ_32)
1199 .long __fiq_svc @ 3 (SVC_26 / SVC_32)
1213 .globl vector_fiq_offset
1214 .equ vector_fiq_offset, vector_fiq
1216 .section .vectors, "ax", %progbits
1220 W(ldr) pc, __vectors_start + 0x1000
1223 W(b) vector_addrexcptn
1233 #ifdef CONFIG_MULTI_IRQ_HANDLER
1234 .globl handle_arch_irq