2 * linux/arch/arm/kernel/head.S
4 * Copyright (C) 1994-2002 Russell King
5 * Copyright (c) 2003 ARM Limited
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * Kernel startup code for all 32-bit CPUs
14 #include <linux/linkage.h>
15 #include <linux/init.h>
17 #include <asm/assembler.h>
18 #include <asm/domain.h>
19 #include <asm/ptrace.h>
20 #include <asm/asm-offsets.h>
21 #include <asm/memory.h>
22 #include <asm/thread_info.h>
23 #include <asm/system.h>
25 #ifdef CONFIG_DEBUG_LL
26 #include <mach/debug-macro.S>
30 * swapper_pg_dir is the virtual address of the initial page table.
31 * We place the page tables 16K below KERNEL_RAM_VADDR. Therefore, we must
32 * make sure that KERNEL_RAM_VADDR is correctly set. Currently, we expect
33 * the least significant 16 bits to be 0x8000, but we could probably
34 * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000.
36 #define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET)
37 #if (KERNEL_RAM_VADDR & 0xffff) != 0x8000
38 #error KERNEL_RAM_VADDR must start at 0xXXXX8000
42 .equ swapper_pg_dir, KERNEL_RAM_VADDR - 0x4000
44 .macro pgtbl, rd, phys
46 add \rd, \phys, #((TEXT_OFFSET - 0x4000) & 0xffff0000)
47 add \rd, \rd, #((TEXT_OFFSET - 0x4000) & 0x0000ffff)
49 add \rd, \phys, #TEXT_OFFSET - 0x4000
53 #ifdef CONFIG_XIP_KERNEL
54 #define KERNEL_START XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR)
55 #define KERNEL_END _edata_loc
57 #define KERNEL_START KERNEL_RAM_VADDR
58 #define KERNEL_END _end
62 * Kernel startup entry point.
63 * ---------------------------
65 * This is normally called from the decompressor code. The requirements
66 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
67 * r1 = machine nr, r2 = atags or dtb pointer.
69 * This code is mostly position independent, so if you link the kernel at
70 * 0xc0008000, you call this at __pa(0xc0008000).
72 * See linux/arch/arm/tools/mach-types for the complete list of machine
75 * We're trying to keep crap to a minimum; DO NOT add any machine specific
76 * crap here - that's what the boot loader (or in extreme, well justified
77 * circumstances, zImage) is for.
81 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
83 mrc p15, 0, r9, c0, c0 @ get processor id
84 bl __lookup_processor_type @ r5=procinfo r9=cpuid
85 movs r10, r5 @ invalid processor (r5=0)?
86 THUMB( it eq ) @ force fixup-able long branch encoding
87 beq __error_p @ yes, error 'p'
89 #ifndef CONFIG_XIP_KERNEL
92 sub r4, r3, r4 @ (PHYS_OFFSET - PAGE_OFFSET)
93 add r8, r8, r4 @ PHYS_OFFSET
95 ldr r8, =PLAT_PHYS_OFFSET
99 * r1 = machine no, r2 = atags or dtb,
100 * r8 = phys_offset, r9 = cpuid, r10 = procinfo
103 #ifdef CONFIG_SMP_ON_UP
106 #ifdef CONFIG_ARM_PATCH_PHYS_VIRT
109 bl __create_page_tables
112 * The following calls CPU specific code in a position independent
113 * manner. See arch/arm/mm/proc-*.S for details. r10 = base of
114 * xxx_proc_info structure selected by __lookup_processor_type
115 * above. On return, the CPU will be ready for the MMU to be
116 * turned on, and r0 will hold the CPU control register value.
118 ldr r13, =__mmap_switched @ address to jump to after
119 @ mmu has been enabled
120 adr lr, BSYM(1f) @ return (PIC) address
121 mov r8, r4 @ set TTBR1 to swapper_pg_dir
122 ARM( add pc, r10, #PROCINFO_INITFUNC )
123 THUMB( add r12, r10, #PROCINFO_INITFUNC )
128 #ifndef CONFIG_XIP_KERNEL
134 * Setup the initial page tables. We only setup the barest
135 * amount which are required to get the kernel running, which
136 * generally means mapping in the kernel code.
138 * r8 = phys_offset, r9 = cpuid, r10 = procinfo
141 * r0, r3, r5-r7 corrupted
142 * r4 = physical page table address
144 __create_page_tables:
145 pgtbl r4, r8 @ page table address
148 * Clear the 16K level 1 swapper page table
160 ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags
163 * Create identity mapping to cater for __enable_mmu.
164 * This identity mapping will be removed by paging_init().
166 adr r0, __enable_mmu_loc
167 ldmia r0, {r3, r5, r6}
168 sub r0, r0, r3 @ virt->phys offset
169 add r5, r5, r0 @ phys __enable_mmu
170 add r6, r6, r0 @ phys __enable_mmu_end
174 1: orr r3, r7, r5, lsl #20 @ flags + kernel base
175 str r3, [r4, r5, lsl #2] @ identity mapping
177 addne r5, r5, #1 @ next section
181 * Now setup the pagetables for our kernel direct
186 orr r3, r7, r3, lsl #20
187 add r0, r4, #(KERNEL_START & 0xff000000) >> 18
188 str r3, [r0, #(KERNEL_START & 0x00f00000) >> 18]!
189 ldr r6, =(KERNEL_END - 1)
191 add r6, r4, r6, lsr #18
197 #ifdef CONFIG_XIP_KERNEL
199 * Map some ram to cover our .data and .bss areas.
201 add r3, r8, #TEXT_OFFSET
203 add r0, r4, #(KERNEL_RAM_VADDR & 0xff000000) >> 18
204 str r3, [r0, #(KERNEL_RAM_VADDR & 0x00f00000) >> 18]!
207 add r6, r4, r6, lsr #18
215 * Then map boot params address in r2 or
216 * the first 1MB of ram if boot params address is not specified.
222 add r3, r3, #PAGE_OFFSET
223 add r3, r4, r3, lsr #18
227 #ifdef CONFIG_DEBUG_LL
228 #ifndef CONFIG_DEBUG_ICEDCC
230 * Map in IO space for serial debugging.
231 * This allows debug messages to be output
232 * via a serial console before paging_init.
240 rsb r3, r3, #0x4000 @ PTRS_PER_PGD*sizeof(long)
241 cmp r3, #0x0800 @ limit to 512MB
245 ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
246 orr r3, r7, r3, lsl #20
252 #else /* CONFIG_DEBUG_ICEDCC */
253 /* we don't need any serial debugging mappings for ICEDCC */
254 ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
255 #endif /* !CONFIG_DEBUG_ICEDCC */
257 #if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS)
259 * If we're using the NetWinder or CATS, we also need to map
260 * in the 16550-type serial port for the debug messages
262 add r0, r4, #0xff000000 >> 18
263 orr r3, r7, #0x7c000000
266 #ifdef CONFIG_ARCH_RPC
268 * Map in screen at 0x02000000 & SCREEN2_BASE
269 * Similar reasons here - for debug. This is
270 * only for Acorn RiscPC architectures.
272 add r0, r4, #0x02000000 >> 18
273 orr r3, r7, #0x02000000
275 add r0, r4, #0xd8000000 >> 18
280 ENDPROC(__create_page_tables)
286 .long __enable_mmu_end
288 #if defined(CONFIG_SMP)
290 ENTRY(secondary_startup)
292 * Common entry point for secondary CPUs.
294 * Ensure that we're in SVC mode, and IRQs are disabled. Lookup
295 * the processor type - there is no need to check the machine type
296 * as it has already been validated by the primary processor.
298 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9
299 mrc p15, 0, r9, c0, c0 @ get processor id
300 bl __lookup_processor_type
301 movs r10, r5 @ invalid processor?
302 moveq r0, #'p' @ yes, error 'p'
303 THUMB( it eq ) @ force fixup-able long branch encoding
307 * Use the page tables supplied from __cpu_up.
309 adr r4, __secondary_data
310 ldmia r4, {r5, r7, r12} @ address to jump to after
311 sub lr, r4, r5 @ mmu has been enabled
312 ldr r4, [r7, lr] @ get secondary_data.pgdir
314 ldr r8, [r7, lr] @ get secondary_data.swapper_pg_dir
315 adr lr, BSYM(__enable_mmu) @ return address
316 mov r13, r12 @ __secondary_switched address
317 ARM( add pc, r10, #PROCINFO_INITFUNC ) @ initialise processor
318 @ (return control reg)
319 THUMB( add r12, r10, #PROCINFO_INITFUNC )
321 ENDPROC(secondary_startup)
324 * r6 = &secondary_data
326 ENTRY(__secondary_switched)
327 ldr sp, [r7, #4] @ get secondary_data.stack
329 b secondary_start_kernel
330 ENDPROC(__secondary_switched)
334 .type __secondary_data, %object
338 .long __secondary_switched
339 #endif /* defined(CONFIG_SMP) */
344 * Setup common bits before finally enabling the MMU. Essentially
345 * this is just loading the page table pointer and domain access
348 * r0 = cp#15 control register
350 * r2 = atags or dtb pointer
351 * r4 = page table pointer
353 * r13 = *virtual* address to jump to upon completion
356 #if defined(CONFIG_ALIGNMENT_TRAP) && __LINUX_ARM_ARCH__ < 6
361 #ifdef CONFIG_CPU_DCACHE_DISABLE
364 #ifdef CONFIG_CPU_BPREDICT_DISABLE
367 #ifdef CONFIG_CPU_ICACHE_DISABLE
370 mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
371 domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
372 domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
373 domain_val(DOMAIN_IO, DOMAIN_CLIENT))
374 mcr p15, 0, r5, c3, c0, 0 @ load domain access register
375 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
377 ENDPROC(__enable_mmu)
380 * Enable the MMU. This completely changes the structure of the visible
381 * memory space. You will not be able to trace execution through this.
382 * If you have an enquiry about this, *please* check the linux-arm-kernel
383 * mailing list archives BEFORE sending another post to the list.
385 * r0 = cp#15 control register
387 * r2 = atags or dtb pointer
389 * r13 = *virtual* address to jump to upon completion
391 * other registers depend on the function called upon completion
396 mcr p15, 0, r0, c1, c0, 0 @ write control reg
397 mrc p15, 0, r3, c0, c0, 0 @ read id reg
402 ENDPROC(__turn_mmu_on)
405 #ifdef CONFIG_SMP_ON_UP
408 and r3, r9, #0x000f0000 @ architecture version
409 teq r3, #0x000f0000 @ CPU ID supported?
410 bne __fixup_smp_on_up @ no, assume UP
412 bic r3, r9, #0x00ff0000
413 bic r3, r3, #0x0000000f @ mask 0xff00fff0
415 orr r4, r4, #0x0000b000
416 orr r4, r4, #0x00000020 @ val 0x4100b020
417 teq r3, r4 @ ARM 11MPCore?
418 moveq pc, lr @ yes, assume SMP
420 mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
421 and r0, r0, #0xc0000000 @ multiprocessing extensions and
422 teq r0, #0x80000000 @ not part of a uniprocessor system?
423 moveq pc, lr @ yes, assume SMP
431 b __do_fixup_smp_on_up
448 __do_fixup_smp_on_up:
452 ARM( str r6, [r0, r3] )
453 THUMB( add r0, r0, r3 )
455 THUMB( mov r6, r6, ror #16 ) @ Convert word order for big-endian.
457 THUMB( strh r6, [r0], #2 ) @ For Thumb-2, store as two halfwords
458 THUMB( mov r6, r6, lsr #16 ) @ to be robust against misaligned r3.
459 THUMB( strh r6, [r0] )
460 b __do_fixup_smp_on_up
461 ENDPROC(__do_fixup_smp_on_up)
464 stmfd sp!, {r4 - r6, lr}
468 bl __do_fixup_smp_on_up
469 ldmfd sp!, {r4 - r6, pc}
472 #ifdef CONFIG_ARM_PATCH_PHYS_VIRT
474 /* __fixup_pv_table - patch the stub instructions with the delta between
475 * PHYS_OFFSET and PAGE_OFFSET, which is assumed to be 16MiB aligned and
476 * can be expressed by an immediate shifter operand. The stub instruction
477 * has a form of '(add|sub) rd, rn, #imm'.
482 ldmia r0, {r3-r5, r7}
483 sub r3, r0, r3 @ PHYS_OFFSET - PAGE_OFFSET
484 add r4, r4, r3 @ adjust table start address
485 add r5, r5, r3 @ adjust table end address
486 add r7, r7, r3 @ adjust __pv_phys_offset address
487 str r8, [r7] @ save computed PHYS_OFFSET to __pv_phys_offset
488 #ifndef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT
489 mov r6, r3, lsr #24 @ constant for add/sub instructions
490 teq r3, r6, lsl #24 @ must be 16MiB aligned
492 mov r6, r3, lsr #16 @ constant for add/sub instructions
493 teq r3, r6, lsl #16 @ must be 64kiB aligned
495 THUMB( it ne @ cross section branch )
497 str r6, [r7, #4] @ save to __pv_offset
499 ENDPROC(__fixup_pv_table)
503 .long __pv_table_begin
505 2: .long __pv_phys_offset
509 #ifdef CONFIG_THUMB2_KERNEL
510 #ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT
520 orr r0, r0, r7, lsl #12
530 orr r6, r6, r7, lsl #12
533 2: @ at this point the C flag is always clear
535 #ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT
537 tst ip, 0x0400 @ the i bit tells us LS or MS byte
539 cmp r0, #0 @ set C flag, and ...
540 biceq ip, 0x0400 @ immediate zero value has a special encoding
541 streqh ip, [r7] @ that requires the i bit cleared
545 orrcc ip, r6 @ mask in offset bits 31-24
546 orrcs ip, r0 @ mask in offset bits 23-16
549 ldrcc r7, [r4], #4 @ use branch for delay slot
553 #ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT
554 and r0, r6, #255 @ offset bits 23-16
555 mov r6, r6, lsr #8 @ offset bits 31-24
557 mov r0, #0 @ just in case...
561 bic ip, ip, #0x000000ff
562 tst ip, #0x400 @ rotate shift tells us LS or MS byte
563 orrne ip, ip, r6 @ mask in offset bits 31-24
564 orreq ip, ip, r0 @ mask in offset bits 23-16
567 ldrcc r7, [r4], #4 @ use branch for delay slot
571 ENDPROC(__fixup_a_pv_table)
573 ENTRY(fixup_pv_table)
574 stmfd sp!, {r4 - r7, lr}
575 ldr r2, 2f @ get address of __pv_phys_offset
576 mov r3, #0 @ no offset
577 mov r4, r0 @ r0 = table start
578 add r5, r0, r1 @ r1 = table size
579 ldr r6, [r2, #4] @ get __pv_offset
580 bl __fixup_a_pv_table
581 ldmfd sp!, {r4 - r7, pc}
582 ENDPROC(fixup_pv_table)
585 2: .long __pv_phys_offset
588 .globl __pv_phys_offset
589 .type __pv_phys_offset, %object
592 .size __pv_phys_offset, . - __pv_phys_offset
597 #include "head-common.S"