2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
15 * Copyright (C) 2009, 2010 ARM Limited
17 * Author: Will Deacon <will.deacon@arm.com>
21 * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
22 * using the CPU's debug registers.
24 #define pr_fmt(fmt) "hw-breakpoint: " fmt
26 #include <linux/errno.h>
27 #include <linux/hardirq.h>
28 #include <linux/perf_event.h>
29 #include <linux/hw_breakpoint.h>
30 #include <linux/smp.h>
32 #include <asm/cacheflush.h>
33 #include <asm/cputype.h>
34 #include <asm/current.h>
35 #include <asm/hw_breakpoint.h>
36 #include <asm/kdebug.h>
37 #include <asm/system.h>
38 #include <asm/traps.h>
40 /* Breakpoint currently in use for each BRP. */
41 static DEFINE_PER_CPU(struct perf_event *, bp_on_reg[ARM_MAX_BRP]);
43 /* Watchpoint currently in use for each WRP. */
44 static DEFINE_PER_CPU(struct perf_event *, wp_on_reg[ARM_MAX_WRP]);
46 /* Number of BRP/WRP registers on this CPU. */
47 static int core_num_brps;
48 static int core_num_reserved_brps;
49 static int core_num_wrps;
51 /* Debug architecture version. */
54 /* Maximum supported watchpoint length. */
55 static u8 max_watchpoint_len;
57 #define READ_WB_REG_CASE(OP2, M, VAL) \
58 case ((OP2 << 4) + M): \
59 ARM_DBG_READ(c ## M, OP2, VAL); \
62 #define WRITE_WB_REG_CASE(OP2, M, VAL) \
63 case ((OP2 << 4) + M): \
64 ARM_DBG_WRITE(c ## M, OP2, VAL);\
67 #define GEN_READ_WB_REG_CASES(OP2, VAL) \
68 READ_WB_REG_CASE(OP2, 0, VAL); \
69 READ_WB_REG_CASE(OP2, 1, VAL); \
70 READ_WB_REG_CASE(OP2, 2, VAL); \
71 READ_WB_REG_CASE(OP2, 3, VAL); \
72 READ_WB_REG_CASE(OP2, 4, VAL); \
73 READ_WB_REG_CASE(OP2, 5, VAL); \
74 READ_WB_REG_CASE(OP2, 6, VAL); \
75 READ_WB_REG_CASE(OP2, 7, VAL); \
76 READ_WB_REG_CASE(OP2, 8, VAL); \
77 READ_WB_REG_CASE(OP2, 9, VAL); \
78 READ_WB_REG_CASE(OP2, 10, VAL); \
79 READ_WB_REG_CASE(OP2, 11, VAL); \
80 READ_WB_REG_CASE(OP2, 12, VAL); \
81 READ_WB_REG_CASE(OP2, 13, VAL); \
82 READ_WB_REG_CASE(OP2, 14, VAL); \
83 READ_WB_REG_CASE(OP2, 15, VAL)
85 #define GEN_WRITE_WB_REG_CASES(OP2, VAL) \
86 WRITE_WB_REG_CASE(OP2, 0, VAL); \
87 WRITE_WB_REG_CASE(OP2, 1, VAL); \
88 WRITE_WB_REG_CASE(OP2, 2, VAL); \
89 WRITE_WB_REG_CASE(OP2, 3, VAL); \
90 WRITE_WB_REG_CASE(OP2, 4, VAL); \
91 WRITE_WB_REG_CASE(OP2, 5, VAL); \
92 WRITE_WB_REG_CASE(OP2, 6, VAL); \
93 WRITE_WB_REG_CASE(OP2, 7, VAL); \
94 WRITE_WB_REG_CASE(OP2, 8, VAL); \
95 WRITE_WB_REG_CASE(OP2, 9, VAL); \
96 WRITE_WB_REG_CASE(OP2, 10, VAL); \
97 WRITE_WB_REG_CASE(OP2, 11, VAL); \
98 WRITE_WB_REG_CASE(OP2, 12, VAL); \
99 WRITE_WB_REG_CASE(OP2, 13, VAL); \
100 WRITE_WB_REG_CASE(OP2, 14, VAL); \
101 WRITE_WB_REG_CASE(OP2, 15, VAL)
103 static u32 read_wb_reg(int n)
108 GEN_READ_WB_REG_CASES(ARM_OP2_BVR, val);
109 GEN_READ_WB_REG_CASES(ARM_OP2_BCR, val);
110 GEN_READ_WB_REG_CASES(ARM_OP2_WVR, val);
111 GEN_READ_WB_REG_CASES(ARM_OP2_WCR, val);
113 pr_warning("attempt to read from unknown breakpoint "
120 static void write_wb_reg(int n, u32 val)
123 GEN_WRITE_WB_REG_CASES(ARM_OP2_BVR, val);
124 GEN_WRITE_WB_REG_CASES(ARM_OP2_BCR, val);
125 GEN_WRITE_WB_REG_CASES(ARM_OP2_WVR, val);
126 GEN_WRITE_WB_REG_CASES(ARM_OP2_WCR, val);
128 pr_warning("attempt to write to unknown breakpoint "
134 /* Determine debug architecture. */
135 static u8 get_debug_arch(void)
139 /* Do we implement the extended CPUID interface? */
140 if (WARN_ONCE((((read_cpuid_id() >> 16) & 0xf) != 0xf),
141 "CPUID feature registers not supported. "
142 "Assuming v6 debug is present.\n"))
143 return ARM_DEBUG_ARCH_V6;
145 ARM_DBG_READ(c0, 0, didr);
146 return (didr >> 16) & 0xf;
149 u8 arch_get_debug_arch(void)
154 static int debug_arch_supported(void)
156 u8 arch = get_debug_arch();
157 return arch >= ARM_DEBUG_ARCH_V6 && arch <= ARM_DEBUG_ARCH_V7_ECP14;
160 /* Determine number of BRP register available. */
161 static int get_num_brp_resources(void)
164 ARM_DBG_READ(c0, 0, didr);
165 return ((didr >> 24) & 0xf) + 1;
168 /* Does this core support mismatch breakpoints? */
169 static int core_has_mismatch_brps(void)
171 return (get_debug_arch() >= ARM_DEBUG_ARCH_V7_ECP14 &&
172 get_num_brp_resources() > 1);
175 /* Determine number of usable WRPs available. */
176 static int get_num_wrps(void)
179 * FIXME: When a watchpoint fires, the only way to work out which
180 * watchpoint it was is by disassembling the faulting instruction
181 * and working out the address of the memory access.
183 * Furthermore, we can only do this if the watchpoint was precise
184 * since imprecise watchpoints prevent us from calculating register
187 * Providing we have more than 1 breakpoint register, we only report
188 * a single watchpoint register for the time being. This way, we always
189 * know which watchpoint fired. In the future we can either add a
190 * disassembler and address generation emulator, or we can insert a
191 * check to see if the DFAR is set on watchpoint exception entry
192 * [the ARM ARM states that the DFAR is UNKNOWN, but experience shows
193 * that it is set on some implementations].
199 ARM_DBG_READ(c0, 0, didr);
200 wrps = ((didr >> 28) & 0xf) + 1;
204 if (core_has_mismatch_brps() && wrps >= get_num_brp_resources())
205 wrps = get_num_brp_resources() - 1;
210 /* We reserve one breakpoint for each watchpoint. */
211 static int get_num_reserved_brps(void)
213 if (core_has_mismatch_brps())
214 return get_num_wrps();
218 /* Determine number of usable BRPs available. */
219 static int get_num_brps(void)
221 int brps = get_num_brp_resources();
222 if (core_has_mismatch_brps())
223 brps -= get_num_reserved_brps();
228 * In order to access the breakpoint/watchpoint control registers,
229 * we must be running in debug monitor mode. Unfortunately, we can
230 * be put into halting debug mode at any time by an external debugger
231 * but there is nothing we can do to prevent that.
233 static int enable_monitor_mode(void)
238 ARM_DBG_READ(c1, 0, dscr);
240 /* Ensure that halting mode is disabled. */
241 if (WARN_ONCE(dscr & ARM_DSCR_HDBGEN, "halting debug mode enabled."
242 "Unable to access hardware resources.")) {
247 /* If monitor mode is already enabled, just return. */
248 if (dscr & ARM_DSCR_MDBGEN)
251 /* Write to the corresponding DSCR. */
252 switch (get_debug_arch()) {
253 case ARM_DEBUG_ARCH_V6:
254 case ARM_DEBUG_ARCH_V6_1:
255 ARM_DBG_WRITE(c1, 0, (dscr | ARM_DSCR_MDBGEN));
257 case ARM_DEBUG_ARCH_V7_ECP14:
258 ARM_DBG_WRITE(c2, 2, (dscr | ARM_DSCR_MDBGEN));
265 /* Check that the write made it through. */
266 ARM_DBG_READ(c1, 0, dscr);
267 if (!(dscr & ARM_DSCR_MDBGEN))
274 int hw_breakpoint_slots(int type)
276 if (!debug_arch_supported())
280 * We can be called early, so don't rely on
281 * our static variables being initialised.
285 return get_num_brps();
287 return get_num_wrps();
289 pr_warning("unknown slot type: %d\n", type);
295 * Check if 8-bit byte-address select is available.
296 * This clobbers WRP 0.
298 static u8 get_max_wp_len(void)
301 struct arch_hw_breakpoint_ctrl ctrl;
304 if (debug_arch < ARM_DEBUG_ARCH_V7_ECP14)
307 memset(&ctrl, 0, sizeof(ctrl));
308 ctrl.len = ARM_BREAKPOINT_LEN_8;
309 ctrl_reg = encode_ctrl_reg(ctrl);
311 write_wb_reg(ARM_BASE_WVR, 0);
312 write_wb_reg(ARM_BASE_WCR, ctrl_reg);
313 if ((read_wb_reg(ARM_BASE_WCR) & ctrl_reg) == ctrl_reg)
320 u8 arch_get_max_wp_len(void)
322 return max_watchpoint_len;
326 * Install a perf counter breakpoint.
328 int arch_install_hw_breakpoint(struct perf_event *bp)
330 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
331 struct perf_event **slot, **slots;
332 int i, max_slots, ctrl_base, val_base, ret = 0;
335 /* Ensure that we are in monitor mode and halting mode is disabled. */
336 ret = enable_monitor_mode();
340 addr = info->address;
341 ctrl = encode_ctrl_reg(info->ctrl) | 0x1;
343 if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
345 ctrl_base = ARM_BASE_BCR;
346 val_base = ARM_BASE_BVR;
347 slots = (struct perf_event **)__get_cpu_var(bp_on_reg);
348 max_slots = core_num_brps;
349 if (info->step_ctrl.enabled) {
350 /* Override the breakpoint data with the step data. */
351 addr = info->trigger & ~0x3;
352 ctrl = encode_ctrl_reg(info->step_ctrl);
356 if (info->step_ctrl.enabled) {
357 /* Install into the reserved breakpoint region. */
358 ctrl_base = ARM_BASE_BCR + core_num_brps;
359 val_base = ARM_BASE_BVR + core_num_brps;
360 /* Override the watchpoint data with the step data. */
361 addr = info->trigger & ~0x3;
362 ctrl = encode_ctrl_reg(info->step_ctrl);
364 ctrl_base = ARM_BASE_WCR;
365 val_base = ARM_BASE_WVR;
367 slots = (struct perf_event **)__get_cpu_var(wp_on_reg);
368 max_slots = core_num_wrps;
371 for (i = 0; i < max_slots; ++i) {
380 if (WARN_ONCE(i == max_slots, "Can't find any breakpoint slot")) {
385 /* Setup the address register. */
386 write_wb_reg(val_base + i, addr);
388 /* Setup the control register. */
389 write_wb_reg(ctrl_base + i, ctrl);
395 void arch_uninstall_hw_breakpoint(struct perf_event *bp)
397 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
398 struct perf_event **slot, **slots;
399 int i, max_slots, base;
401 if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
404 slots = (struct perf_event **)__get_cpu_var(bp_on_reg);
405 max_slots = core_num_brps;
408 if (info->step_ctrl.enabled)
409 base = ARM_BASE_BCR + core_num_brps;
412 slots = (struct perf_event **)__get_cpu_var(wp_on_reg);
413 max_slots = core_num_wrps;
416 /* Remove the breakpoint. */
417 for (i = 0; i < max_slots; ++i) {
426 if (WARN_ONCE(i == max_slots, "Can't find any breakpoint slot"))
429 /* Reset the control register. */
430 write_wb_reg(base + i, 0);
433 static int get_hbp_len(u8 hbp_len)
435 unsigned int len_in_bytes = 0;
438 case ARM_BREAKPOINT_LEN_1:
441 case ARM_BREAKPOINT_LEN_2:
444 case ARM_BREAKPOINT_LEN_4:
447 case ARM_BREAKPOINT_LEN_8:
456 * Check whether bp virtual address is in kernel space.
458 int arch_check_bp_in_kernelspace(struct perf_event *bp)
462 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
465 len = get_hbp_len(info->ctrl.len);
467 return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE);
471 * Extract generic type and length encodings from an arch_hw_breakpoint_ctrl.
472 * Hopefully this will disappear when ptrace can bypass the conversion
473 * to generic breakpoint descriptions.
475 int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
476 int *gen_len, int *gen_type)
480 case ARM_BREAKPOINT_EXECUTE:
481 *gen_type = HW_BREAKPOINT_X;
483 case ARM_BREAKPOINT_LOAD:
484 *gen_type = HW_BREAKPOINT_R;
486 case ARM_BREAKPOINT_STORE:
487 *gen_type = HW_BREAKPOINT_W;
489 case ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE:
490 *gen_type = HW_BREAKPOINT_RW;
498 case ARM_BREAKPOINT_LEN_1:
499 *gen_len = HW_BREAKPOINT_LEN_1;
501 case ARM_BREAKPOINT_LEN_2:
502 *gen_len = HW_BREAKPOINT_LEN_2;
504 case ARM_BREAKPOINT_LEN_4:
505 *gen_len = HW_BREAKPOINT_LEN_4;
507 case ARM_BREAKPOINT_LEN_8:
508 *gen_len = HW_BREAKPOINT_LEN_8;
518 * Construct an arch_hw_breakpoint from a perf_event.
520 static int arch_build_bp_info(struct perf_event *bp)
522 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
525 switch (bp->attr.bp_type) {
526 case HW_BREAKPOINT_X:
527 info->ctrl.type = ARM_BREAKPOINT_EXECUTE;
529 case HW_BREAKPOINT_R:
530 info->ctrl.type = ARM_BREAKPOINT_LOAD;
532 case HW_BREAKPOINT_W:
533 info->ctrl.type = ARM_BREAKPOINT_STORE;
535 case HW_BREAKPOINT_RW:
536 info->ctrl.type = ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE;
543 switch (bp->attr.bp_len) {
544 case HW_BREAKPOINT_LEN_1:
545 info->ctrl.len = ARM_BREAKPOINT_LEN_1;
547 case HW_BREAKPOINT_LEN_2:
548 info->ctrl.len = ARM_BREAKPOINT_LEN_2;
550 case HW_BREAKPOINT_LEN_4:
551 info->ctrl.len = ARM_BREAKPOINT_LEN_4;
553 case HW_BREAKPOINT_LEN_8:
554 info->ctrl.len = ARM_BREAKPOINT_LEN_8;
555 if ((info->ctrl.type != ARM_BREAKPOINT_EXECUTE)
556 && max_watchpoint_len >= 8)
563 * Breakpoints must be of length 2 (thumb) or 4 (ARM) bytes.
564 * Watchpoints can be of length 1, 2, 4 or 8 bytes if supported
565 * by the hardware and must be aligned to the appropriate number of
568 if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE &&
569 info->ctrl.len != ARM_BREAKPOINT_LEN_2 &&
570 info->ctrl.len != ARM_BREAKPOINT_LEN_4)
574 info->address = bp->attr.bp_addr;
577 info->ctrl.privilege = ARM_BREAKPOINT_USER;
578 if (arch_check_bp_in_kernelspace(bp))
579 info->ctrl.privilege |= ARM_BREAKPOINT_PRIV;
582 info->ctrl.enabled = !bp->attr.disabled;
585 info->ctrl.mismatch = 0;
591 * Validate the arch-specific HW Breakpoint register settings.
593 int arch_validate_hwbkpt_settings(struct perf_event *bp)
595 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
597 u32 offset, alignment_mask = 0x3;
599 /* Build the arch_hw_breakpoint. */
600 ret = arch_build_bp_info(bp);
604 /* Check address alignment. */
605 if (info->ctrl.len == ARM_BREAKPOINT_LEN_8)
606 alignment_mask = 0x7;
607 offset = info->address & alignment_mask;
613 /* Allow single byte watchpoint. */
614 if (info->ctrl.len == ARM_BREAKPOINT_LEN_1)
617 /* Allow halfword watchpoints and breakpoints. */
618 if (info->ctrl.len == ARM_BREAKPOINT_LEN_2)
625 info->address &= ~alignment_mask;
626 info->ctrl.len <<= offset;
629 * Currently we rely on an overflow handler to take
630 * care of single-stepping the breakpoint when it fires.
631 * In the case of userspace breakpoints on a core with V7 debug,
632 * we can use the mismatch feature as a poor-man's hardware
633 * single-step, but this only works for per-task breakpoints.
635 if (WARN_ONCE(!bp->overflow_handler &&
636 (arch_check_bp_in_kernelspace(bp) || !core_has_mismatch_brps()
637 || !bp->hw.bp_target),
638 "overflow handler required but none found")) {
646 * Enable/disable single-stepping over the breakpoint bp at address addr.
648 static void enable_single_step(struct perf_event *bp, u32 addr)
650 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
652 arch_uninstall_hw_breakpoint(bp);
653 info->step_ctrl.mismatch = 1;
654 info->step_ctrl.len = ARM_BREAKPOINT_LEN_4;
655 info->step_ctrl.type = ARM_BREAKPOINT_EXECUTE;
656 info->step_ctrl.privilege = info->ctrl.privilege;
657 info->step_ctrl.enabled = 1;
658 info->trigger = addr;
659 arch_install_hw_breakpoint(bp);
662 static void disable_single_step(struct perf_event *bp)
664 arch_uninstall_hw_breakpoint(bp);
665 counter_arch_bp(bp)->step_ctrl.enabled = 0;
666 arch_install_hw_breakpoint(bp);
669 static void watchpoint_handler(unsigned long unknown, struct pt_regs *regs)
672 struct perf_event *wp, **slots;
673 struct arch_hw_breakpoint *info;
675 slots = (struct perf_event **)__get_cpu_var(wp_on_reg);
677 /* Without a disassembler, we can only handle 1 watchpoint. */
678 BUG_ON(core_num_wrps > 1);
680 for (i = 0; i < core_num_wrps; ++i) {
691 * The DFAR is an unknown value. Since we only allow a
692 * single watchpoint, we can set the trigger to the lowest
693 * possible faulting address.
695 info = counter_arch_bp(wp);
696 info->trigger = wp->attr.bp_addr;
697 pr_debug("watchpoint fired: address = 0x%x\n", info->trigger);
698 perf_bp_event(wp, regs);
701 * If no overflow handler is present, insert a temporary
702 * mismatch breakpoint so we can single-step over the
703 * watchpoint trigger.
705 if (!wp->overflow_handler)
706 enable_single_step(wp, instruction_pointer(regs));
712 static void watchpoint_single_step_handler(unsigned long pc)
715 struct perf_event *wp, **slots;
716 struct arch_hw_breakpoint *info;
718 slots = (struct perf_event **)__get_cpu_var(wp_on_reg);
720 for (i = 0; i < core_num_reserved_brps; ++i) {
728 info = counter_arch_bp(wp);
729 if (!info->step_ctrl.enabled)
733 * Restore the original watchpoint if we've completed the
736 if (info->trigger != pc)
737 disable_single_step(wp);
744 static void breakpoint_handler(unsigned long unknown, struct pt_regs *regs)
747 u32 ctrl_reg, val, addr;
748 struct perf_event *bp, **slots;
749 struct arch_hw_breakpoint *info;
750 struct arch_hw_breakpoint_ctrl ctrl;
752 slots = (struct perf_event **)__get_cpu_var(bp_on_reg);
754 /* The exception entry code places the amended lr in the PC. */
757 /* Check the currently installed breakpoints first. */
758 for (i = 0; i < core_num_brps; ++i) {
766 info = counter_arch_bp(bp);
768 /* Check if the breakpoint value matches. */
769 val = read_wb_reg(ARM_BASE_BVR + i);
770 if (val != (addr & ~0x3))
773 /* Possible match, check the byte address select to confirm. */
774 ctrl_reg = read_wb_reg(ARM_BASE_BCR + i);
775 decode_ctrl_reg(ctrl_reg, &ctrl);
776 if ((1 << (addr & 0x3)) & ctrl.len) {
777 info->trigger = addr;
778 pr_debug("breakpoint fired: address = 0x%x\n", addr);
779 perf_bp_event(bp, regs);
780 if (!bp->overflow_handler)
781 enable_single_step(bp, addr);
786 /* If we're stepping a breakpoint, it can now be restored. */
787 if (info->step_ctrl.enabled)
788 disable_single_step(bp);
793 /* Handle any pending watchpoint single-step breakpoints. */
794 watchpoint_single_step_handler(addr);
798 * Called from either the Data Abort Handler [watchpoint] or the
799 * Prefetch Abort Handler [breakpoint] with preemption disabled.
801 static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr,
802 struct pt_regs *regs)
807 /* We must be called with preemption disabled. */
808 WARN_ON(preemptible());
810 /* We only handle watchpoints and hardware breakpoints. */
811 ARM_DBG_READ(c1, 0, dscr);
813 /* Perform perf callbacks. */
814 switch (ARM_DSCR_MOE(dscr)) {
815 case ARM_ENTRY_BREAKPOINT:
816 breakpoint_handler(addr, regs);
818 case ARM_ENTRY_ASYNC_WATCHPOINT:
819 WARN(1, "Asynchronous watchpoint exception taken. Debugging results may be unreliable\n");
820 case ARM_ENTRY_SYNC_WATCHPOINT:
821 watchpoint_handler(addr, regs);
824 ret = 1; /* Unhandled fault. */
828 * Re-enable preemption after it was disabled in the
829 * low-level exception handling code.
837 * One-time initialisation.
839 static void reset_ctrl_regs(void *unused)
844 * v7 debug contains save and restore registers so that debug state
845 * can be maintained across low-power modes without leaving the debug
846 * logic powered up. It is IMPLEMENTATION DEFINED whether we can access
847 * the debug registers out of reset, so we must unlock the OS Lock
848 * Access Register to avoid taking undefined instruction exceptions
851 if (debug_arch >= ARM_DEBUG_ARCH_V7_ECP14) {
853 * Unconditionally clear the lock by writing a value
854 * other than 0xC5ACCE55 to the access register.
856 asm volatile("mcr p14, 0, %0, c1, c0, 4" : : "r" (0));
860 if (enable_monitor_mode())
863 /* We must also reset any reserved registers. */
864 for (i = 0; i < core_num_brps + core_num_reserved_brps; ++i) {
865 write_wb_reg(ARM_BASE_BCR + i, 0UL);
866 write_wb_reg(ARM_BASE_BVR + i, 0UL);
869 for (i = 0; i < core_num_wrps; ++i) {
870 write_wb_reg(ARM_BASE_WCR + i, 0UL);
871 write_wb_reg(ARM_BASE_WVR + i, 0UL);
875 static int __cpuinit dbg_reset_notify(struct notifier_block *self,
876 unsigned long action, void *cpu)
878 if (action == CPU_ONLINE)
879 smp_call_function_single((int)cpu, reset_ctrl_regs, NULL, 1);
883 static struct notifier_block __cpuinitdata dbg_reset_nb = {
884 .notifier_call = dbg_reset_notify,
887 static int __init arch_hw_breakpoint_init(void)
891 debug_arch = get_debug_arch();
893 if (!debug_arch_supported()) {
894 pr_info("debug architecture 0x%x unsupported.\n", debug_arch);
898 /* Determine how many BRPs/WRPs are available. */
899 core_num_brps = get_num_brps();
900 core_num_reserved_brps = get_num_reserved_brps();
901 core_num_wrps = get_num_wrps();
903 pr_info("found %d breakpoint and %d watchpoint registers.\n",
904 core_num_brps + core_num_reserved_brps, core_num_wrps);
906 if (core_num_reserved_brps)
907 pr_info("%d breakpoint(s) reserved for watchpoint "
908 "single-step.\n", core_num_reserved_brps);
911 * Reset the breakpoint resources. We assume that a halting
912 * debugger will leave the world in a nice state for us.
914 on_each_cpu(reset_ctrl_regs, NULL, 1);
916 ARM_DBG_READ(c1, 0, dscr);
917 if (dscr & ARM_DSCR_HDBGEN) {
918 max_watchpoint_len = 4;
919 pr_warning("halting debug mode enabled. Assuming maximum "
920 "watchpoint size of %u bytes.", max_watchpoint_len);
922 /* Work out the maximum supported watchpoint length. */
923 max_watchpoint_len = get_max_wp_len();
924 pr_info("maximum watchpoint size is %u bytes.\n",
928 /* Register debug fault handler. */
929 hook_fault_code(2, hw_breakpoint_pending, SIGTRAP, TRAP_HWBKPT,
930 "watchpoint debug exception");
931 hook_ifault_code(2, hw_breakpoint_pending, SIGTRAP, TRAP_HWBKPT,
932 "breakpoint debug exception");
934 /* Register hotplug notifier. */
935 register_cpu_notifier(&dbg_reset_nb);
938 arch_initcall(arch_hw_breakpoint_init);
940 void hw_breakpoint_pmu_read(struct perf_event *bp)
945 * Dummy function to register with die_notifier.
947 int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
948 unsigned long val, void *data)