2 * linux/arch/arm/kernel/iwmmxt.S
4 * XScale iWMMXt (Concan) context switching and handling
7 * Copyright (c) 2003, Intel Corporation
9 * Full lazy switching support, optimizations and more, by Nicolas Pitre
10 * Copyright (c) 2003-2004, MontaVista Software, Inc.
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/linkage.h>
18 #include <asm/ptrace.h>
19 #include <asm/thread_info.h>
20 #include <asm/asm-offsets.h>
21 #include <asm/assembler.h>
23 #if defined(CONFIG_CPU_PJ4) || defined(CONFIG_CPU_PJ4B)
24 #define PJ4(code...) code
26 #elif defined(CONFIG_CPU_MOHAWK) || \
27 defined(CONFIG_CPU_XSC3) || \
28 defined(CONFIG_CPU_XSCALE)
30 #define XSC(code...) code
32 #error "Unsupported iWMMXt architecture"
35 #define MMX_WR0 (0x00)
36 #define MMX_WR1 (0x08)
37 #define MMX_WR2 (0x10)
38 #define MMX_WR3 (0x18)
39 #define MMX_WR4 (0x20)
40 #define MMX_WR5 (0x28)
41 #define MMX_WR6 (0x30)
42 #define MMX_WR7 (0x38)
43 #define MMX_WR8 (0x40)
44 #define MMX_WR9 (0x48)
45 #define MMX_WR10 (0x50)
46 #define MMX_WR11 (0x58)
47 #define MMX_WR12 (0x60)
48 #define MMX_WR13 (0x68)
49 #define MMX_WR14 (0x70)
50 #define MMX_WR15 (0x78)
51 #define MMX_WCSSF (0x80)
52 #define MMX_WCASF (0x84)
53 #define MMX_WCGR0 (0x88)
54 #define MMX_WCGR1 (0x8C)
55 #define MMX_WCGR2 (0x90)
56 #define MMX_WCGR3 (0x94)
58 #define MMX_SIZE (0x98)
63 * Lazy switching of Concan coprocessor context
65 * r10 = struct thread_info pointer
66 * r9 = ret_from_exception
67 * lr = undefined instr exit
69 * called from prefetch exception handler with interrupts enabled
72 ENTRY(iwmmxt_task_enable)
73 inc_preempt_count r10, r3
75 XSC(mrc p15, 0, r2, c15, c1, 0)
76 PJ4(mrc p15, 0, r2, c1, c0, 2)
77 @ CP0 and CP1 accessible?
80 bne 4f @ if so no business here
81 @ enable access to CP0 and CP1
83 XSC(mcr p15, 0, r2, c15, c1, 0)
85 PJ4(mcr p15, 0, r2, c1, c0, 2)
88 add r0, r10, #TI_IWMMXT_STATE @ get task Concan save area
89 ldr r2, [sp, #60] @ current task pc value
90 ldr r1, [r3] @ get current Concan owner
91 str r0, [r3] @ this task now owns Concan regs
92 sub r2, r2, #4 @ adjust pc back
95 mrc p15, 0, r2, c2, c0, 0
99 #ifdef CONFIG_PREEMPT_COUNT
102 4: dec_preempt_count r10, r3
103 mov pc, r9 @ normal exit from exception
107 teq r1, #0 @ test for last ownership
108 beq concan_load @ no owner, skip save
118 wstrw wCSSF, [r1, #MMX_WCSSF]
119 wstrw wCASF, [r1, #MMX_WCASF]
120 wstrw wCGR0, [r1, #MMX_WCGR0]
121 wstrw wCGR1, [r1, #MMX_WCGR1]
122 wstrw wCGR2, [r1, #MMX_WCGR2]
123 wstrw wCGR3, [r1, #MMX_WCGR3]
129 wstrd wR0, [r1, #MMX_WR0]
130 wstrd wR1, [r1, #MMX_WR1]
131 wstrd wR2, [r1, #MMX_WR2]
132 wstrd wR3, [r1, #MMX_WR3]
133 wstrd wR4, [r1, #MMX_WR4]
134 wstrd wR5, [r1, #MMX_WR5]
135 wstrd wR6, [r1, #MMX_WR6]
136 wstrd wR7, [r1, #MMX_WR7]
137 wstrd wR8, [r1, #MMX_WR8]
138 wstrd wR9, [r1, #MMX_WR9]
139 wstrd wR10, [r1, #MMX_WR10]
140 wstrd wR11, [r1, #MMX_WR11]
141 wstrd wR12, [r1, #MMX_WR12]
142 wstrd wR13, [r1, #MMX_WR13]
143 wstrd wR14, [r1, #MMX_WR14]
144 wstrd wR15, [r1, #MMX_WR15]
146 2: teq r0, #0 @ anything to load?
147 moveq pc, lr @ if not, return
152 wldrd wR0, [r0, #MMX_WR0]
153 wldrd wR1, [r0, #MMX_WR1]
154 wldrd wR2, [r0, #MMX_WR2]
155 wldrd wR3, [r0, #MMX_WR3]
156 wldrd wR4, [r0, #MMX_WR4]
157 wldrd wR5, [r0, #MMX_WR5]
158 wldrd wR6, [r0, #MMX_WR6]
159 wldrd wR7, [r0, #MMX_WR7]
160 wldrd wR8, [r0, #MMX_WR8]
161 wldrd wR9, [r0, #MMX_WR9]
162 wldrd wR10, [r0, #MMX_WR10]
163 wldrd wR11, [r0, #MMX_WR11]
164 wldrd wR12, [r0, #MMX_WR12]
165 wldrd wR13, [r0, #MMX_WR13]
166 wldrd wR14, [r0, #MMX_WR14]
167 wldrd wR15, [r0, #MMX_WR15]
170 wldrw wCSSF, [r0, #MMX_WCSSF]
171 wldrw wCASF, [r0, #MMX_WCASF]
172 wldrw wCGR0, [r0, #MMX_WCGR0]
173 wldrw wCGR1, [r0, #MMX_WCGR1]
174 wldrw wCGR2, [r0, #MMX_WCGR2]
175 wldrw wCGR3, [r0, #MMX_WCGR3]
177 @ clear CUP/MUP (only if r1 != 0)
186 * Back up Concan regs to save area and disable access to them
187 * (mainly for gdb or sleep mode usage)
189 * r0 = struct thread_info pointer of target task or NULL for any
192 ENTRY(iwmmxt_task_disable)
197 orr r2, ip, #PSR_I_BIT @ disable interrupts
200 ldr r3, =concan_owner
201 add r2, r0, #TI_IWMMXT_STATE @ get task Concan save area
202 ldr r1, [r3] @ get current Concan owner
203 teq r1, #0 @ any current owner?
205 teq r0, #0 @ any owner?
206 teqne r1, r2 @ or specified one?
209 @ enable access to CP0 and CP1
210 XSC(mrc p15, 0, r4, c15, c1, 0)
211 XSC(orr r4, r4, #0x3)
212 XSC(mcr p15, 0, r4, c15, c1, 0)
213 PJ4(mrc p15, 0, r4, c1, c0, 2)
214 PJ4(orr r4, r4, #0xf)
215 PJ4(mcr p15, 0, r4, c1, c0, 2)
217 mov r0, #0 @ nothing to load
218 str r0, [r3] @ no more current owner
219 mrc p15, 0, r2, c2, c0, 0
223 @ disable access to CP0 and CP1
224 XSC(bic r4, r4, #0x3)
225 XSC(mcr p15, 0, r4, c15, c1, 0)
226 PJ4(bic r4, r4, #0xf)
227 PJ4(mcr p15, 0, r4, c1, c0, 2)
229 mrc p15, 0, r2, c2, c0, 0
232 1: msr cpsr_c, ip @ restore interrupt mode
236 * Copy Concan state to given memory address
238 * r0 = struct thread_info pointer of target task
239 * r1 = memory address where to store Concan state
241 * this is called mainly in the creation of signal stack frames
244 ENTRY(iwmmxt_task_copy)
247 orr r2, ip, #PSR_I_BIT @ disable interrupts
250 ldr r3, =concan_owner
251 add r2, r0, #TI_IWMMXT_STATE @ get task Concan save area
252 ldr r3, [r3] @ get current Concan owner
253 teq r2, r3 @ does this task own it...
256 @ current Concan values are in the task save area
257 msr cpsr_c, ip @ restore interrupt mode
263 1: @ this task owns Concan regs -- grab a copy from there
264 mov r0, #0 @ nothing to load
265 mov r2, #3 @ save all regs
266 mov r3, lr @ preserve return address
268 msr cpsr_c, ip @ restore interrupt mode
272 * Restore Concan state from given memory address
274 * r0 = struct thread_info pointer of target task
275 * r1 = memory address where to get Concan state from
277 * this is used to restore Concan state when unwinding a signal stack frame
280 ENTRY(iwmmxt_task_restore)
283 orr r2, ip, #PSR_I_BIT @ disable interrupts
286 ldr r3, =concan_owner
287 add r2, r0, #TI_IWMMXT_STATE @ get task Concan save area
288 ldr r3, [r3] @ get current Concan owner
289 bic r2, r2, #0x7 @ 64-bit alignment
290 teq r2, r3 @ does this task own it...
293 @ this task doesn't own Concan regs -- use its save area
294 msr cpsr_c, ip @ restore interrupt mode
299 1: @ this task owns Concan regs -- load them directly
301 mov r1, #0 @ don't clear CUP/MUP
302 mov r3, lr @ preserve return address
304 msr cpsr_c, ip @ restore interrupt mode
308 * Concan handling on task switch
310 * r0 = next thread_info pointer
312 * Called only from the iwmmxt notifier with task preemption disabled.
314 ENTRY(iwmmxt_task_switch)
316 XSC(mrc p15, 0, r1, c15, c1, 0)
317 PJ4(mrc p15, 0, r1, c1, c0, 2)
318 @ CP0 and CP1 accessible?
321 bne 1f @ yes: block them for next task
323 ldr r2, =concan_owner
324 add r3, r0, #TI_IWMMXT_STATE @ get next task Concan save area
325 ldr r2, [r2] @ get current Concan owner
326 teq r2, r3 @ next task owns it?
327 movne pc, lr @ no: leave Concan disabled
329 1: @ flip Concan access
330 XSC(eor r1, r1, #0x3)
331 XSC(mcr p15, 0, r1, c15, c1, 0)
332 PJ4(eor r1, r1, #0xf)
333 PJ4(mcr p15, 0, r1, c1, c0, 2)
335 mrc p15, 0, r1, c2, c0, 0
336 sub pc, lr, r1, lsr #32 @ cpwait and return
339 * Remove Concan ownership of given task
341 * r0 = struct thread_info pointer
343 ENTRY(iwmmxt_task_release)
346 orr ip, r2, #PSR_I_BIT @ disable interrupts
348 ldr r3, =concan_owner
349 add r0, r0, #TI_IWMMXT_STATE @ get task Concan save area
350 ldr r1, [r3] @ get current Concan owner
351 eors r0, r0, r1 @ if equal...
352 streq r0, [r3] @ then clear ownership
353 msr cpsr_c, r2 @ restore interrupts