4 * ARM performance counter support.
6 * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
7 * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
9 * This code is based on the sparc64 perf event code, which is in turn based
10 * on the x86 code. Callchain code is based on the ARM OProfile backtrace
13 #define pr_fmt(fmt) "hw perfevents: " fmt
15 #include <linux/kernel.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/uaccess.h>
20 #include <asm/irq_regs.h>
22 #include <asm/stacktrace.h>
25 armpmu_map_cache_event(const unsigned (*cache_map)
26 [PERF_COUNT_HW_CACHE_MAX]
27 [PERF_COUNT_HW_CACHE_OP_MAX]
28 [PERF_COUNT_HW_CACHE_RESULT_MAX],
31 unsigned int cache_type, cache_op, cache_result, ret;
33 cache_type = (config >> 0) & 0xff;
34 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
37 cache_op = (config >> 8) & 0xff;
38 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
41 cache_result = (config >> 16) & 0xff;
42 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
45 ret = (int)(*cache_map)[cache_type][cache_op][cache_result];
47 if (ret == CACHE_OP_UNSUPPORTED)
54 armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
58 if (config >= PERF_COUNT_HW_MAX)
61 mapping = (*event_map)[config];
62 return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
66 armpmu_map_raw_event(u32 raw_event_mask, u64 config)
68 return (int)(config & raw_event_mask);
72 armpmu_map_event(struct perf_event *event,
73 const unsigned (*event_map)[PERF_COUNT_HW_MAX],
74 const unsigned (*cache_map)
75 [PERF_COUNT_HW_CACHE_MAX]
76 [PERF_COUNT_HW_CACHE_OP_MAX]
77 [PERF_COUNT_HW_CACHE_RESULT_MAX],
80 u64 config = event->attr.config;
82 switch (event->attr.type) {
83 case PERF_TYPE_HARDWARE:
84 return armpmu_map_hw_event(event_map, config);
85 case PERF_TYPE_HW_CACHE:
86 return armpmu_map_cache_event(cache_map, config);
88 return armpmu_map_raw_event(raw_event_mask, config);
94 int armpmu_event_set_period(struct perf_event *event)
96 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
97 struct hw_perf_event *hwc = &event->hw;
98 s64 left = local64_read(&hwc->period_left);
99 s64 period = hwc->sample_period;
102 /* The period may have been changed by PERF_EVENT_IOC_PERIOD */
103 if (unlikely(period != hwc->last_period))
104 left = period - (hwc->last_period - left);
106 if (unlikely(left <= -period)) {
108 local64_set(&hwc->period_left, left);
109 hwc->last_period = period;
113 if (unlikely(left <= 0)) {
115 local64_set(&hwc->period_left, left);
116 hwc->last_period = period;
120 if (left > (s64)armpmu->max_period)
121 left = armpmu->max_period;
123 local64_set(&hwc->prev_count, (u64)-left);
125 armpmu->write_counter(event, (u64)(-left) & 0xffffffff);
127 perf_event_update_userpage(event);
132 u64 armpmu_event_update(struct perf_event *event)
134 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
135 struct hw_perf_event *hwc = &event->hw;
136 u64 delta, prev_raw_count, new_raw_count;
139 prev_raw_count = local64_read(&hwc->prev_count);
140 new_raw_count = armpmu->read_counter(event);
142 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
143 new_raw_count) != prev_raw_count)
146 delta = (new_raw_count - prev_raw_count) & armpmu->max_period;
148 local64_add(delta, &event->count);
149 local64_sub(delta, &hwc->period_left);
151 return new_raw_count;
155 armpmu_read(struct perf_event *event)
157 armpmu_event_update(event);
161 armpmu_stop(struct perf_event *event, int flags)
163 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
164 struct hw_perf_event *hwc = &event->hw;
167 * ARM pmu always has to update the counter, so ignore
168 * PERF_EF_UPDATE, see comments in armpmu_start().
170 if (!(hwc->state & PERF_HES_STOPPED)) {
171 armpmu->disable(event);
172 armpmu_event_update(event);
173 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
177 static void armpmu_start(struct perf_event *event, int flags)
179 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
180 struct hw_perf_event *hwc = &event->hw;
183 * ARM pmu always has to reprogram the period, so ignore
184 * PERF_EF_RELOAD, see the comment below.
186 if (flags & PERF_EF_RELOAD)
187 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
191 * Set the period again. Some counters can't be stopped, so when we
192 * were stopped we simply disabled the IRQ source and the counter
193 * may have been left counting. If we don't do this step then we may
194 * get an interrupt too soon or *way* too late if the overflow has
195 * happened since disabling.
197 armpmu_event_set_period(event);
198 armpmu->enable(event);
202 armpmu_del(struct perf_event *event, int flags)
204 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
205 struct pmu_hw_events *hw_events = armpmu->get_hw_events();
206 struct hw_perf_event *hwc = &event->hw;
209 armpmu_stop(event, PERF_EF_UPDATE);
210 hw_events->events[idx] = NULL;
211 clear_bit(idx, hw_events->used_mask);
213 perf_event_update_userpage(event);
217 armpmu_add(struct perf_event *event, int flags)
219 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
220 struct pmu_hw_events *hw_events = armpmu->get_hw_events();
221 struct hw_perf_event *hwc = &event->hw;
225 perf_pmu_disable(event->pmu);
227 /* If we don't have a space for the counter then finish early. */
228 idx = armpmu->get_event_idx(hw_events, event);
235 * If there is an event in the counter we are going to use then make
236 * sure it is disabled.
239 armpmu->disable(event);
240 hw_events->events[idx] = event;
242 hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
243 if (flags & PERF_EF_START)
244 armpmu_start(event, PERF_EF_RELOAD);
246 /* Propagate our changes to the userspace mapping. */
247 perf_event_update_userpage(event);
250 perf_pmu_enable(event->pmu);
255 validate_event(struct pmu_hw_events *hw_events,
256 struct perf_event *event)
258 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
259 struct pmu *leader_pmu = event->group_leader->pmu;
261 if (is_software_event(event))
264 if (event->pmu != leader_pmu || event->state < PERF_EVENT_STATE_OFF)
267 if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec)
270 return armpmu->get_event_idx(hw_events, event) >= 0;
274 validate_group(struct perf_event *event)
276 struct perf_event *sibling, *leader = event->group_leader;
277 struct pmu_hw_events fake_pmu;
278 DECLARE_BITMAP(fake_used_mask, ARMPMU_MAX_HWEVENTS);
281 * Initialise the fake PMU. We only need to populate the
282 * used_mask for the purposes of validation.
284 memset(fake_used_mask, 0, sizeof(fake_used_mask));
285 fake_pmu.used_mask = fake_used_mask;
287 if (!validate_event(&fake_pmu, leader))
290 list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
291 if (!validate_event(&fake_pmu, sibling))
295 if (!validate_event(&fake_pmu, event))
301 static irqreturn_t armpmu_dispatch_irq(int irq, void *dev)
303 struct arm_pmu *armpmu = (struct arm_pmu *) dev;
304 struct platform_device *plat_device = armpmu->plat_device;
305 struct arm_pmu_platdata *plat = dev_get_platdata(&plat_device->dev);
307 if (plat && plat->handle_irq)
308 return plat->handle_irq(irq, dev, armpmu->handle_irq);
310 return armpmu->handle_irq(irq, dev);
314 armpmu_release_hardware(struct arm_pmu *armpmu)
316 armpmu->free_irq(armpmu);
317 pm_runtime_put_sync(&armpmu->plat_device->dev);
321 armpmu_reserve_hardware(struct arm_pmu *armpmu)
324 struct platform_device *pmu_device = armpmu->plat_device;
329 pm_runtime_get_sync(&pmu_device->dev);
330 err = armpmu->request_irq(armpmu, armpmu_dispatch_irq);
332 armpmu_release_hardware(armpmu);
340 hw_perf_event_destroy(struct perf_event *event)
342 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
343 atomic_t *active_events = &armpmu->active_events;
344 struct mutex *pmu_reserve_mutex = &armpmu->reserve_mutex;
346 if (atomic_dec_and_mutex_lock(active_events, pmu_reserve_mutex)) {
347 armpmu_release_hardware(armpmu);
348 mutex_unlock(pmu_reserve_mutex);
353 event_requires_mode_exclusion(struct perf_event_attr *attr)
355 return attr->exclude_idle || attr->exclude_user ||
356 attr->exclude_kernel || attr->exclude_hv;
360 __hw_perf_event_init(struct perf_event *event)
362 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
363 struct hw_perf_event *hwc = &event->hw;
366 mapping = armpmu->map_event(event);
369 pr_debug("event %x:%llx not supported\n", event->attr.type,
375 * We don't assign an index until we actually place the event onto
376 * hardware. Use -1 to signify that we haven't decided where to put it
377 * yet. For SMP systems, each core has it's own PMU so we can't do any
378 * clever allocation or constraints checking at this point.
381 hwc->config_base = 0;
386 * Check whether we need to exclude the counter from certain modes.
388 if ((!armpmu->set_event_filter ||
389 armpmu->set_event_filter(hwc, &event->attr)) &&
390 event_requires_mode_exclusion(&event->attr)) {
391 pr_debug("ARM performance counters do not support "
397 * Store the event encoding into the config_base field.
399 hwc->config_base |= (unsigned long)mapping;
401 if (!hwc->sample_period) {
403 * For non-sampling runs, limit the sample_period to half
404 * of the counter width. That way, the new counter value
405 * is far less likely to overtake the previous one unless
406 * you have some serious IRQ latency issues.
408 hwc->sample_period = armpmu->max_period >> 1;
409 hwc->last_period = hwc->sample_period;
410 local64_set(&hwc->period_left, hwc->sample_period);
413 if (event->group_leader != event) {
414 if (validate_group(event) != 0)
421 static int armpmu_event_init(struct perf_event *event)
423 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
425 atomic_t *active_events = &armpmu->active_events;
427 /* does not support taken branch sampling */
428 if (has_branch_stack(event))
431 if (armpmu->map_event(event) == -ENOENT)
434 event->destroy = hw_perf_event_destroy;
436 if (!atomic_inc_not_zero(active_events)) {
437 mutex_lock(&armpmu->reserve_mutex);
438 if (atomic_read(active_events) == 0)
439 err = armpmu_reserve_hardware(armpmu);
442 atomic_inc(active_events);
443 mutex_unlock(&armpmu->reserve_mutex);
449 err = __hw_perf_event_init(event);
451 hw_perf_event_destroy(event);
456 static void armpmu_enable(struct pmu *pmu)
458 struct arm_pmu *armpmu = to_arm_pmu(pmu);
459 struct pmu_hw_events *hw_events = armpmu->get_hw_events();
460 int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
463 armpmu->start(armpmu);
466 static void armpmu_disable(struct pmu *pmu)
468 struct arm_pmu *armpmu = to_arm_pmu(pmu);
469 armpmu->stop(armpmu);
472 #ifdef CONFIG_PM_RUNTIME
473 static int armpmu_runtime_resume(struct device *dev)
475 struct arm_pmu_platdata *plat = dev_get_platdata(dev);
477 if (plat && plat->runtime_resume)
478 return plat->runtime_resume(dev);
483 static int armpmu_runtime_suspend(struct device *dev)
485 struct arm_pmu_platdata *plat = dev_get_platdata(dev);
487 if (plat && plat->runtime_suspend)
488 return plat->runtime_suspend(dev);
494 const struct dev_pm_ops armpmu_dev_pm_ops = {
495 SET_RUNTIME_PM_OPS(armpmu_runtime_suspend, armpmu_runtime_resume, NULL)
498 static void armpmu_init(struct arm_pmu *armpmu)
500 atomic_set(&armpmu->active_events, 0);
501 mutex_init(&armpmu->reserve_mutex);
503 armpmu->pmu = (struct pmu) {
504 .pmu_enable = armpmu_enable,
505 .pmu_disable = armpmu_disable,
506 .event_init = armpmu_event_init,
509 .start = armpmu_start,
515 int armpmu_register(struct arm_pmu *armpmu, int type)
518 pm_runtime_enable(&armpmu->plat_device->dev);
519 pr_info("enabled with %s PMU driver, %d counters available\n",
520 armpmu->name, armpmu->num_events);
521 return perf_pmu_register(&armpmu->pmu, armpmu->name, type);
525 * Callchain handling code.
529 * The registers we're interested in are at the end of the variable
530 * length saved register structure. The fp points at the end of this
531 * structure so the address of this struct is:
532 * (struct frame_tail *)(xxx->fp)-1
534 * This code has been adapted from the ARM OProfile support.
537 struct frame_tail __user *fp;
540 } __attribute__((packed));
543 * Get the return address for a single stackframe and return a pointer to the
546 static struct frame_tail __user *
547 user_backtrace(struct frame_tail __user *tail,
548 struct perf_callchain_entry *entry)
550 struct frame_tail buftail;
552 /* Also check accessibility of one struct frame_tail beyond */
553 if (!access_ok(VERIFY_READ, tail, sizeof(buftail)))
555 if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail)))
558 perf_callchain_store(entry, buftail.lr);
561 * Frame pointers should strictly progress back up the stack
562 * (towards higher addresses).
564 if (tail + 1 >= buftail.fp)
567 return buftail.fp - 1;
571 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
573 struct frame_tail __user *tail;
575 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
576 /* We don't support guest os callchain now */
580 perf_callchain_store(entry, regs->ARM_pc);
581 tail = (struct frame_tail __user *)regs->ARM_fp - 1;
583 while ((entry->nr < PERF_MAX_STACK_DEPTH) &&
584 tail && !((unsigned long)tail & 0x3))
585 tail = user_backtrace(tail, entry);
589 * Gets called by walk_stackframe() for every stackframe. This will be called
590 * whist unwinding the stackframe and is like a subroutine return so we use
594 callchain_trace(struct stackframe *fr,
597 struct perf_callchain_entry *entry = data;
598 perf_callchain_store(entry, fr->pc);
603 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
605 struct stackframe fr;
607 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
608 /* We don't support guest os callchain now */
612 fr.fp = regs->ARM_fp;
613 fr.sp = regs->ARM_sp;
614 fr.lr = regs->ARM_lr;
615 fr.pc = regs->ARM_pc;
616 walk_stackframe(&fr, callchain_trace, entry);
619 unsigned long perf_instruction_pointer(struct pt_regs *regs)
621 if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
622 return perf_guest_cbs->get_guest_ip();
624 return instruction_pointer(regs);
627 unsigned long perf_misc_flags(struct pt_regs *regs)
631 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
632 if (perf_guest_cbs->is_user_mode())
633 misc |= PERF_RECORD_MISC_GUEST_USER;
635 misc |= PERF_RECORD_MISC_GUEST_KERNEL;
638 misc |= PERF_RECORD_MISC_USER;
640 misc |= PERF_RECORD_MISC_KERNEL;