2 * arch/arm/mach-at91/at91sam9263.c
4 * Copyright (C) 2007 Atmel Corporation.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
13 #include <linux/module.h>
14 #include <linux/clk/at91_pmc.h>
16 #include <asm/proc-fns.h>
18 #include <asm/mach/arch.h>
19 #include <asm/mach/map.h>
20 #include <asm/system_misc.h>
21 #include <mach/at91sam9263.h>
24 #include "at91_rstc.h"
31 /* --------------------------------------------------------------------
33 * -------------------------------------------------------------------- */
36 * The peripheral clocks.
38 static struct clk pioA_clk = {
40 .pmc_mask = 1 << AT91SAM9263_ID_PIOA,
41 .type = CLK_TYPE_PERIPHERAL,
43 static struct clk pioB_clk = {
45 .pmc_mask = 1 << AT91SAM9263_ID_PIOB,
46 .type = CLK_TYPE_PERIPHERAL,
48 static struct clk pioCDE_clk = {
50 .pmc_mask = 1 << AT91SAM9263_ID_PIOCDE,
51 .type = CLK_TYPE_PERIPHERAL,
53 static struct clk usart0_clk = {
55 .pmc_mask = 1 << AT91SAM9263_ID_US0,
56 .type = CLK_TYPE_PERIPHERAL,
58 static struct clk usart1_clk = {
60 .pmc_mask = 1 << AT91SAM9263_ID_US1,
61 .type = CLK_TYPE_PERIPHERAL,
63 static struct clk usart2_clk = {
65 .pmc_mask = 1 << AT91SAM9263_ID_US2,
66 .type = CLK_TYPE_PERIPHERAL,
68 static struct clk mmc0_clk = {
70 .pmc_mask = 1 << AT91SAM9263_ID_MCI0,
71 .type = CLK_TYPE_PERIPHERAL,
73 static struct clk mmc1_clk = {
75 .pmc_mask = 1 << AT91SAM9263_ID_MCI1,
76 .type = CLK_TYPE_PERIPHERAL,
78 static struct clk can_clk = {
80 .pmc_mask = 1 << AT91SAM9263_ID_CAN,
81 .type = CLK_TYPE_PERIPHERAL,
83 static struct clk twi_clk = {
85 .pmc_mask = 1 << AT91SAM9263_ID_TWI,
86 .type = CLK_TYPE_PERIPHERAL,
88 static struct clk spi0_clk = {
90 .pmc_mask = 1 << AT91SAM9263_ID_SPI0,
91 .type = CLK_TYPE_PERIPHERAL,
93 static struct clk spi1_clk = {
95 .pmc_mask = 1 << AT91SAM9263_ID_SPI1,
96 .type = CLK_TYPE_PERIPHERAL,
98 static struct clk ssc0_clk = {
100 .pmc_mask = 1 << AT91SAM9263_ID_SSC0,
101 .type = CLK_TYPE_PERIPHERAL,
103 static struct clk ssc1_clk = {
105 .pmc_mask = 1 << AT91SAM9263_ID_SSC1,
106 .type = CLK_TYPE_PERIPHERAL,
108 static struct clk ac97_clk = {
110 .pmc_mask = 1 << AT91SAM9263_ID_AC97C,
111 .type = CLK_TYPE_PERIPHERAL,
113 static struct clk tcb_clk = {
115 .pmc_mask = 1 << AT91SAM9263_ID_TCB,
116 .type = CLK_TYPE_PERIPHERAL,
118 static struct clk pwm_clk = {
120 .pmc_mask = 1 << AT91SAM9263_ID_PWMC,
121 .type = CLK_TYPE_PERIPHERAL,
123 static struct clk macb_clk = {
125 .pmc_mask = 1 << AT91SAM9263_ID_EMAC,
126 .type = CLK_TYPE_PERIPHERAL,
128 static struct clk dma_clk = {
130 .pmc_mask = 1 << AT91SAM9263_ID_DMA,
131 .type = CLK_TYPE_PERIPHERAL,
133 static struct clk twodge_clk = {
135 .pmc_mask = 1 << AT91SAM9263_ID_2DGE,
136 .type = CLK_TYPE_PERIPHERAL,
138 static struct clk udc_clk = {
140 .pmc_mask = 1 << AT91SAM9263_ID_UDP,
141 .type = CLK_TYPE_PERIPHERAL,
143 static struct clk isi_clk = {
145 .pmc_mask = 1 << AT91SAM9263_ID_ISI,
146 .type = CLK_TYPE_PERIPHERAL,
148 static struct clk lcdc_clk = {
150 .pmc_mask = 1 << AT91SAM9263_ID_LCDC,
151 .type = CLK_TYPE_PERIPHERAL,
153 static struct clk ohci_clk = {
155 .pmc_mask = 1 << AT91SAM9263_ID_UHP,
156 .type = CLK_TYPE_PERIPHERAL,
159 static struct clk *periph_clocks[] __initdata = {
187 static struct clk_lookup periph_clocks_lookups[] = {
188 /* One additional fake clock for macb_hclk */
189 CLKDEV_CON_ID("hclk", &macb_clk),
190 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
191 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
192 CLKDEV_CON_DEV_ID("pclk", "fff98000.ssc", &ssc0_clk),
193 CLKDEV_CON_DEV_ID("pclk", "fff9c000.ssc", &ssc1_clk),
194 CLKDEV_CON_DEV_ID("hclk", "at91sam9263-lcdfb.0", &lcdc_clk),
195 CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
196 CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
197 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
198 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
199 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
200 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260.0", &twi_clk),
201 /* fake hclk clock */
202 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
203 CLKDEV_CON_ID("pioA", &pioA_clk),
204 CLKDEV_CON_ID("pioB", &pioB_clk),
205 CLKDEV_CON_ID("pioC", &pioCDE_clk),
206 CLKDEV_CON_ID("pioD", &pioCDE_clk),
207 CLKDEV_CON_ID("pioE", &pioCDE_clk),
208 /* more usart lookup table for DT entries */
209 CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
210 CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
211 CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
212 CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
213 /* more tc lookup table for DT entries */
214 CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb_clk),
215 CLKDEV_CON_DEV_ID("hclk", "a00000.ohci", &ohci_clk),
216 CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
217 CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
218 CLKDEV_CON_DEV_ID("mci_clk", "fff80000.mmc", &mmc0_clk),
219 CLKDEV_CON_DEV_ID("mci_clk", "fff84000.mmc", &mmc1_clk),
220 CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi_clk),
221 CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
222 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
223 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioCDE_clk),
224 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCDE_clk),
225 CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCDE_clk),
228 static struct clk_lookup usart_clocks_lookups[] = {
229 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
230 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
231 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
232 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
236 * The four programmable clocks.
237 * You must configure pin multiplexing to bring these signals out.
239 static struct clk pck0 = {
241 .pmc_mask = AT91_PMC_PCK0,
242 .type = CLK_TYPE_PROGRAMMABLE,
245 static struct clk pck1 = {
247 .pmc_mask = AT91_PMC_PCK1,
248 .type = CLK_TYPE_PROGRAMMABLE,
251 static struct clk pck2 = {
253 .pmc_mask = AT91_PMC_PCK2,
254 .type = CLK_TYPE_PROGRAMMABLE,
257 static struct clk pck3 = {
259 .pmc_mask = AT91_PMC_PCK3,
260 .type = CLK_TYPE_PROGRAMMABLE,
264 static void __init at91sam9263_register_clocks(void)
268 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
269 clk_register(periph_clocks[i]);
271 clkdev_add_table(periph_clocks_lookups,
272 ARRAY_SIZE(periph_clocks_lookups));
273 clkdev_add_table(usart_clocks_lookups,
274 ARRAY_SIZE(usart_clocks_lookups));
282 /* --------------------------------------------------------------------
284 * -------------------------------------------------------------------- */
286 static struct at91_gpio_bank at91sam9263_gpio[] __initdata = {
288 .id = AT91SAM9263_ID_PIOA,
289 .regbase = AT91SAM9263_BASE_PIOA,
291 .id = AT91SAM9263_ID_PIOB,
292 .regbase = AT91SAM9263_BASE_PIOB,
294 .id = AT91SAM9263_ID_PIOCDE,
295 .regbase = AT91SAM9263_BASE_PIOC,
297 .id = AT91SAM9263_ID_PIOCDE,
298 .regbase = AT91SAM9263_BASE_PIOD,
300 .id = AT91SAM9263_ID_PIOCDE,
301 .regbase = AT91SAM9263_BASE_PIOE,
305 /* --------------------------------------------------------------------
306 * AT91SAM9263 processor initialization
307 * -------------------------------------------------------------------- */
309 static void __init at91sam9263_map_io(void)
311 at91_init_sram(0, AT91SAM9263_SRAM0_BASE, AT91SAM9263_SRAM0_SIZE);
312 at91_init_sram(1, AT91SAM9263_SRAM1_BASE, AT91SAM9263_SRAM1_SIZE);
315 static void __init at91sam9263_ioremap_registers(void)
317 at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC);
318 at91_ioremap_rstc(AT91SAM9263_BASE_RSTC);
319 at91_ioremap_ramc(0, AT91SAM9263_BASE_SDRAMC0, 512);
320 at91_ioremap_ramc(1, AT91SAM9263_BASE_SDRAMC1, 512);
321 at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT);
322 at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0);
323 at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1);
324 at91_ioremap_matrix(AT91SAM9263_BASE_MATRIX);
325 at91_pm_set_standby(at91sam9_sdram_standby);
328 static void __init at91sam9263_initialize(void)
330 arm_pm_idle = at91sam9_idle;
331 arm_pm_restart = at91sam9_alt_restart;
333 at91_sysirq_mask_rtt(AT91SAM9263_BASE_RTT0);
334 at91_sysirq_mask_rtt(AT91SAM9263_BASE_RTT1);
336 /* Register GPIO subsystem */
337 at91_gpio_init(at91sam9263_gpio, 5);
340 /* --------------------------------------------------------------------
341 * Interrupt initialization
342 * -------------------------------------------------------------------- */
345 * The default interrupt priority levels (0 = lowest, 7 = highest).
347 static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
348 7, /* Advanced Interrupt Controller (FIQ) */
349 7, /* System Peripherals */
350 1, /* Parallel IO Controller A */
351 1, /* Parallel IO Controller B */
352 1, /* Parallel IO Controller C, D and E */
358 0, /* Multimedia Card Interface 0 */
359 0, /* Multimedia Card Interface 1 */
361 6, /* Two-Wire Interface */
362 5, /* Serial Peripheral Interface 0 */
363 5, /* Serial Peripheral Interface 1 */
364 4, /* Serial Synchronous Controller 0 */
365 4, /* Serial Synchronous Controller 1 */
366 5, /* AC97 Controller */
367 0, /* Timer Counter 0, 1 and 2 */
368 0, /* Pulse Width Modulation Controller */
371 0, /* 2D Graphic Engine */
372 2, /* USB Device Port */
373 0, /* Image Sensor Interface */
374 3, /* LDC Controller */
375 0, /* DMA Controller */
377 2, /* USB Host port */
378 0, /* Advanced Interrupt Controller (IRQ0) */
379 0, /* Advanced Interrupt Controller (IRQ1) */
382 AT91_SOC_START(at91sam9263)
383 .map_io = at91sam9263_map_io,
384 .default_irq_priority = at91sam9263_default_irq_priority,
385 .extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1),
386 .ioremap_registers = at91sam9263_ioremap_registers,
387 .register_clocks = at91sam9263_register_clocks,
388 .init = at91sam9263_initialize,