2 * AT91 Power Management
4 * Copyright (C) 2005 David Brownell
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 #ifndef __ARCH_ARM_MACH_AT91_PM
12 #define __ARCH_ARM_MACH_AT91_PM
14 #include <asm/proc-fns.h>
16 #include <mach/at91_ramc.h>
19 extern void at91_pm_set_standby(void (*at91_standby)(void));
21 static inline void at91_pm_set_standby(void (*at91_standby)(void)) { }
25 * The AT91RM9200 goes into self-refresh mode with this command, and will
26 * terminate self-refresh automatically on the next SDRAM access.
28 * Self-refresh mode is exited as soon as a memory access is made, but we don't
29 * know for sure when that happens. However, we need to restore the low-power
30 * mode if it was enabled before going idle. Restoring low-power mode while
31 * still in self-refresh is "not recommended", but seems to work.
34 static inline void at91rm9200_standby(void)
36 u32 lpr = at91_ramc_read(0, AT91RM9200_SDRAMC_LPR);
41 "1: mcr p15, 0, %0, c7, c10, 4\n\t"
42 " str %0, [%1, %2]\n\t"
43 " str %3, [%1, %4]\n\t"
44 " mcr p15, 0, %0, c7, c0, 4\n\t"
47 : "r" (0), "r" (at91_ramc_base[0]), "r" (AT91RM9200_SDRAMC_LPR),
48 "r" (1), "r" (AT91RM9200_SDRAMC_SRR),
52 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
55 static inline void at91_ddr_standby(void)
57 /* Those two values allow us to delay self-refresh activation
60 u32 saved_lpr0, saved_lpr1 = 0;
62 if (at91_ramc_base[1]) {
63 saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
64 lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
65 lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
68 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
69 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
70 lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
72 /* self-refresh mode now */
73 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
74 if (at91_ramc_base[1])
75 at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
79 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
80 if (at91_ramc_base[1])
81 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
84 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
87 static inline void at91sam9_sdram_standby(void)
90 u32 saved_lpr0, saved_lpr1 = 0;
92 if (at91_ramc_base[1]) {
93 saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
94 lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
95 lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
98 saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
99 lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
100 lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
102 /* self-refresh mode now */
103 at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
104 if (at91_ramc_base[1])
105 at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
109 at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
110 if (at91_ramc_base[1])
111 at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);