2 * arch/arm/mach-at91/pm_slow_clock.S
4 * Copyright (C) 2006 Savin Zlobec
7 * Copyright (C) 2007 Anti Sullin <anti.sullin@artecdesign.ee
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/linkage.h>
15 #include <linux/clk/at91_pmc.h>
16 #include <mach/at91_ramc.h>
19 #define SRAMC_SELF_FRESH_ACTIVE 0x01
20 #define SRAMC_SELF_FRESH_EXIT 0x00
27 * Wait until master clock is ready (after switching master clock source)
30 1: ldr tmp1, [pmc, #AT91_PMC_SR]
31 tst tmp1, #AT91_PMC_MCKRDY
36 * Wait until master oscillator has stabilized.
39 1: ldr tmp1, [pmc, #AT91_PMC_SR]
40 tst tmp1, #AT91_PMC_MOSCS
45 * Wait until PLLA has locked.
48 1: ldr tmp1, [pmc, #AT91_PMC_SR]
49 tst tmp1, #AT91_PMC_LOCKA
54 * Put the processor to enter the idle state
58 #if defined(CONFIG_CPU_V7)
59 mov tmp1, #AT91_PMC_PCK
60 str tmp1, [pmc, #AT91_PMC_SCDR]
64 wfi @ Wait For Interrupt
66 mcr p15, 0, tmp1, c7, c0, 4
76 * void at91_pm_suspend_in_sram(void __iomem *pmc, void __iomem *sdramc,
77 * void __iomem *ramc1, int memctrl)
79 * @r0: base address of AT91_PMC
80 * @r1: base address of SDRAM Controller (SDRAM, DDRSDR, or AT91_SYS)
81 * @r2: base address of second SDRAM Controller or 0 if not present
84 ENTRY(at91_pm_suspend_in_sram)
85 /* Save registers on stack */
86 stmfd sp!, {r4 - r12, lr}
88 /* Drain write buffer */
90 mcr p15, 0, tmp1, c7, c10, 4
96 and r0, r3, #AT91_PM_MEMTYPE_MASK
99 lsr r0, r3, #AT91_PM_MODE_OFFSET
100 and r0, r0, #AT91_PM_MODE_MASK
103 /* Active the self-refresh mode */
104 mov r0, #SRAMC_SELF_FRESH_ACTIVE
105 bl at91_sramc_self_refresh
108 tst r0, #AT91_PM_SLOW_CLOCK
109 beq skip_disable_main_clock
113 /* Save Master clock setting */
114 ldr tmp1, [pmc, #AT91_PMC_MCKR]
115 str tmp1, .saved_mckr
118 * Set the Master clock source to slow clock
120 bic tmp1, tmp1, #AT91_PMC_CSS
121 str tmp1, [pmc, #AT91_PMC_MCKR]
125 /* Save PLLA setting and disable it */
126 ldr tmp1, [pmc, #AT91_CKGR_PLLAR]
127 str tmp1, .saved_pllar
129 mov tmp1, #AT91_PMC_PLLCOUNT
130 orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */
131 str tmp1, [pmc, #AT91_CKGR_PLLAR]
133 /* Turn off the main oscillator */
134 ldr tmp1, [pmc, #AT91_CKGR_MOR]
135 bic tmp1, tmp1, #AT91_PMC_MOSCEN
136 orr tmp1, tmp1, #AT91_PMC_KEY
137 str tmp1, [pmc, #AT91_CKGR_MOR]
139 skip_disable_main_clock:
142 /* Wait for interrupt */
146 tst r0, #AT91_PM_SLOW_CLOCK
147 beq skip_enable_main_clock
151 /* Turn on the main oscillator */
152 ldr tmp1, [pmc, #AT91_CKGR_MOR]
153 orr tmp1, tmp1, #AT91_PMC_MOSCEN
154 orr tmp1, tmp1, #AT91_PMC_KEY
155 str tmp1, [pmc, #AT91_CKGR_MOR]
159 /* Restore PLLA setting */
160 ldr tmp1, .saved_pllar
161 str tmp1, [pmc, #AT91_CKGR_PLLAR]
163 tst tmp1, #(AT91_PMC_MUL & 0xff0000)
165 tst tmp1, #(AT91_PMC_MUL & ~0xff0000)
172 * Restore master clock setting
174 ldr tmp1, .saved_mckr
175 str tmp1, [pmc, #AT91_PMC_MCKR]
179 skip_enable_main_clock:
180 /* Exit the self-refresh mode */
181 mov r0, #SRAMC_SELF_FRESH_EXIT
182 bl at91_sramc_self_refresh
184 /* Restore registers, and return */
185 ldmfd sp!, {r4 - r12, pc}
186 ENDPROC(at91_pm_suspend_in_sram)
189 * void at91_sramc_self_refresh(unsigned int is_active)
192 * @r0: 1 - active self-refresh mode
193 * 0 - exit self-refresh mode
196 * @r2: base address of the sram controller
199 ENTRY(at91_sramc_self_refresh)
203 cmp r1, #AT91_MEMCTRL_MC
207 * at91rm9200 Memory controller
211 * For exiting the self-refresh mode, do nothing,
212 * automatically exit the self-refresh mode.
214 tst r0, #SRAMC_SELF_FRESH_ACTIVE
217 /* Active SDRAM self-refresh mode */
219 str r3, [r2, #AT91RM9200_SDRAMC_SRR]
223 cmp r1, #AT91_MEMCTRL_DDRSDR
227 * DDR Memory controller
229 tst r0, #SRAMC_SELF_FRESH_ACTIVE
232 /* LPDDR1 --> force DDR2 mode during self-refresh */
233 ldr r3, [r2, #AT91_DDRSDRC_MDR]
234 str r3, .saved_sam9_mdr
235 bic r3, r3, #~AT91_DDRSDRC_MD
236 cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR
237 ldreq r3, [r2, #AT91_DDRSDRC_MDR]
238 biceq r3, r3, #AT91_DDRSDRC_MD
239 orreq r3, r3, #AT91_DDRSDRC_MD_DDR2
240 streq r3, [r2, #AT91_DDRSDRC_MDR]
242 /* Active DDRC self-refresh mode */
243 ldr r3, [r2, #AT91_DDRSDRC_LPR]
244 str r3, .saved_sam9_lpr
245 bic r3, r3, #AT91_DDRSDRC_LPCB
246 orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
247 str r3, [r2, #AT91_DDRSDRC_LPR]
249 /* If using the 2nd ddr controller */
254 ldr r3, [r2, #AT91_DDRSDRC_MDR]
255 str r3, .saved_sam9_mdr1
256 bic r3, r3, #~AT91_DDRSDRC_MD
257 cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR
258 ldreq r3, [r2, #AT91_DDRSDRC_MDR]
259 biceq r3, r3, #AT91_DDRSDRC_MD
260 orreq r3, r3, #AT91_DDRSDRC_MD_DDR2
261 streq r3, [r2, #AT91_DDRSDRC_MDR]
263 /* Active DDRC self-refresh mode */
264 ldr r3, [r2, #AT91_DDRSDRC_LPR]
265 str r3, .saved_sam9_lpr1
266 bic r3, r3, #AT91_DDRSDRC_LPCB
267 orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
268 str r3, [r2, #AT91_DDRSDRC_LPR]
274 /* Restore MDR in case of LPDDR1 */
275 ldr r3, .saved_sam9_mdr
276 str r3, [r2, #AT91_DDRSDRC_MDR]
277 /* Restore LPR on AT91 with DDRAM */
278 ldr r3, .saved_sam9_lpr
279 str r3, [r2, #AT91_DDRSDRC_LPR]
281 /* If using the 2nd ddr controller */
284 ldrne r3, .saved_sam9_mdr1
285 strne r3, [r2, #AT91_DDRSDRC_MDR]
286 ldrne r3, .saved_sam9_lpr1
287 strne r3, [r2, #AT91_DDRSDRC_LPR]
292 * SDRAMC Memory controller
295 tst r0, #SRAMC_SELF_FRESH_ACTIVE
298 /* Active SDRAMC self-refresh mode */
299 ldr r3, [r2, #AT91_SDRAMC_LPR]
300 str r3, .saved_sam9_lpr
301 bic r3, r3, #AT91_SDRAMC_LPCB
302 orr r3, r3, #AT91_SDRAMC_LPCB_SELF_REFRESH
303 str r3, [r2, #AT91_SDRAMC_LPR]
306 ldr r3, .saved_sam9_lpr
307 str r3, [r2, #AT91_SDRAMC_LPR]
311 ENDPROC(at91_sramc_self_refresh)
336 ENTRY(at91_pm_suspend_in_sram_sz)
337 .word .-at91_pm_suspend_in_sram