arch/arm/mach-at91/setup.c

   1 /*
   2  * Copyright (C) 2007 Atmel Corporation.
   3  * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
   4  *
   5  * Under GPLv2
   6  */
   7
   8 #include <linux/module.h>
   9 #include <linux/io.h>
  10 #include <linux/mm.h>
  11 #include <linux/pm.h>
  12 #include <linux/of_address.h>
  13 #include <linux/pinctrl/machine.h>
  14 #include <linux/clk/at91_pmc.h>
  15
  16 #include <asm/system_misc.h>
  17 #include <asm/mach/map.h>
  18
  19 #include <mach/hardware.h>
  20 #include <mach/cpu.h>
  21 #include <mach/at91_dbgu.h>
  22
  23 #include "at91_shdwc.h"
  24 #include "soc.h"
  25 #include "generic.h"
  26 #include "pm.h"
  27
  28 struct at91_init_soc __initdata at91_boot_soc;
  29
  30 struct at91_socinfo at91_soc_initdata;
  31 EXPORT_SYMBOL(at91_soc_initdata);
  32
  33 void __init at91rm9200_set_type(int type)
  34 {
  35         if (type == ARCH_REVISON_9200_PQFP)
  36                 at91_soc_initdata.subtype = AT91_SOC_RM9200_PQFP;
  37         else
  38                 at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
  39
  40         pr_info("AT91: filled in soc subtype: %s\n",
  41                 at91_get_soc_subtype(&at91_soc_initdata));
  42 }
  43
  44 void __init at91_init_irq_default(void)
  45 {
  46         at91_init_interrupts(at91_boot_soc.default_irq_priority);
  47 }
  48
  49 void __init at91_init_interrupts(unsigned int *priority)
  50 {
  51         /* Initialize the AIC interrupt controller */
  52         at91_aic_init(priority, at91_boot_soc.extern_irq);
  53
  54         /* Enable GPIO interrupts */
  55         at91_gpio_irq_setup();
  56 }
  57
  58 void __iomem *at91_ramc_base[2];
  59 EXPORT_SYMBOL_GPL(at91_ramc_base);
  60
  61 void __init at91_ioremap_ramc(int id, u32 addr, u32 size)
  62 {
  63         if (id < 0 || id > 1) {
  64                 pr_emerg("Wrong RAM controller id (%d), cannot continue\n", id);
  65                 BUG();
  66         }
  67         at91_ramc_base[id] = ioremap(addr, size);
  68         if (!at91_ramc_base[id])
  69                 panic("Impossible to ioremap ramc.%d 0x%x\n", id, addr);
  70 }
  71
  72 static struct map_desc sram_desc[2] __initdata;
  73
  74 void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
  75 {
  76         struct map_desc *desc = &sram_desc[bank];
  77
  78         desc->virtual = (unsigned long)AT91_IO_VIRT_BASE - length;
  79         if (bank > 0)
  80                 desc->virtual -= sram_desc[bank - 1].length;
  81
  82         desc->pfn = __phys_to_pfn(base);
  83         desc->length = length;
  84         desc->type = MT_MEMORY_RWX_NONCACHED;
  85
  86         pr_info("AT91: sram at 0x%lx of 0x%x mapped at 0x%lx\n",
  87                 base, length, desc->virtual);
  88
  89         iotable_init(desc, 1);
  90 }
  91
  92 static struct map_desc at91_io_desc __initdata __maybe_unused = {
  93         .virtual        = (unsigned long)AT91_VA_BASE_SYS,
  94         .pfn            = __phys_to_pfn(AT91_BASE_SYS),
  95         .length         = SZ_16K,
  96         .type           = MT_DEVICE,
  97 };
  98
  99 static struct map_desc at91_alt_io_desc __initdata __maybe_unused = {
 100         .virtual        = (unsigned long)AT91_ALT_VA_BASE_SYS,
 101         .pfn            = __phys_to_pfn(AT91_ALT_BASE_SYS),
 102         .length         = 24 * SZ_1K,
 103         .type           = MT_DEVICE,
 104 };
 105
 106 static void __init soc_detect(u32 dbgu_base)
 107 {
 108         u32 cidr, socid;
 109
 110         cidr = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
 111         socid = cidr & ~AT91_CIDR_VERSION;
 112
 113         switch (socid) {
 114         case ARCH_ID_AT91RM9200:
 115                 at91_soc_initdata.type = AT91_SOC_RM9200;
 116                 if (at91_soc_initdata.subtype == AT91_SOC_SUBTYPE_UNKNOWN)
 117                         at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
 118                 at91_boot_soc = at91rm9200_soc;
 119                 break;
 120
 121         case ARCH_ID_AT91SAM9260:
 122                 at91_soc_initdata.type = AT91_SOC_SAM9260;
 123                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
 124                 at91_boot_soc = at91sam9260_soc;
 125                 break;
 126
 127         case ARCH_ID_AT91SAM9261:
 128                 at91_soc_initdata.type = AT91_SOC_SAM9261;
 129                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
 130                 at91_boot_soc = at91sam9261_soc;
 131                 break;
 132
 133         case ARCH_ID_AT91SAM9263:
 134                 at91_soc_initdata.type = AT91_SOC_SAM9263;
 135                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
 136                 at91_boot_soc = at91sam9263_soc;
 137                 break;
 138
 139         case ARCH_ID_AT91SAM9G20:
 140                 at91_soc_initdata.type = AT91_SOC_SAM9G20;
 141                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
 142                 at91_boot_soc = at91sam9260_soc;
 143                 break;
 144
 145         case ARCH_ID_AT91SAM9G45:
 146                 at91_soc_initdata.type = AT91_SOC_SAM9G45;
 147                 if (cidr == ARCH_ID_AT91SAM9G45ES)
 148                         at91_soc_initdata.subtype = AT91_SOC_SAM9G45ES;
 149                 at91_boot_soc = at91sam9g45_soc;
 150                 break;
 151
 152         case ARCH_ID_AT91SAM9RL64:
 153                 at91_soc_initdata.type = AT91_SOC_SAM9RL;
 154                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
 155                 at91_boot_soc = at91sam9rl_soc;
 156                 break;
 157
 158         case ARCH_ID_AT91SAM9X5:
 159                 at91_soc_initdata.type = AT91_SOC_SAM9X5;
 160                 at91_boot_soc = at91sam9x5_soc;
 161                 break;
 162
 163         case ARCH_ID_AT91SAM9N12:
 164                 at91_soc_initdata.type = AT91_SOC_SAM9N12;
 165                 at91_boot_soc = at91sam9n12_soc;
 166                 break;
 167
 168         case ARCH_ID_SAMA5:
 169                 at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
 170                 if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D3) {
 171                         at91_soc_initdata.type = AT91_SOC_SAMA5D3;
 172                         at91_boot_soc = sama5d3_soc;
 173                 }
 174                 break;
 175         }
 176
 177         /* at91sam9g10 */
 178         if ((socid & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
 179                 at91_soc_initdata.type = AT91_SOC_SAM9G10;
 180                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
 181                 at91_boot_soc = at91sam9261_soc;
 182         }
 183         /* at91sam9xe */
 184         else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) {
 185                 at91_soc_initdata.type = AT91_SOC_SAM9260;
 186                 at91_soc_initdata.subtype = AT91_SOC_SAM9XE;
 187                 at91_boot_soc = at91sam9260_soc;
 188         }
 189
 190         if (!at91_soc_is_detected())
 191                 return;
 192
 193         at91_soc_initdata.cidr = cidr;
 194
 195         /* sub version of soc */
 196         if (!at91_soc_initdata.exid)
 197                 at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
 198
 199         if (at91_soc_initdata.type == AT91_SOC_SAM9G45) {
 200                 switch (at91_soc_initdata.exid) {
 201                 case ARCH_EXID_AT91SAM9M10:
 202                         at91_soc_initdata.subtype = AT91_SOC_SAM9M10;
 203                         break;
 204                 case ARCH_EXID_AT91SAM9G46:
 205                         at91_soc_initdata.subtype = AT91_SOC_SAM9G46;
 206                         break;
 207                 case ARCH_EXID_AT91SAM9M11:
 208                         at91_soc_initdata.subtype = AT91_SOC_SAM9M11;
 209                         break;
 210                 }
 211         }
 212
 213         if (at91_soc_initdata.type == AT91_SOC_SAM9X5) {
 214                 switch (at91_soc_initdata.exid) {
 215                 case ARCH_EXID_AT91SAM9G15:
 216                         at91_soc_initdata.subtype = AT91_SOC_SAM9G15;
 217                         break;
 218                 case ARCH_EXID_AT91SAM9G35:
 219                         at91_soc_initdata.subtype = AT91_SOC_SAM9G35;
 220                         break;
 221                 case ARCH_EXID_AT91SAM9X35:
 222                         at91_soc_initdata.subtype = AT91_SOC_SAM9X35;
 223                         break;
 224                 case ARCH_EXID_AT91SAM9G25:
 225                         at91_soc_initdata.subtype = AT91_SOC_SAM9G25;
 226                         break;
 227                 case ARCH_EXID_AT91SAM9X25:
 228                         at91_soc_initdata.subtype = AT91_SOC_SAM9X25;
 229                         break;
 230                 }
 231         }
 232
 233         if (at91_soc_initdata.type == AT91_SOC_SAMA5D3) {
 234                 switch (at91_soc_initdata.exid) {
 235                 case ARCH_EXID_SAMA5D31:
 236                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D31;
 237                         break;
 238                 case ARCH_EXID_SAMA5D33:
 239                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D33;
 240                         break;
 241                 case ARCH_EXID_SAMA5D34:
 242                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D34;
 243                         break;
 244                 case ARCH_EXID_SAMA5D35:
 245                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D35;
 246                         break;
 247                 case ARCH_EXID_SAMA5D36:
 248                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D36;
 249                         break;
 250                 }
 251         }
 252 }
 253
 254 static void __init alt_soc_detect(u32 dbgu_base)
 255 {
 256         u32 cidr, socid;
 257
 258         /* SoC ID */
 259         cidr = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
 260         socid = cidr & ~AT91_CIDR_VERSION;
 261
 262         switch (socid) {
 263         case ARCH_ID_SAMA5:
 264                 at91_soc_initdata.exid = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
 265                 if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D3) {
 266                         at91_soc_initdata.type = AT91_SOC_SAMA5D3;
 267                         at91_boot_soc = sama5d3_soc;
 268                 } else if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D4) {
 269                         at91_soc_initdata.type = AT91_SOC_SAMA5D4;
 270                         at91_boot_soc = sama5d4_soc;
 271                 }
 272                 break;
 273         }
 274
 275         if (!at91_soc_is_detected())
 276                 return;
 277
 278         at91_soc_initdata.cidr = cidr;
 279
 280         /* sub version of soc */
 281         if (!at91_soc_initdata.exid)
 282                 at91_soc_initdata.exid = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
 283
 284         if (at91_soc_initdata.type == AT91_SOC_SAMA5D4) {
 285                 switch (at91_soc_initdata.exid) {
 286                 case ARCH_EXID_SAMA5D41:
 287                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D41;
 288                         break;
 289                 case ARCH_EXID_SAMA5D42:
 290                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D42;
 291                         break;
 292                 case ARCH_EXID_SAMA5D43:
 293                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D43;
 294                         break;
 295                 case ARCH_EXID_SAMA5D44:
 296                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D44;
 297                         break;
 298                 }
 299         }
 300 }
 301
 302 static const char *soc_name[] = {
 303         [AT91_SOC_RM9200]       = "at91rm9200",
 304         [AT91_SOC_SAM9260]      = "at91sam9260",
 305         [AT91_SOC_SAM9261]      = "at91sam9261",
 306         [AT91_SOC_SAM9263]      = "at91sam9263",
 307         [AT91_SOC_SAM9G10]      = "at91sam9g10",
 308         [AT91_SOC_SAM9G20]      = "at91sam9g20",
 309         [AT91_SOC_SAM9G45]      = "at91sam9g45",
 310         [AT91_SOC_SAM9RL]       = "at91sam9rl",
 311         [AT91_SOC_SAM9X5]       = "at91sam9x5",
 312         [AT91_SOC_SAM9N12]      = "at91sam9n12",
 313         [AT91_SOC_SAMA5D3]      = "sama5d3",
 314         [AT91_SOC_SAMA5D4]      = "sama5d4",
 315         [AT91_SOC_UNKNOWN]      = "Unknown",
 316 };
 317
 318 const char *at91_get_soc_type(struct at91_socinfo *c)
 319 {
 320         return soc_name[c->type];
 321 }
 322 EXPORT_SYMBOL(at91_get_soc_type);
 323
 324 static const char *soc_subtype_name[] = {
 325         [AT91_SOC_RM9200_BGA]   = "at91rm9200 BGA",
 326         [AT91_SOC_RM9200_PQFP]  = "at91rm9200 PQFP",
 327         [AT91_SOC_SAM9XE]       = "at91sam9xe",
 328         [AT91_SOC_SAM9G45ES]    = "at91sam9g45es",
 329         [AT91_SOC_SAM9M10]      = "at91sam9m10",
 330         [AT91_SOC_SAM9G46]      = "at91sam9g46",
 331         [AT91_SOC_SAM9M11]      = "at91sam9m11",
 332         [AT91_SOC_SAM9G15]      = "at91sam9g15",
 333         [AT91_SOC_SAM9G35]      = "at91sam9g35",
 334         [AT91_SOC_SAM9X35]      = "at91sam9x35",
 335         [AT91_SOC_SAM9G25]      = "at91sam9g25",
 336         [AT91_SOC_SAM9X25]      = "at91sam9x25",
 337         [AT91_SOC_SAMA5D31]     = "sama5d31",
 338         [AT91_SOC_SAMA5D33]     = "sama5d33",
 339         [AT91_SOC_SAMA5D34]     = "sama5d34",
 340         [AT91_SOC_SAMA5D35]     = "sama5d35",
 341         [AT91_SOC_SAMA5D36]     = "sama5d36",
 342         [AT91_SOC_SAMA5D41]     = "sama5d41",
 343         [AT91_SOC_SAMA5D42]     = "sama5d42",
 344         [AT91_SOC_SAMA5D43]     = "sama5d43",
 345         [AT91_SOC_SAMA5D44]     = "sama5d44",
 346         [AT91_SOC_SUBTYPE_NONE] = "None",
 347         [AT91_SOC_SUBTYPE_UNKNOWN] = "Unknown",
 348 };
 349
 350 const char *at91_get_soc_subtype(struct at91_socinfo *c)
 351 {
 352         return soc_subtype_name[c->subtype];
 353 }
 354 EXPORT_SYMBOL(at91_get_soc_subtype);
 355
 356 void __init at91_map_io(void)
 357 {
 358         /* Map peripherals */
 359         iotable_init(&at91_io_desc, 1);
 360
 361         at91_soc_initdata.type = AT91_SOC_UNKNOWN;
 362         at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_UNKNOWN;
 363
 364         soc_detect(AT91_BASE_DBGU0);
 365         if (!at91_soc_is_detected())
 366                 soc_detect(AT91_BASE_DBGU1);
 367
 368         if (!at91_soc_is_detected())
 369                 panic("AT91: Impossible to detect the SOC type");
 370
 371         pr_info("AT91: Detected soc type: %s\n",
 372                 at91_get_soc_type(&at91_soc_initdata));
 373         if (at91_soc_initdata.subtype != AT91_SOC_SUBTYPE_NONE)
 374                 pr_info("AT91: Detected soc subtype: %s\n",
 375                         at91_get_soc_subtype(&at91_soc_initdata));
 376
 377         if (!at91_soc_is_enabled())
 378                 panic("AT91: Soc not enabled");
 379
 380         if (at91_boot_soc.map_io)
 381                 at91_boot_soc.map_io();
 382 }
 383
 384 void __iomem *at91_shdwc_base = NULL;
 385
 386 static void at91sam9_poweroff(void)
 387 {
 388         at91_shdwc_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
 389 }
 390
 391 void __init at91_ioremap_shdwc(u32 base_addr)
 392 {
 393         at91_shdwc_base = ioremap(base_addr, 16);
 394         if (!at91_shdwc_base)
 395                 panic("Impossible to ioremap at91_shdwc_base\n");
 396         pm_power_off = at91sam9_poweroff;
 397 }
 398
 399 void __iomem *at91_rstc_base;
 400
 401 void __init at91_ioremap_rstc(u32 base_addr)
 402 {
 403         at91_rstc_base = ioremap(base_addr, 16);
 404         if (!at91_rstc_base)
 405                 panic("Impossible to ioremap at91_rstc_base\n");
 406 }
 407
 408 void __init at91_alt_map_io(void)
 409 {
 410         /* Map peripherals */
 411         iotable_init(&at91_alt_io_desc, 1);
 412
 413         at91_soc_initdata.type = AT91_SOC_UNKNOWN;
 414         at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_UNKNOWN;
 415
 416         alt_soc_detect(AT91_BASE_DBGU2);
 417         if (!at91_soc_is_detected())
 418                 panic("AT91: Impossible to detect the SOC type");
 419
 420         pr_info("AT91: Detected soc type: %s\n",
 421                 at91_get_soc_type(&at91_soc_initdata));
 422         if (at91_soc_initdata.subtype != AT91_SOC_SUBTYPE_NONE)
 423                 pr_info("AT91: Detected soc subtype: %s\n",
 424                         at91_get_soc_subtype(&at91_soc_initdata));
 425
 426         if (!at91_soc_is_enabled())
 427                 panic("AT91: Soc not enabled");
 428
 429         if (at91_boot_soc.map_io)
 430                 at91_boot_soc.map_io();
 431 }
 432
 433 void __iomem *at91_matrix_base;
 434 EXPORT_SYMBOL_GPL(at91_matrix_base);
 435
 436 void __init at91_ioremap_matrix(u32 base_addr)
 437 {
 438         at91_matrix_base = ioremap(base_addr, 512);
 439         if (!at91_matrix_base)
 440                 panic("Impossible to ioremap at91_matrix_base\n");
 441 }
 442
 443 #if defined(CONFIG_OF) && !defined(CONFIG_ARCH_AT91X40)
 444 static struct of_device_id rstc_ids[] = {
 445         { .compatible = "atmel,at91sam9260-rstc", .data = at91sam9_alt_restart },
 446         { .compatible = "atmel,at91sam9g45-rstc", .data = at91sam9g45_restart },
 447         { /*sentinel*/ }
 448 };
 449
 450 static void at91_dt_rstc(void)
 451 {
 452         struct device_node *np;
 453         const struct of_device_id *of_id;
 454
 455         np = of_find_matching_node(NULL, rstc_ids);
 456         if (!np)
 457                 panic("unable to find compatible rstc node in dtb\n");
 458
 459         at91_rstc_base = of_iomap(np, 0);
 460         if (!at91_rstc_base)
 461                 panic("unable to map rstc cpu registers\n");
 462
 463         of_id = of_match_node(rstc_ids, np);
 464         if (!of_id)
 465                 panic("AT91: rtsc no restart function available\n");
 466
 467         arm_pm_restart = of_id->data;
 468
 469         of_node_put(np);
 470 }
 471
 472 static struct of_device_id ramc_ids[] = {
 473         { .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
 474         { .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
 475         { .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby },
 476         { /*sentinel*/ }
 477 };
 478
 479 static void at91_dt_ramc(void)
 480 {
 481         struct device_node *np;
 482         const struct of_device_id *of_id;
 483
 484         np = of_find_matching_node(NULL, ramc_ids);
 485         if (!np)
 486                 panic("unable to find compatible ram controller node in dtb\n");
 487
 488         at91_ramc_base[0] = of_iomap(np, 0);
 489         if (!at91_ramc_base[0])
 490                 panic("unable to map ramc[0] cpu registers\n");
 491         /* the controller may have 2 banks */
 492         at91_ramc_base[1] = of_iomap(np, 1);
 493
 494         of_id = of_match_node(ramc_ids, np);
 495         if (!of_id)
 496                 pr_warn("AT91: ramc no standby function available\n");
 497         else
 498                 at91_pm_set_standby(of_id->data);
 499
 500         of_node_put(np);
 501 }
 502
 503 static struct of_device_id shdwc_ids[] = {
 504         { .compatible = "atmel,at91sam9260-shdwc", },
 505         { .compatible = "atmel,at91sam9rl-shdwc", },
 506         { .compatible = "atmel,at91sam9x5-shdwc", },
 507         { /*sentinel*/ }
 508 };
 509
 510 static const char *shdwc_wakeup_modes[] = {
 511         [AT91_SHDW_WKMODE0_NONE]        = "none",
 512         [AT91_SHDW_WKMODE0_HIGH]        = "high",
 513         [AT91_SHDW_WKMODE0_LOW]         = "low",
 514         [AT91_SHDW_WKMODE0_ANYLEVEL]    = "any",
 515 };
 516
 517 const int at91_dtget_shdwc_wakeup_mode(struct device_node *np)
 518 {
 519         const char *pm;
 520         int err, i;
 521
 522         err = of_property_read_string(np, "atmel,wakeup-mode", &pm);
 523         if (err < 0)
 524                 return AT91_SHDW_WKMODE0_ANYLEVEL;
 525
 526         for (i = 0; i < ARRAY_SIZE(shdwc_wakeup_modes); i++)
 527                 if (!strcasecmp(pm, shdwc_wakeup_modes[i]))
 528                         return i;
 529
 530         return -ENODEV;
 531 }
 532
 533 static void at91_dt_shdwc(void)
 534 {
 535         struct device_node *np;
 536         int wakeup_mode;
 537         u32 reg;
 538         u32 mode = 0;
 539
 540         np = of_find_matching_node(NULL, shdwc_ids);
 541         if (!np) {
 542                 pr_debug("AT91: unable to find compatible shutdown (shdwc) controller node in dtb\n");
 543                 return;
 544         }
 545
 546         at91_shdwc_base = of_iomap(np, 0);
 547         if (!at91_shdwc_base)
 548                 panic("AT91: unable to map shdwc cpu registers\n");
 549
 550         wakeup_mode = at91_dtget_shdwc_wakeup_mode(np);
 551         if (wakeup_mode < 0) {
 552                 pr_warn("AT91: shdwc unknown wakeup mode\n");
 553                 goto end;
 554         }
 555
 556         if (!of_property_read_u32(np, "atmel,wakeup-counter", &reg)) {
 557                 if (reg > AT91_SHDW_CPTWK0_MAX) {
 558                         pr_warn("AT91: shdwc wakeup counter 0x%x > 0x%x reduce it to 0x%x\n",
 559                                 reg, AT91_SHDW_CPTWK0_MAX, AT91_SHDW_CPTWK0_MAX);
 560                         reg = AT91_SHDW_CPTWK0_MAX;
 561                 }
 562                 mode |= AT91_SHDW_CPTWK0_(reg);
 563         }
 564
 565         if (of_property_read_bool(np, "atmel,wakeup-rtc-timer"))
 566                         mode |= AT91_SHDW_RTCWKEN;
 567
 568         if (of_property_read_bool(np, "atmel,wakeup-rtt-timer"))
 569                         mode |= AT91_SHDW_RTTWKEN;
 570
 571         at91_shdwc_write(AT91_SHDW_MR, wakeup_mode | mode);
 572
 573 end:
 574         pm_power_off = at91sam9_poweroff;
 575
 576         of_node_put(np);
 577 }
 578
 579 void __init at91rm9200_dt_initialize(void)
 580 {
 581         at91_dt_ramc();
 582
 583         /* Init clock subsystem */
 584         at91_dt_clock_init();
 585
 586         /* Register the processor-specific clocks */
 587         if (at91_boot_soc.register_clocks)
 588                 at91_boot_soc.register_clocks();
 589
 590         at91_boot_soc.init();
 591 }
 592
 593 void __init at91_dt_initialize(void)
 594 {
 595         at91_dt_rstc();
 596         at91_dt_ramc();
 597         at91_dt_shdwc();
 598
 599         /* Init clock subsystem */
 600         at91_dt_clock_init();
 601
 602         /* Register the processor-specific clocks */
 603         if (at91_boot_soc.register_clocks)
 604                 at91_boot_soc.register_clocks();
 605
 606         if (at91_boot_soc.init)
 607                 at91_boot_soc.init();
 608 }
 609 #endif
 610
 611 void __init at91_initialize(unsigned long main_clock)
 612 {
 613         at91_boot_soc.ioremap_registers();
 614
 615         /* Init clock subsystem */
 616         at91_clock_init(main_clock);
 617
 618         /* Register the processor-specific clocks */
 619         at91_boot_soc.register_clocks();
 620
 621         at91_boot_soc.init();
 622
 623         pinctrl_provide_dummies();
 624 }