2 * Broadcom BCM63138 PMB initialization for secondary CPU(s)
4 * Copyright (C) 2015 Broadcom Corporation
5 * Author: Florian Fainelli <f.fainelli@gmail.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 #include <linux/kernel.h>
14 #include <linux/spinlock.h>
15 #include <linux/reset/bcm63xx_pmb.h>
17 #include <linux/of_address.h>
19 #include "bcm63xx_smp.h"
21 /* ARM Control register definitions */
22 #define CORE_PWR_CTRL_SHIFT 0
23 #define CORE_PWR_CTRL_MASK 0x3
24 #define PLL_PWR_ON BIT(8)
25 #define PLL_LDO_PWR_ON BIT(9)
26 #define PLL_CLAMP_ON BIT(10)
27 #define CPU_RESET_N(x) BIT(13 + (x))
28 #define NEON_RESET_N BIT(15)
29 #define PWR_CTRL_STATUS_SHIFT 28
30 #define PWR_CTRL_STATUS_MASK 0x3
31 #define PWR_DOWN_SHIFT 30
32 #define PWR_DOWN_MASK 0x3
34 /* CPU Power control register definitions */
35 #define MEM_PWR_OK BIT(0)
36 #define MEM_PWR_ON BIT(1)
37 #define MEM_CLAMP_ON BIT(2)
38 #define MEM_PWR_OK_STATUS BIT(4)
39 #define MEM_PWR_ON_STATUS BIT(5)
40 #define MEM_PDA_SHIFT 8
41 #define MEM_PDA_MASK 0xf
42 #define MEM_PDA_CPU_MASK 0x1
43 #define MEM_PDA_NEON_MASK 0xf
44 #define CLAMP_ON BIT(15)
45 #define PWR_OK_SHIFT 16
46 #define PWR_OK_MASK 0xf
47 #define PWR_ON_SHIFT 20
48 #define PWR_CPU_MASK 0x03
49 #define PWR_NEON_MASK 0x01
50 #define PWR_ON_MASK 0xf
51 #define PWR_OK_STATUS_SHIFT 24
52 #define PWR_OK_STATUS_MASK 0xf
53 #define PWR_ON_STATUS_SHIFT 28
54 #define PWR_ON_STATUS_MASK 0xf
56 #define ARM_CONTROL 0x30
57 #define ARM_PWR_CONTROL_BASE 0x34
58 #define ARM_PWR_CONTROL(x) (ARM_PWR_CONTROL_BASE + (x) * 0x4)
59 #define ARM_NEON_L2 0x3c
61 /* Perform a value write, then spin until the value shifted by
62 * shift is seen, masked with mask and is different from cond.
64 static int bpcm_wr_rd_mask(void __iomem *master,
65 unsigned int addr, u32 off, u32 *val,
66 u32 shift, u32 mask, u32 cond)
70 ret = bpcm_wr(master, addr, off, *val);
75 ret = bpcm_rd(master, addr, off, val);
80 } while (((*val >> shift) & mask) != cond);
85 /* Global lock to serialize accesses to the PMB registers while we
86 * are bringing up the secondary CPU
88 static DEFINE_SPINLOCK(pmb_lock);
90 static int bcm63xx_pmb_get_resources(struct device_node *dn,
95 struct device_node *pmb_dn;
96 struct of_phandle_args args;
99 ret = of_property_read_u32(dn, "reg", cpu);
101 pr_err("CPU is missing a reg node\n");
105 ret = of_parse_phandle_with_args(dn, "resets", "#reset-cells",
108 pr_err("CPU is missing a resets phandle\n");
113 if (args.args_count != 2) {
114 pr_err("reset-controller does not conform to reset-cells\n");
118 *base = of_iomap(args.np, 0);
120 pr_err("failed remapping PMB register\n");
124 /* We do not need the number of zones */
125 *addr = args.args[0];
130 int bcm63xx_pmb_power_on_cpu(struct device_node *dn)
133 unsigned int cpu, addr;
138 ret = bcm63xx_pmb_get_resources(dn, &base, &cpu, &addr);
142 /* We would not know how to enable a third and greater CPU */
145 spin_lock_irqsave(&pmb_lock, flags);
147 /* Check if the CPU is already on and save the ARM_CONTROL register
148 * value since we will use it later for CPU de-assert once done with
149 * the CPU-specific power sequence
151 ret = bpcm_rd(base, addr, ARM_CONTROL, &ctrl);
155 if (ctrl & CPU_RESET_N(cpu)) {
156 pr_info("PMB: CPU%d is already powered on\n", cpu);
162 ret = bpcm_rd(base, addr, ARM_PWR_CONTROL(cpu), &val);
166 val |= (PWR_CPU_MASK << PWR_ON_SHIFT);
168 ret = bpcm_wr_rd_mask(base, addr, ARM_PWR_CONTROL(cpu), &val,
169 PWR_ON_STATUS_SHIFT, PWR_CPU_MASK, PWR_CPU_MASK);
173 val |= (PWR_CPU_MASK << PWR_OK_SHIFT);
175 ret = bpcm_wr_rd_mask(base, addr, ARM_PWR_CONTROL(cpu), &val,
176 PWR_OK_STATUS_SHIFT, PWR_CPU_MASK, PWR_CPU_MASK);
182 ret = bpcm_wr(base, addr, ARM_PWR_CONTROL(cpu), val);
186 /* Power on CPU<N> RAM */
187 val &= ~(MEM_PDA_MASK << MEM_PDA_SHIFT);
189 ret = bpcm_wr(base, addr, ARM_PWR_CONTROL(cpu), val);
195 ret = bpcm_wr_rd_mask(base, addr, ARM_PWR_CONTROL(cpu), &val,
196 0, MEM_PWR_ON_STATUS, MEM_PWR_ON_STATUS);
202 ret = bpcm_wr_rd_mask(base, addr, ARM_PWR_CONTROL(cpu), &val,
203 0, MEM_PWR_OK_STATUS, MEM_PWR_OK_STATUS);
207 val &= ~MEM_CLAMP_ON;
209 ret = bpcm_wr(base, addr, ARM_PWR_CONTROL(cpu), val);
213 /* De-assert CPU reset */
214 ctrl |= CPU_RESET_N(cpu);
216 ret = bpcm_wr(base, addr, ARM_CONTROL, ctrl);
218 spin_unlock_irqrestore(&pmb_lock, flags);