2 * Broadcom STB CPU SMP and hotplug support for ARM
4 * Copyright (C) 2013-2014 Broadcom Corporation
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/delay.h>
17 #include <linux/errno.h>
18 #include <linux/init.h>
20 #include <linux/of_address.h>
21 #include <linux/of_platform.h>
22 #include <linux/printk.h>
23 #include <linux/regmap.h>
24 #include <linux/smp.h>
25 #include <linux/mfd/syscon.h>
26 #include <linux/spinlock.h>
28 #include <asm/cacheflush.h>
30 #include <asm/mach-types.h>
31 #include <asm/smp_plat.h>
36 ZONE_MAN_CLKEN_MASK = BIT(0),
37 ZONE_MAN_RESET_CNTL_MASK = BIT(1),
38 ZONE_MAN_MEM_PWR_MASK = BIT(4),
39 ZONE_RESERVED_1_MASK = BIT(5),
40 ZONE_MAN_ISO_CNTL_MASK = BIT(6),
41 ZONE_MANUAL_CONTROL_MASK = BIT(7),
42 ZONE_PWR_DN_REQ_MASK = BIT(9),
43 ZONE_PWR_UP_REQ_MASK = BIT(10),
44 ZONE_BLK_RST_ASSERT_MASK = BIT(12),
45 ZONE_PWR_OFF_STATE_MASK = BIT(25),
46 ZONE_PWR_ON_STATE_MASK = BIT(26),
47 ZONE_DPG_PWR_STATE_MASK = BIT(28),
48 ZONE_MEM_PWR_STATE_MASK = BIT(29),
49 ZONE_RESET_STATE_MASK = BIT(31),
50 CPU0_PWR_ZONE_CTRL_REG = 1,
51 CPU_RESET_CONFIG_REG = 2,
54 static void __iomem *cpubiuctrl_block;
55 static void __iomem *hif_cont_block;
56 static u32 cpu0_pwr_zone_ctrl_reg;
57 static u32 cpu_rst_cfg_reg;
58 static u32 hif_cont_reg;
60 #ifdef CONFIG_HOTPLUG_CPU
61 static DEFINE_PER_CPU_ALIGNED(int, per_cpu_sw_state);
63 static int per_cpu_sw_state_rd(u32 cpu)
65 sync_cache_r(SHIFT_PERCPU_PTR(&per_cpu_sw_state, per_cpu_offset(cpu)));
66 return per_cpu(per_cpu_sw_state, cpu);
69 static void per_cpu_sw_state_wr(u32 cpu, int val)
71 per_cpu(per_cpu_sw_state, cpu) = val;
73 sync_cache_w(SHIFT_PERCPU_PTR(&per_cpu_sw_state, per_cpu_offset(cpu)));
77 static inline void per_cpu_sw_state_wr(u32 cpu, int val) { }
80 static void __iomem *pwr_ctrl_get_base(u32 cpu)
82 void __iomem *base = cpubiuctrl_block + cpu0_pwr_zone_ctrl_reg;
83 base += (cpu_logical_map(cpu) * 4);
87 static u32 pwr_ctrl_rd(u32 cpu)
89 void __iomem *base = pwr_ctrl_get_base(cpu);
90 return readl_relaxed(base);
93 static void pwr_ctrl_wr(u32 cpu, u32 val)
95 void __iomem *base = pwr_ctrl_get_base(cpu);
99 static void cpu_rst_cfg_set(u32 cpu, int set)
102 val = readl_relaxed(cpubiuctrl_block + cpu_rst_cfg_reg);
104 val |= BIT(cpu_logical_map(cpu));
106 val &= ~BIT(cpu_logical_map(cpu));
107 writel_relaxed(val, cpubiuctrl_block + cpu_rst_cfg_reg);
110 static void cpu_set_boot_addr(u32 cpu, unsigned long boot_addr)
112 const int reg_ofs = cpu_logical_map(cpu) * 8;
113 writel_relaxed(0, hif_cont_block + hif_cont_reg + reg_ofs);
114 writel_relaxed(boot_addr, hif_cont_block + hif_cont_reg + 4 + reg_ofs);
117 static void brcmstb_cpu_boot(u32 cpu)
119 pr_info("SMP: Booting CPU%d...\n", cpu);
122 * set the reset vector to point to the secondary_startup
125 cpu_set_boot_addr(cpu, virt_to_phys(brcmstb_secondary_startup));
128 cpu_rst_cfg_set(cpu, 0);
131 static void brcmstb_cpu_power_on(u32 cpu)
134 * The secondary cores power was cut, so we must go through
135 * power-on initialization.
139 pr_info("SMP: Powering up CPU%d...\n", cpu);
141 /* Request zone power up */
142 pwr_ctrl_wr(cpu, ZONE_PWR_UP_REQ_MASK);
144 /* Wait for the power up FSM to complete */
146 tmp = pwr_ctrl_rd(cpu);
147 } while (!(tmp & ZONE_PWR_ON_STATE_MASK));
149 per_cpu_sw_state_wr(cpu, 1);
152 static int brcmstb_cpu_get_power_state(u32 cpu)
154 int tmp = pwr_ctrl_rd(cpu);
155 return (tmp & ZONE_RESET_STATE_MASK) ? 0 : 1;
158 #ifdef CONFIG_HOTPLUG_CPU
160 static void brcmstb_cpu_die(u32 cpu)
162 v7_exit_coherency_flush(all);
164 /* Prevent all interrupts from reaching this CPU. */
165 arch_local_irq_disable();
168 * Final full barrier to ensure everything before this instruction has
174 per_cpu_sw_state_wr(cpu, 0);
176 /* Sit and wait to die */
179 /* We should never get here... */
180 panic("Spurious interrupt on CPU %d received!\n", cpu);
183 static int brcmstb_cpu_kill(u32 cpu)
187 pr_info("SMP: Powering down CPU%d...\n", cpu);
189 while (per_cpu_sw_state_rd(cpu))
192 /* Program zone reset */
193 pwr_ctrl_wr(cpu, ZONE_RESET_STATE_MASK | ZONE_BLK_RST_ASSERT_MASK |
194 ZONE_PWR_DN_REQ_MASK);
196 /* Verify zone reset */
197 tmp = pwr_ctrl_rd(cpu);
198 if (!(tmp & ZONE_RESET_STATE_MASK))
199 pr_err("%s: Zone reset bit for CPU %d not asserted!\n",
202 /* Wait for power down */
204 tmp = pwr_ctrl_rd(cpu);
205 } while (!(tmp & ZONE_PWR_OFF_STATE_MASK));
207 /* Settle-time from Broadcom-internal DVT reference code */
210 /* Assert reset on the CPU */
211 cpu_rst_cfg_set(cpu, 1);
216 #endif /* CONFIG_HOTPLUG_CPU */
218 static int __init setup_hifcpubiuctrl_regs(struct device_node *np)
222 struct device_node *syscon_np = NULL;
226 syscon_np = of_parse_phandle(np, name, 0);
228 pr_err("can't find phandle %s\n", name);
233 cpubiuctrl_block = of_iomap(syscon_np, 0);
234 if (!cpubiuctrl_block) {
235 pr_err("iomap failed for cpubiuctrl_block\n");
240 rc = of_property_read_u32_index(np, name, CPU0_PWR_ZONE_CTRL_REG,
241 &cpu0_pwr_zone_ctrl_reg);
243 pr_err("failed to read 1st entry from %s property (%d)\n", name,
249 rc = of_property_read_u32_index(np, name, CPU_RESET_CONFIG_REG,
252 pr_err("failed to read 2nd entry from %s property (%d)\n", name,
260 of_node_put(syscon_np);
265 static int __init setup_hifcont_regs(struct device_node *np)
269 struct device_node *syscon_np = NULL;
271 name = "syscon-cont";
273 syscon_np = of_parse_phandle(np, name, 0);
275 pr_err("can't find phandle %s\n", name);
280 hif_cont_block = of_iomap(syscon_np, 0);
281 if (!hif_cont_block) {
282 pr_err("iomap failed for hif_cont_block\n");
287 /* offset is at top of hif_cont_block */
292 of_node_put(syscon_np);
297 static void __init brcmstb_cpu_ctrl_setup(unsigned int max_cpus)
300 struct device_node *np;
303 name = "brcm,brcmstb-smpboot";
304 np = of_find_compatible_node(NULL, NULL, name);
306 pr_err("can't find compatible node %s\n", name);
310 rc = setup_hifcpubiuctrl_regs(np);
314 rc = setup_hifcont_regs(np);
319 static DEFINE_SPINLOCK(boot_lock);
321 static void brcmstb_secondary_init(unsigned int cpu)
324 * Synchronise with the boot thread.
326 spin_lock(&boot_lock);
327 spin_unlock(&boot_lock);
330 static int brcmstb_boot_secondary(unsigned int cpu, struct task_struct *idle)
333 * set synchronisation state between this boot processor
334 * and the secondary one
336 spin_lock(&boot_lock);
338 /* Bring up power to the core if necessary */
339 if (brcmstb_cpu_get_power_state(cpu) == 0)
340 brcmstb_cpu_power_on(cpu);
342 brcmstb_cpu_boot(cpu);
345 * now the secondary core is starting up let it run its
346 * calibrations, then wait for it to finish
348 spin_unlock(&boot_lock);
353 static struct smp_operations brcmstb_smp_ops __initdata = {
354 .smp_prepare_cpus = brcmstb_cpu_ctrl_setup,
355 .smp_secondary_init = brcmstb_secondary_init,
356 .smp_boot_secondary = brcmstb_boot_secondary,
357 #ifdef CONFIG_HOTPLUG_CPU
358 .cpu_kill = brcmstb_cpu_kill,
359 .cpu_die = brcmstb_cpu_die,
363 CPU_METHOD_OF_DECLARE(brcmstb_smp, "brcm,brahma-b15", &brcmstb_smp_ops);