2 * Broadcom STB CPU SMP and hotplug support for ARM
4 * Copyright (C) 2013-2014 Broadcom Corporation
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/delay.h>
17 #include <linux/errno.h>
18 #include <linux/init.h>
20 #include <linux/of_address.h>
21 #include <linux/of_platform.h>
22 #include <linux/printk.h>
23 #include <linux/regmap.h>
24 #include <linux/smp.h>
25 #include <linux/mfd/syscon.h>
27 #include <asm/cacheflush.h>
29 #include <asm/mach-types.h>
30 #include <asm/smp_plat.h>
35 ZONE_MAN_CLKEN_MASK = BIT(0),
36 ZONE_MAN_RESET_CNTL_MASK = BIT(1),
37 ZONE_MAN_MEM_PWR_MASK = BIT(4),
38 ZONE_RESERVED_1_MASK = BIT(5),
39 ZONE_MAN_ISO_CNTL_MASK = BIT(6),
40 ZONE_MANUAL_CONTROL_MASK = BIT(7),
41 ZONE_PWR_DN_REQ_MASK = BIT(9),
42 ZONE_PWR_UP_REQ_MASK = BIT(10),
43 ZONE_BLK_RST_ASSERT_MASK = BIT(12),
44 ZONE_PWR_OFF_STATE_MASK = BIT(25),
45 ZONE_PWR_ON_STATE_MASK = BIT(26),
46 ZONE_DPG_PWR_STATE_MASK = BIT(28),
47 ZONE_MEM_PWR_STATE_MASK = BIT(29),
48 ZONE_RESET_STATE_MASK = BIT(31),
49 CPU0_PWR_ZONE_CTRL_REG = 1,
50 CPU_RESET_CONFIG_REG = 2,
53 static void __iomem *cpubiuctrl_block;
54 static void __iomem *hif_cont_block;
55 static u32 cpu0_pwr_zone_ctrl_reg;
56 static u32 cpu_rst_cfg_reg;
57 static u32 hif_cont_reg;
59 #ifdef CONFIG_HOTPLUG_CPU
61 * We must quiesce a dying CPU before it can be killed by the boot CPU. Because
62 * one or more cache may be disabled, we must flush to ensure coherency. We
63 * cannot use traditionl completion structures or spinlocks as they rely on
66 static DEFINE_PER_CPU_ALIGNED(int, per_cpu_sw_state);
68 static int per_cpu_sw_state_rd(u32 cpu)
70 sync_cache_r(SHIFT_PERCPU_PTR(&per_cpu_sw_state, per_cpu_offset(cpu)));
71 return per_cpu(per_cpu_sw_state, cpu);
74 static void per_cpu_sw_state_wr(u32 cpu, int val)
77 per_cpu(per_cpu_sw_state, cpu) = val;
78 sync_cache_w(SHIFT_PERCPU_PTR(&per_cpu_sw_state, per_cpu_offset(cpu)));
81 static inline void per_cpu_sw_state_wr(u32 cpu, int val) { }
84 static void __iomem *pwr_ctrl_get_base(u32 cpu)
86 void __iomem *base = cpubiuctrl_block + cpu0_pwr_zone_ctrl_reg;
87 base += (cpu_logical_map(cpu) * 4);
91 static u32 pwr_ctrl_rd(u32 cpu)
93 void __iomem *base = pwr_ctrl_get_base(cpu);
94 return readl_relaxed(base);
97 static void pwr_ctrl_wr(u32 cpu, u32 val)
99 void __iomem *base = pwr_ctrl_get_base(cpu);
103 static void cpu_rst_cfg_set(u32 cpu, int set)
106 val = readl_relaxed(cpubiuctrl_block + cpu_rst_cfg_reg);
108 val |= BIT(cpu_logical_map(cpu));
110 val &= ~BIT(cpu_logical_map(cpu));
111 writel_relaxed(val, cpubiuctrl_block + cpu_rst_cfg_reg);
114 static void cpu_set_boot_addr(u32 cpu, unsigned long boot_addr)
116 const int reg_ofs = cpu_logical_map(cpu) * 8;
117 writel_relaxed(0, hif_cont_block + hif_cont_reg + reg_ofs);
118 writel_relaxed(boot_addr, hif_cont_block + hif_cont_reg + 4 + reg_ofs);
121 static void brcmstb_cpu_boot(u32 cpu)
123 /* Mark this CPU as "up" */
124 per_cpu_sw_state_wr(cpu, 1);
127 * Set the reset vector to point to the secondary_startup
130 cpu_set_boot_addr(cpu, virt_to_phys(brcmstb_secondary_startup));
133 cpu_rst_cfg_set(cpu, 0);
136 static void brcmstb_cpu_power_on(u32 cpu)
139 * The secondary cores power was cut, so we must go through
140 * power-on initialization.
144 /* Request zone power up */
145 pwr_ctrl_wr(cpu, ZONE_PWR_UP_REQ_MASK);
147 /* Wait for the power up FSM to complete */
149 tmp = pwr_ctrl_rd(cpu);
150 } while (!(tmp & ZONE_PWR_ON_STATE_MASK));
153 static int brcmstb_cpu_get_power_state(u32 cpu)
155 int tmp = pwr_ctrl_rd(cpu);
156 return (tmp & ZONE_RESET_STATE_MASK) ? 0 : 1;
159 #ifdef CONFIG_HOTPLUG_CPU
161 static void brcmstb_cpu_die(u32 cpu)
163 v7_exit_coherency_flush(all);
165 per_cpu_sw_state_wr(cpu, 0);
167 /* Sit and wait to die */
170 /* We should never get here... */
175 static int brcmstb_cpu_kill(u32 cpu)
179 while (per_cpu_sw_state_rd(cpu))
182 /* Program zone reset */
183 pwr_ctrl_wr(cpu, ZONE_RESET_STATE_MASK | ZONE_BLK_RST_ASSERT_MASK |
184 ZONE_PWR_DN_REQ_MASK);
186 /* Verify zone reset */
187 tmp = pwr_ctrl_rd(cpu);
188 if (!(tmp & ZONE_RESET_STATE_MASK))
189 pr_err("%s: Zone reset bit for CPU %d not asserted!\n",
192 /* Wait for power down */
194 tmp = pwr_ctrl_rd(cpu);
195 } while (!(tmp & ZONE_PWR_OFF_STATE_MASK));
197 /* Flush pipeline before resetting CPU */
200 /* Assert reset on the CPU */
201 cpu_rst_cfg_set(cpu, 1);
206 #endif /* CONFIG_HOTPLUG_CPU */
208 static int __init setup_hifcpubiuctrl_regs(struct device_node *np)
212 struct device_node *syscon_np = NULL;
216 syscon_np = of_parse_phandle(np, name, 0);
218 pr_err("can't find phandle %s\n", name);
223 cpubiuctrl_block = of_iomap(syscon_np, 0);
224 if (!cpubiuctrl_block) {
225 pr_err("iomap failed for cpubiuctrl_block\n");
230 rc = of_property_read_u32_index(np, name, CPU0_PWR_ZONE_CTRL_REG,
231 &cpu0_pwr_zone_ctrl_reg);
233 pr_err("failed to read 1st entry from %s property (%d)\n", name,
239 rc = of_property_read_u32_index(np, name, CPU_RESET_CONFIG_REG,
242 pr_err("failed to read 2nd entry from %s property (%d)\n", name,
249 of_node_put(syscon_np);
253 static int __init setup_hifcont_regs(struct device_node *np)
257 struct device_node *syscon_np = NULL;
259 name = "syscon-cont";
261 syscon_np = of_parse_phandle(np, name, 0);
263 pr_err("can't find phandle %s\n", name);
268 hif_cont_block = of_iomap(syscon_np, 0);
269 if (!hif_cont_block) {
270 pr_err("iomap failed for hif_cont_block\n");
275 /* Offset is at top of hif_cont_block */
279 of_node_put(syscon_np);
283 static void __init brcmstb_cpu_ctrl_setup(unsigned int max_cpus)
286 struct device_node *np;
289 name = "brcm,brcmstb-smpboot";
290 np = of_find_compatible_node(NULL, NULL, name);
292 pr_err("can't find compatible node %s\n", name);
296 rc = setup_hifcpubiuctrl_regs(np);
300 rc = setup_hifcont_regs(np);
305 static int brcmstb_boot_secondary(unsigned int cpu, struct task_struct *idle)
307 /* Missing the brcm,brcmstb-smpboot DT node? */
308 if (!cpubiuctrl_block || !hif_cont_block)
311 /* Bring up power to the core if necessary */
312 if (brcmstb_cpu_get_power_state(cpu) == 0)
313 brcmstb_cpu_power_on(cpu);
315 brcmstb_cpu_boot(cpu);
320 static struct smp_operations brcmstb_smp_ops __initdata = {
321 .smp_prepare_cpus = brcmstb_cpu_ctrl_setup,
322 .smp_boot_secondary = brcmstb_boot_secondary,
323 #ifdef CONFIG_HOTPLUG_CPU
324 .cpu_kill = brcmstb_cpu_kill,
325 .cpu_die = brcmstb_cpu_die,
329 CPU_METHOD_OF_DECLARE(brcmstb_smp, "brcm,brahma-b15", &brcmstb_smp_ops);