2 * Cavium Networks CNS3420 Validation Board
4 * Copyright 2000 Deep Blue Solutions Ltd
5 * Copyright 2008 ARM Limited
6 * Copyright 2008 Cavium Networks
8 * Copyright 2010 MontaVista Software, LLC.
9 * Anton Vorontsov <avorontsov@mvista.com>
11 * This file is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License, Version 2, as
13 * published by the Free Software Foundation.
16 #include <linux/init.h>
17 #include <linux/kernel.h>
18 #include <linux/compiler.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/serial_core.h>
22 #include <linux/serial_8250.h>
23 #include <linux/platform_device.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/physmap.h>
26 #include <linux/mtd/partitions.h>
27 #include <asm/setup.h>
28 #include <asm/mach-types.h>
29 #include <asm/mach/arch.h>
30 #include <asm/mach/map.h>
31 #include <asm/mach/time.h>
32 #include <mach/cns3xxx.h>
33 #include <mach/irqs.h>
40 static struct mtd_partition cns3420_nor_partitions[] = {
45 .mask_flags = MTD_WRITEABLE,
49 .offset = MTDPART_OFS_APPEND,
53 .offset = MTDPART_OFS_APPEND,
55 .name = "filesystem2",
57 .offset = MTDPART_OFS_APPEND,
60 .size = MTDPART_SIZ_FULL,
61 .offset = MTDPART_OFS_APPEND,
65 static struct physmap_flash_data cns3420_nor_pdata = {
67 .parts = cns3420_nor_partitions,
68 .nr_parts = ARRAY_SIZE(cns3420_nor_partitions),
71 static struct resource cns3420_nor_res = {
72 .start = CNS3XXX_FLASH_BASE,
73 .end = CNS3XXX_FLASH_BASE + SZ_128M - 1,
74 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
77 static struct platform_device cns3420_nor_pdev = {
78 .name = "physmap-flash",
80 .resource = &cns3420_nor_res,
83 .platform_data = &cns3420_nor_pdata,
90 static void __init cns3420_early_serial_setup(void)
92 #ifdef CONFIG_SERIAL_8250_CONSOLE
93 static struct uart_port cns3420_serial_port = {
94 .membase = (void __iomem *)CNS3XXX_UART0_BASE_VIRT,
95 .mapbase = CNS3XXX_UART0_BASE,
96 .irq = IRQ_CNS3XXX_UART0,
98 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
106 early_serial_setup(&cns3420_serial_port);
113 static struct resource cns3xxx_usb_ehci_resources[] = {
115 .start = CNS3XXX_USB_BASE,
116 .end = CNS3XXX_USB_BASE + SZ_16M - 1,
117 .flags = IORESOURCE_MEM,
120 .start = IRQ_CNS3XXX_USB_EHCI,
121 .flags = IORESOURCE_IRQ,
125 static u64 cns3xxx_usb_ehci_dma_mask = DMA_BIT_MASK(32);
127 static struct platform_device cns3xxx_usb_ehci_device = {
128 .name = "cns3xxx-ehci",
129 .num_resources = ARRAY_SIZE(cns3xxx_usb_ehci_resources),
130 .resource = cns3xxx_usb_ehci_resources,
132 .dma_mask = &cns3xxx_usb_ehci_dma_mask,
133 .coherent_dma_mask = DMA_BIT_MASK(32),
137 static struct resource cns3xxx_usb_ohci_resources[] = {
139 .start = CNS3XXX_USB_OHCI_BASE,
140 .end = CNS3XXX_USB_OHCI_BASE + SZ_16M - 1,
141 .flags = IORESOURCE_MEM,
144 .start = IRQ_CNS3XXX_USB_OHCI,
145 .flags = IORESOURCE_IRQ,
149 static u64 cns3xxx_usb_ohci_dma_mask = DMA_BIT_MASK(32);
151 static struct platform_device cns3xxx_usb_ohci_device = {
152 .name = "cns3xxx-ohci",
153 .num_resources = ARRAY_SIZE(cns3xxx_usb_ohci_resources),
154 .resource = cns3xxx_usb_ohci_resources,
156 .dma_mask = &cns3xxx_usb_ohci_dma_mask,
157 .coherent_dma_mask = DMA_BIT_MASK(32),
164 static struct platform_device *cns3420_pdevs[] __initdata = {
166 &cns3xxx_usb_ehci_device,
167 &cns3xxx_usb_ohci_device,
170 static void __init cns3420_init(void)
174 platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));
177 cns3xxx_sdhci_init();
179 pm_power_off = cns3xxx_power_off;
182 static struct map_desc cns3420_io_desc[] __initdata = {
184 .virtual = CNS3XXX_UART0_BASE_VIRT,
185 .pfn = __phys_to_pfn(CNS3XXX_UART0_BASE),
191 static void __init cns3420_map_io(void)
194 iotable_init(cns3420_io_desc, ARRAY_SIZE(cns3420_io_desc));
196 cns3420_early_serial_setup();
199 MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board")
200 .atag_offset = 0x100,
201 .map_io = cns3420_map_io,
202 .init_irq = cns3xxx_init_irq,
203 .timer = &cns3xxx_timer,
204 .init_machine = cns3420_init,