2 * PCI-E support for CNS3xxx
4 * Copyright 2008 Cavium Networks
5 * Richard Liu <richard.liu@caviumnetworks.com>
6 * Copyright 2010 MontaVista Software, LLC.
7 * Anton Vorontsov <avorontsov@mvista.com>
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/bug.h>
17 #include <linux/pci.h>
19 #include <linux/ioport.h>
20 #include <linux/interrupt.h>
21 #include <linux/ptrace.h>
22 #include <asm/mach/map.h>
27 void __iomem *host_regs; /* PCI config registers for host bridge */
28 void __iomem *cfg0_regs; /* PCI Type 0 config registers */
29 void __iomem *cfg1_regs; /* PCI Type 1 config registers */
31 struct resource res_io;
32 struct resource res_mem;
38 static struct cns3xxx_pcie cns3xxx_pcie[]; /* forward decl. */
40 static struct cns3xxx_pcie *sysdata_to_cnspci(void *sysdata)
42 struct pci_sys_data *root = sysdata;
44 return &cns3xxx_pcie[root->domain];
47 static struct cns3xxx_pcie *pdev_to_cnspci(const struct pci_dev *dev)
49 return sysdata_to_cnspci(dev->sysdata);
52 static struct cns3xxx_pcie *pbus_to_cnspci(struct pci_bus *bus)
54 return sysdata_to_cnspci(bus->sysdata);
57 static void __iomem *cns3xxx_pci_cfg_base(struct pci_bus *bus,
58 unsigned int devfn, int where)
60 struct cns3xxx_pcie *cnspci = pbus_to_cnspci(bus);
61 int busno = bus->number;
62 int slot = PCI_SLOT(devfn);
65 /* If there is no link, just show the CNS PCI bridge. */
66 if (!cnspci->linked && busno > 0)
70 * The CNS PCI bridge doesn't fit into the PCI hierarchy, though
71 * we still want to access it. For this to work, we must place
72 * the first device on the same bus as the CNS PCI bridge.
74 if (busno == 0) { /* internal PCIe bus, host bridge device */
75 if (devfn == 0) /* device# and function# are ignored by hw */
76 base = cnspci->host_regs;
78 return NULL; /* no such device */
80 } else if (busno == 1) { /* directly connected PCIe device */
81 if (slot == 0) /* device# is ignored by hw */
82 base = cnspci->cfg0_regs;
84 return NULL; /* no such device */
85 } else /* remote PCI bus */
86 base = cnspci->cfg1_regs + ((busno & 0xf) << 20);
88 return base + (where & 0xffc) + (devfn << 12);
91 static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
92 int where, int size, u32 *val)
96 u32 mask = (0x1ull << (size * 8)) - 1;
97 int shift = (where % 4) * 8;
99 base = cns3xxx_pci_cfg_base(bus, devfn, where);
102 return PCIBIOS_SUCCESSFUL;
105 v = __raw_readl(base);
107 if (bus->number == 0 && devfn == 0 &&
108 (where & 0xffc) == PCI_CLASS_REVISION) {
110 * RC's class is 0xb, but Linux PCI driver needs 0x604
111 * for a PCIe bridge. So we must fixup the class code
118 *val = (v >> shift) & mask;
120 return PCIBIOS_SUCCESSFUL;
123 static int cns3xxx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
124 int where, int size, u32 val)
128 u32 mask = (0x1ull << (size * 8)) - 1;
129 int shift = (where % 4) * 8;
131 base = cns3xxx_pci_cfg_base(bus, devfn, where);
133 return PCIBIOS_SUCCESSFUL;
135 v = __raw_readl(base);
137 v &= ~(mask << shift);
138 v |= (val & mask) << shift;
140 __raw_writel(v, base);
142 return PCIBIOS_SUCCESSFUL;
145 static int cns3xxx_pci_setup(int nr, struct pci_sys_data *sys)
147 struct cns3xxx_pcie *cnspci = sysdata_to_cnspci(sys);
148 struct resource *res_io = &cnspci->res_io;
149 struct resource *res_mem = &cnspci->res_mem;
151 BUG_ON(request_resource(&iomem_resource, res_io) ||
152 request_resource(&iomem_resource, res_mem));
154 pci_add_resource_offset(&sys->resources, res_io, sys->io_offset);
155 pci_add_resource_offset(&sys->resources, res_mem, sys->mem_offset);
160 static struct pci_ops cns3xxx_pcie_ops = {
161 .read = cns3xxx_pci_read_config,
162 .write = cns3xxx_pci_write_config,
165 static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
167 struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev);
168 int irq = cnspci->irqs[!!dev->bus->number];
170 pr_info("PCIe map irq: %04d:%02x:%02x.%02x slot %d, pin %d, irq: %d\n",
171 pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn),
172 PCI_FUNC(dev->devfn), slot, pin, irq);
177 static struct cns3xxx_pcie cns3xxx_pcie[] = {
179 .host_regs = (void __iomem *)CNS3XXX_PCIE0_HOST_BASE_VIRT,
180 .cfg0_regs = (void __iomem *)CNS3XXX_PCIE0_CFG0_BASE_VIRT,
181 .cfg1_regs = (void __iomem *)CNS3XXX_PCIE0_CFG1_BASE_VIRT,
183 .name = "PCIe0 I/O space",
184 .start = CNS3XXX_PCIE0_IO_BASE,
185 .end = CNS3XXX_PCIE0_CFG0_BASE - 1, /* 16 MiB */
186 .flags = IORESOURCE_IO,
189 .name = "PCIe0 non-prefetchable",
190 .start = CNS3XXX_PCIE0_MEM_BASE,
191 .end = CNS3XXX_PCIE0_HOST_BASE - 1, /* 176 MiB */
192 .flags = IORESOURCE_MEM,
194 .irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, },
198 .ops = &cns3xxx_pcie_ops,
199 .setup = cns3xxx_pci_setup,
200 .map_irq = cns3xxx_pcie_map_irq,
204 .host_regs = (void __iomem *)CNS3XXX_PCIE1_HOST_BASE_VIRT,
205 .cfg0_regs = (void __iomem *)CNS3XXX_PCIE1_CFG0_BASE_VIRT,
206 .cfg1_regs = (void __iomem *)CNS3XXX_PCIE1_CFG1_BASE_VIRT,
208 .name = "PCIe1 I/O space",
209 .start = CNS3XXX_PCIE1_IO_BASE,
210 .end = CNS3XXX_PCIE1_CFG0_BASE - 1, /* 16 MiB */
211 .flags = IORESOURCE_IO,
214 .name = "PCIe1 non-prefetchable",
215 .start = CNS3XXX_PCIE1_MEM_BASE,
216 .end = CNS3XXX_PCIE1_HOST_BASE - 1, /* 176 MiB */
217 .flags = IORESOURCE_MEM,
219 .irqs = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, },
223 .ops = &cns3xxx_pcie_ops,
224 .setup = cns3xxx_pci_setup,
225 .map_irq = cns3xxx_pcie_map_irq,
230 static void __init cns3xxx_pcie_check_link(struct cns3xxx_pcie *cnspci)
232 int port = cnspci->hw_pci.domain;
236 reg = __raw_readl(MISC_PCIE_CTRL(port));
238 * Enable Application Request to 1, it will exit L1 automatically,
239 * but when chip back, it will use another clock, still can use 0x1.
242 __raw_writel(reg, MISC_PCIE_CTRL(port));
244 pr_info("PCIe: Port[%d] Enable PCIe LTSSM\n", port);
245 pr_info("PCIe: Port[%d] Check data link layer...", port);
249 reg = __raw_readl(MISC_PCIE_PM_DEBUG(port));
251 pr_info("Link up.\n");
254 } else if (time_after(jiffies, time + 50)) {
255 pr_info("Device not found.\n");
261 static void __init cns3xxx_pcie_hw_init(struct cns3xxx_pcie *cnspci)
263 int port = cnspci->hw_pci.domain;
264 struct pci_sys_data sd = {
267 struct pci_bus bus = {
269 .ops = &cns3xxx_pcie_ops,
272 u16 mem_base = cnspci->res_mem.start >> 16;
273 u16 mem_limit = cnspci->res_mem.end >> 16;
274 u16 io_base = cnspci->res_io.start >> 16;
275 u16 io_limit = cnspci->res_io.end >> 16;
281 pci_bus_write_config_byte(&bus, devfn, PCI_PRIMARY_BUS, 0);
282 pci_bus_write_config_byte(&bus, devfn, PCI_SECONDARY_BUS, 1);
283 pci_bus_write_config_byte(&bus, devfn, PCI_SUBORDINATE_BUS, 1);
285 pci_bus_read_config_byte(&bus, devfn, PCI_PRIMARY_BUS, &tmp8);
286 pci_bus_read_config_byte(&bus, devfn, PCI_SECONDARY_BUS, &tmp8);
287 pci_bus_read_config_byte(&bus, devfn, PCI_SUBORDINATE_BUS, &tmp8);
289 pci_bus_write_config_word(&bus, devfn, PCI_MEMORY_BASE, mem_base);
290 pci_bus_write_config_word(&bus, devfn, PCI_MEMORY_LIMIT, mem_limit);
291 pci_bus_write_config_word(&bus, devfn, PCI_IO_BASE_UPPER16, io_base);
292 pci_bus_write_config_word(&bus, devfn, PCI_IO_LIMIT_UPPER16, io_limit);
297 /* Set Device Max_Read_Request_Size to 128 byte */
298 bus.number = 1; /* directly connected PCIe device */
299 devfn = PCI_DEVFN(0, 0);
300 pos = pci_bus_find_capability(&bus, devfn, PCI_CAP_ID_EXP);
301 pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc);
302 if (dc & PCI_EXP_DEVCTL_READRQ) {
303 dc &= ~PCI_EXP_DEVCTL_READRQ;
304 pci_bus_write_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, dc);
305 pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc);
306 if (dc & PCI_EXP_DEVCTL_READRQ)
307 pr_warn("PCIe: Unable to set device Max_Read_Request_Size\n");
309 pr_info("PCIe: Max_Read_Request_Size set to 128 bytes\n");
311 /* Disable PCIe0 Interrupt Mask INTA to INTD */
312 __raw_writel(~0x3FFF, MISC_PCIE_INT_MASK(port));
315 static int cns3xxx_pcie_abort_handler(unsigned long addr, unsigned int fsr,
316 struct pt_regs *regs)
323 void __init cns3xxx_pcie_init_late(void)
330 hook_fault_code(16 + 6, cns3xxx_pcie_abort_handler, SIGBUS, 0,
331 "imprecise external abort");
333 for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
334 cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_PCIE(i));
335 cns3xxx_pwr_soft_rst(0x1 << PM_SOFT_RST_REG_OFFST_PCIE(i));
336 cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
337 cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
338 pci_common_init(&cns3xxx_pcie[i].hw_pci);
341 pci_assign_unassigned_resources();