2 * PCI-E support for CNS3xxx
4 * Copyright 2008 Cavium Networks
5 * Richard Liu <richard.liu@caviumnetworks.com>
6 * Copyright 2010 MontaVista Software, LLC.
7 * Anton Vorontsov <avorontsov@mvista.com>
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/bug.h>
17 #include <linux/pci.h>
19 #include <linux/ioport.h>
20 #include <linux/interrupt.h>
21 #include <linux/ptrace.h>
22 #include <asm/mach/map.h>
27 void __iomem *host_regs; /* PCI config registers for host bridge */
28 void __iomem *cfg0_regs; /* PCI Type 0 config registers */
29 void __iomem *cfg1_regs; /* PCI Type 1 config registers */
31 struct resource res_io;
32 struct resource res_mem;
37 static struct cns3xxx_pcie *sysdata_to_cnspci(void *sysdata)
39 struct pci_sys_data *root = sysdata;
41 return root->private_data;
44 static struct cns3xxx_pcie *pdev_to_cnspci(const struct pci_dev *dev)
46 return sysdata_to_cnspci(dev->sysdata);
49 static struct cns3xxx_pcie *pbus_to_cnspci(struct pci_bus *bus)
51 return sysdata_to_cnspci(bus->sysdata);
54 static void __iomem *cns3xxx_pci_cfg_base(struct pci_bus *bus,
55 unsigned int devfn, int where)
57 struct cns3xxx_pcie *cnspci = pbus_to_cnspci(bus);
58 int busno = bus->number;
59 int slot = PCI_SLOT(devfn);
62 /* If there is no link, just show the CNS PCI bridge. */
63 if (!cnspci->linked && busno > 0)
67 * The CNS PCI bridge doesn't fit into the PCI hierarchy, though
68 * we still want to access it. For this to work, we must place
69 * the first device on the same bus as the CNS PCI bridge.
71 if (busno == 0) { /* internal PCIe bus, host bridge device */
72 if (devfn == 0) /* device# and function# are ignored by hw */
73 base = cnspci->host_regs;
75 return NULL; /* no such device */
77 } else if (busno == 1) { /* directly connected PCIe device */
78 if (slot == 0) /* device# is ignored by hw */
79 base = cnspci->cfg0_regs;
81 return NULL; /* no such device */
82 } else /* remote PCI bus */
83 base = cnspci->cfg1_regs + ((busno & 0xf) << 20);
85 return base + (where & 0xffc) + (devfn << 12);
88 static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
89 int where, int size, u32 *val)
93 u32 mask = (0x1ull << (size * 8)) - 1;
94 int shift = (where % 4) * 8;
96 base = cns3xxx_pci_cfg_base(bus, devfn, where);
99 return PCIBIOS_SUCCESSFUL;
102 v = __raw_readl(base);
104 if (bus->number == 0 && devfn == 0 &&
105 (where & 0xffc) == PCI_CLASS_REVISION) {
107 * RC's class is 0xb, but Linux PCI driver needs 0x604
108 * for a PCIe bridge. So we must fixup the class code
115 *val = (v >> shift) & mask;
117 return PCIBIOS_SUCCESSFUL;
120 static int cns3xxx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
121 int where, int size, u32 val)
125 u32 mask = (0x1ull << (size * 8)) - 1;
126 int shift = (where % 4) * 8;
128 base = cns3xxx_pci_cfg_base(bus, devfn, where);
130 return PCIBIOS_SUCCESSFUL;
132 v = __raw_readl(base);
134 v &= ~(mask << shift);
135 v |= (val & mask) << shift;
137 __raw_writel(v, base);
139 return PCIBIOS_SUCCESSFUL;
142 static int cns3xxx_pci_setup(int nr, struct pci_sys_data *sys)
144 struct cns3xxx_pcie *cnspci = sysdata_to_cnspci(sys);
145 struct resource *res_io = &cnspci->res_io;
146 struct resource *res_mem = &cnspci->res_mem;
148 BUG_ON(request_resource(&iomem_resource, res_io) ||
149 request_resource(&iomem_resource, res_mem));
151 pci_add_resource_offset(&sys->resources, res_io, sys->io_offset);
152 pci_add_resource_offset(&sys->resources, res_mem, sys->mem_offset);
157 static struct pci_ops cns3xxx_pcie_ops = {
158 .read = cns3xxx_pci_read_config,
159 .write = cns3xxx_pci_write_config,
162 static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
164 struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev);
165 int irq = cnspci->irqs[!!dev->bus->number];
167 pr_info("PCIe map irq: %04d:%02x:%02x.%02x slot %d, pin %d, irq: %d\n",
168 pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn),
169 PCI_FUNC(dev->devfn), slot, pin, irq);
174 static struct cns3xxx_pcie cns3xxx_pcie[] = {
176 .host_regs = (void __iomem *)CNS3XXX_PCIE0_HOST_BASE_VIRT,
177 .cfg0_regs = (void __iomem *)CNS3XXX_PCIE0_CFG0_BASE_VIRT,
178 .cfg1_regs = (void __iomem *)CNS3XXX_PCIE0_CFG1_BASE_VIRT,
180 .name = "PCIe0 I/O space",
181 .start = CNS3XXX_PCIE0_IO_BASE,
182 .end = CNS3XXX_PCIE0_CFG0_BASE - 1, /* 16 MiB */
183 .flags = IORESOURCE_IO,
186 .name = "PCIe0 non-prefetchable",
187 .start = CNS3XXX_PCIE0_MEM_BASE,
188 .end = CNS3XXX_PCIE0_HOST_BASE - 1, /* 176 MiB */
189 .flags = IORESOURCE_MEM,
191 .irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, },
195 .host_regs = (void __iomem *)CNS3XXX_PCIE1_HOST_BASE_VIRT,
196 .cfg0_regs = (void __iomem *)CNS3XXX_PCIE1_CFG0_BASE_VIRT,
197 .cfg1_regs = (void __iomem *)CNS3XXX_PCIE1_CFG1_BASE_VIRT,
199 .name = "PCIe1 I/O space",
200 .start = CNS3XXX_PCIE1_IO_BASE,
201 .end = CNS3XXX_PCIE1_CFG0_BASE - 1, /* 16 MiB */
202 .flags = IORESOURCE_IO,
205 .name = "PCIe1 non-prefetchable",
206 .start = CNS3XXX_PCIE1_MEM_BASE,
207 .end = CNS3XXX_PCIE1_HOST_BASE - 1, /* 176 MiB */
208 .flags = IORESOURCE_MEM,
210 .irqs = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, },
215 static void __init cns3xxx_pcie_check_link(struct cns3xxx_pcie *cnspci)
217 int port = cnspci->port;
221 reg = __raw_readl(MISC_PCIE_CTRL(port));
223 * Enable Application Request to 1, it will exit L1 automatically,
224 * but when chip back, it will use another clock, still can use 0x1.
227 __raw_writel(reg, MISC_PCIE_CTRL(port));
229 pr_info("PCIe: Port[%d] Enable PCIe LTSSM\n", port);
230 pr_info("PCIe: Port[%d] Check data link layer...", port);
234 reg = __raw_readl(MISC_PCIE_PM_DEBUG(port));
236 pr_info("Link up.\n");
239 } else if (time_after(jiffies, time + 50)) {
240 pr_info("Device not found.\n");
246 static void __init cns3xxx_pcie_hw_init(struct cns3xxx_pcie *cnspci)
248 int port = cnspci->port;
249 struct pci_sys_data sd = {
250 .private_data = cnspci,
252 struct pci_bus bus = {
254 .ops = &cns3xxx_pcie_ops,
257 u16 mem_base = cnspci->res_mem.start >> 16;
258 u16 mem_limit = cnspci->res_mem.end >> 16;
259 u16 io_base = cnspci->res_io.start >> 16;
260 u16 io_limit = cnspci->res_io.end >> 16;
266 pci_bus_write_config_byte(&bus, devfn, PCI_PRIMARY_BUS, 0);
267 pci_bus_write_config_byte(&bus, devfn, PCI_SECONDARY_BUS, 1);
268 pci_bus_write_config_byte(&bus, devfn, PCI_SUBORDINATE_BUS, 1);
270 pci_bus_read_config_byte(&bus, devfn, PCI_PRIMARY_BUS, &tmp8);
271 pci_bus_read_config_byte(&bus, devfn, PCI_SECONDARY_BUS, &tmp8);
272 pci_bus_read_config_byte(&bus, devfn, PCI_SUBORDINATE_BUS, &tmp8);
274 pci_bus_write_config_word(&bus, devfn, PCI_MEMORY_BASE, mem_base);
275 pci_bus_write_config_word(&bus, devfn, PCI_MEMORY_LIMIT, mem_limit);
276 pci_bus_write_config_word(&bus, devfn, PCI_IO_BASE_UPPER16, io_base);
277 pci_bus_write_config_word(&bus, devfn, PCI_IO_LIMIT_UPPER16, io_limit);
282 /* Set Device Max_Read_Request_Size to 128 byte */
283 bus.number = 1; /* directly connected PCIe device */
284 devfn = PCI_DEVFN(0, 0);
285 pos = pci_bus_find_capability(&bus, devfn, PCI_CAP_ID_EXP);
286 pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc);
287 if (dc & PCI_EXP_DEVCTL_READRQ) {
288 dc &= ~PCI_EXP_DEVCTL_READRQ;
289 pci_bus_write_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, dc);
290 pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc);
291 if (dc & PCI_EXP_DEVCTL_READRQ)
292 pr_warn("PCIe: Unable to set device Max_Read_Request_Size\n");
294 pr_info("PCIe: Max_Read_Request_Size set to 128 bytes\n");
296 /* Disable PCIe0 Interrupt Mask INTA to INTD */
297 __raw_writel(~0x3FFF, MISC_PCIE_INT_MASK(port));
300 static int cns3xxx_pcie_abort_handler(unsigned long addr, unsigned int fsr,
301 struct pt_regs *regs)
308 void __init cns3xxx_pcie_init_late(void)
312 struct hw_pci hw_pci = {
314 .ops = &cns3xxx_pcie_ops,
315 .setup = cns3xxx_pci_setup,
316 .map_irq = cns3xxx_pcie_map_irq,
317 .private_data = &private_data,
323 hook_fault_code(16 + 6, cns3xxx_pcie_abort_handler, SIGBUS, 0,
324 "imprecise external abort");
326 for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
327 cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_PCIE(i));
328 cns3xxx_pwr_soft_rst(0x1 << PM_SOFT_RST_REG_OFFST_PCIE(i));
329 cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
330 cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
331 private_data = &cns3xxx_pcie[i];
332 pci_common_init(&hw_pci);
335 pci_assign_unassigned_resources();