2 * TI DaVinci EVM board support
4 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
6 * 2007 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/platform_device.h>
16 #include <linux/gpio.h>
17 #include <linux/leds.h>
18 #include <linux/memory.h>
20 #include <linux/i2c.h>
21 #include <linux/i2c/pcf857x.h>
22 #include <linux/i2c/at24.h>
23 #include <linux/etherdevice.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/nand.h>
26 #include <linux/mtd/partitions.h>
27 #include <linux/mtd/physmap.h>
29 #include <linux/phy.h>
30 #include <linux/clk.h>
32 #include <asm/setup.h>
33 #include <asm/mach-types.h>
35 #include <asm/mach/arch.h>
36 #include <asm/mach/map.h>
37 #include <asm/mach/flash.h>
39 #include <mach/dm644x.h>
40 #include <mach/common.h>
41 #include <mach/emac.h>
43 #include <mach/serial.h>
46 #include <mach/nand.h>
49 #define DM644X_EVM_PHY_MASK (0x2)
50 #define DM644X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
52 #define DAVINCI_CFC_ATA_BASE 0x01C66000
54 #define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e00000
55 #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
56 #define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
57 #define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x06000000
58 #define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x08000000
60 #define LXT971_PHY_ID (0x001378e2)
61 #define LXT971_PHY_MASK (0xfffffff0)
63 static struct emac_platform_data dm644x_evm_emac_pdata = {
64 .phy_mask = DM644X_EVM_PHY_MASK,
65 .mdio_max_freq = DM644X_EVM_MDIO_FREQUENCY,
68 static struct mtd_partition davinci_evm_norflash_partitions[] = {
69 /* bootloader (UBL, U-Boot, etc) in first 5 sectors */
74 .mask_flags = MTD_WRITEABLE, /* force read-only */
76 /* bootloader params in the next 1 sectors */
79 .offset = MTDPART_OFS_APPEND,
86 .offset = MTDPART_OFS_APPEND,
93 .offset = MTDPART_OFS_APPEND,
94 .size = MTDPART_SIZ_FULL,
99 static struct physmap_flash_data davinci_evm_norflash_data = {
101 .parts = davinci_evm_norflash_partitions,
102 .nr_parts = ARRAY_SIZE(davinci_evm_norflash_partitions),
105 /* NOTE: CFI probe will correctly detect flash part as 32M, but EMIF
106 * limits addresses to 16M, so using addresses past 16M will wrap */
107 static struct resource davinci_evm_norflash_resource = {
108 .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
109 .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
110 .flags = IORESOURCE_MEM,
113 static struct platform_device davinci_evm_norflash_device = {
114 .name = "physmap-flash",
117 .platform_data = &davinci_evm_norflash_data,
120 .resource = &davinci_evm_norflash_resource,
123 /* DM644x EVM includes a 64 MByte small-page NAND flash (16K blocks).
124 * It may used instead of the (default) NOR chip to boot, using TI's
125 * tools to install the secondary boot loader (UBL) and U-Boot.
127 struct mtd_partition davinci_evm_nandflash_partition[] = {
128 /* Bootloader layout depends on whose u-boot is installed, but we
129 * can hide all the details.
130 * - block 0 for u-boot environment ... in mainline u-boot
131 * - block 1 for UBL (plus up to four backup copies in blocks 2..5)
132 * - blocks 6...? for u-boot
133 * - blocks 16..23 for u-boot environment ... in TI's u-boot
136 .name = "bootloader",
138 .size = SZ_256K + SZ_128K,
139 .mask_flags = MTD_WRITEABLE, /* force read-only */
144 .offset = MTDPART_OFS_APPEND,
148 /* File system (older GIT kernels started this on the 5MB mark) */
150 .name = "filesystem",
151 .offset = MTDPART_OFS_APPEND,
152 .size = MTDPART_SIZ_FULL,
155 /* A few blocks at end hold a flash BBT ... created by TI's CCS
156 * using flashwriter_nand.out, but ignored by TI's versions of
157 * Linux and u-boot. We boot faster by using them.
161 static struct davinci_nand_pdata davinci_evm_nandflash_data = {
162 .parts = davinci_evm_nandflash_partition,
163 .nr_parts = ARRAY_SIZE(davinci_evm_nandflash_partition),
164 .ecc_mode = NAND_ECC_HW,
165 .options = NAND_USE_FLASH_BBT,
168 static struct resource davinci_evm_nandflash_resource[] = {
170 .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
171 .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
172 .flags = IORESOURCE_MEM,
174 .start = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
175 .end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
176 .flags = IORESOURCE_MEM,
180 static struct platform_device davinci_evm_nandflash_device = {
181 .name = "davinci_nand",
184 .platform_data = &davinci_evm_nandflash_data,
186 .num_resources = ARRAY_SIZE(davinci_evm_nandflash_resource),
187 .resource = davinci_evm_nandflash_resource,
190 static u64 davinci_fb_dma_mask = DMA_BIT_MASK(32);
192 static struct platform_device davinci_fb_device = {
196 .dma_mask = &davinci_fb_dma_mask,
197 .coherent_dma_mask = DMA_BIT_MASK(32),
202 static struct platform_device rtc_dev = {
203 .name = "rtc_davinci_evm",
207 static struct resource ide_resources[] = {
209 .start = DAVINCI_CFC_ATA_BASE,
210 .end = DAVINCI_CFC_ATA_BASE + 0x7ff,
211 .flags = IORESOURCE_MEM,
216 .flags = IORESOURCE_IRQ,
220 static u64 ide_dma_mask = DMA_BIT_MASK(32);
222 static struct platform_device ide_dev = {
223 .name = "palm_bk3710",
225 .resource = ide_resources,
226 .num_resources = ARRAY_SIZE(ide_resources),
228 .dma_mask = &ide_dma_mask,
229 .coherent_dma_mask = DMA_BIT_MASK(32),
233 /*----------------------------------------------------------------------*/
239 #define PCF_Uxx_BASE(x) (DAVINCI_N_GPIO + ((x) * 8))
244 static struct gpio_led evm_leds[] = {
245 { .name = "DS8", .active_low = 1,
246 .default_trigger = "heartbeat", },
247 { .name = "DS7", .active_low = 1, },
248 { .name = "DS6", .active_low = 1, },
249 { .name = "DS5", .active_low = 1, },
250 { .name = "DS4", .active_low = 1, },
251 { .name = "DS3", .active_low = 1, },
252 { .name = "DS2", .active_low = 1,
253 .default_trigger = "mmc0", },
254 { .name = "DS1", .active_low = 1,
255 .default_trigger = "ide-disk", },
258 static const struct gpio_led_platform_data evm_led_data = {
259 .num_leds = ARRAY_SIZE(evm_leds),
263 static struct platform_device *evm_led_dev;
266 evm_led_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
268 struct gpio_led *leds = evm_leds;
276 /* what an extremely annoying way to be forced to handle
277 * device unregistration ...
279 evm_led_dev = platform_device_alloc("leds-gpio", 0);
280 platform_device_add_data(evm_led_dev,
281 &evm_led_data, sizeof evm_led_data);
283 evm_led_dev->dev.parent = &client->dev;
284 status = platform_device_add(evm_led_dev);
286 platform_device_put(evm_led_dev);
293 evm_led_teardown(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
296 platform_device_unregister(evm_led_dev);
302 static struct pcf857x_platform_data pcf_data_u2 = {
303 .gpio_base = PCF_Uxx_BASE(0),
304 .setup = evm_led_setup,
305 .teardown = evm_led_teardown,
309 /* U18 - A/V clock generator and user switch */
314 sw_show(struct device *d, struct device_attribute *a, char *buf)
316 char *s = gpio_get_value_cansleep(sw_gpio) ? "on\n" : "off\n";
322 static DEVICE_ATTR(user_sw, S_IRUGO, sw_show, NULL);
325 evm_u18_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
329 /* export dip switch option */
331 status = gpio_request(sw_gpio, "user_sw");
333 status = gpio_direction_input(sw_gpio);
335 status = device_create_file(&client->dev, &dev_attr_user_sw);
341 /* audio PLL: 48 kHz (vs 44.1 or 32), single rate (vs double) */
342 gpio_request(gpio + 3, "pll_fs2");
343 gpio_direction_output(gpio + 3, 0);
345 gpio_request(gpio + 2, "pll_fs1");
346 gpio_direction_output(gpio + 2, 0);
348 gpio_request(gpio + 1, "pll_sr");
349 gpio_direction_output(gpio + 1, 0);
355 evm_u18_teardown(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
362 device_remove_file(&client->dev, &dev_attr_user_sw);
368 static struct pcf857x_platform_data pcf_data_u18 = {
369 .gpio_base = PCF_Uxx_BASE(1),
370 .n_latch = (1 << 3) | (1 << 2) | (1 << 1),
371 .setup = evm_u18_setup,
372 .teardown = evm_u18_teardown,
376 /* U35 - various I/O signals used to manage USB, CF, ATA, etc */
379 evm_u35_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
381 /* p0 = nDRV_VBUS (initial: don't supply it) */
382 gpio_request(gpio + 0, "nDRV_VBUS");
383 gpio_direction_output(gpio + 0, 1);
386 gpio_request(gpio + 1, "VDDIMX_EN");
387 gpio_direction_output(gpio + 1, 1);
390 gpio_request(gpio + 2, "VLYNQ_EN");
391 gpio_direction_output(gpio + 2, 1);
393 /* p3 = n3V3_CF_RESET (initial: stay in reset) */
394 gpio_request(gpio + 3, "nCF_RESET");
395 gpio_direction_output(gpio + 3, 0);
399 /* p5 = 1V8_WLAN_RESET (initial: stay in reset) */
400 gpio_request(gpio + 5, "WLAN_RESET");
401 gpio_direction_output(gpio + 5, 1);
403 /* p6 = nATA_SEL (initial: select) */
404 gpio_request(gpio + 6, "nATA_SEL");
405 gpio_direction_output(gpio + 6, 0);
407 /* p7 = nCF_SEL (initial: deselect) */
408 gpio_request(gpio + 7, "nCF_SEL");
409 gpio_direction_output(gpio + 7, 1);
411 /* irlml6401 switches over 1A, in under 8 msec;
412 * now it can be managed by nDRV_VBUS ...
420 evm_u35_teardown(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
432 static struct pcf857x_platform_data pcf_data_u35 = {
433 .gpio_base = PCF_Uxx_BASE(2),
434 .setup = evm_u35_setup,
435 .teardown = evm_u35_teardown,
438 /*----------------------------------------------------------------------*/
440 /* Most of this EEPROM is unused, but U-Boot uses some data:
441 * - 0x7f00, 6 bytes Ethernet Address
442 * - 0x0039, 1 byte NTSC vs PAL (bit 0x80 == PAL)
443 * - ... newer boards may have more
445 static struct memory_accessor *at24_mem_acc;
447 static void at24_setup(struct memory_accessor *mem_acc, void *context)
449 char mac_addr[ETH_ALEN];
451 at24_mem_acc = mem_acc;
453 /* Read MAC addr from EEPROM */
454 if (at24_mem_acc->read(at24_mem_acc, mac_addr, 0x7f00, ETH_ALEN) ==
456 printk(KERN_INFO "Read MAC addr from EEPROM: %pM\n", mac_addr);
457 memcpy(dm644x_evm_emac_pdata.mac_addr, mac_addr, ETH_ALEN);
461 static struct at24_platform_data eeprom_info = {
462 .byte_len = (256*1024) / 8,
464 .flags = AT24_FLAG_ADDR16,
469 * MSP430 supports RTC, card detection, input from IR remote, and
470 * a bit more. It triggers interrupts on GPIO(7) from pressing
471 * buttons on the IR remote, and for card detect switches.
473 static struct i2c_client *dm6446evm_msp;
475 static int dm6446evm_msp_probe(struct i2c_client *client,
476 const struct i2c_device_id *id)
478 dm6446evm_msp = client;
482 static int dm6446evm_msp_remove(struct i2c_client *client)
484 dm6446evm_msp = NULL;
488 static const struct i2c_device_id dm6446evm_msp_ids[] = {
489 { "dm6446evm_msp", 0, },
490 { /* end of list */ },
493 static struct i2c_driver dm6446evm_msp_driver = {
494 .driver.name = "dm6446evm_msp",
495 .id_table = dm6446evm_msp_ids,
496 .probe = dm6446evm_msp_probe,
497 .remove = dm6446evm_msp_remove,
500 static int dm6444evm_msp430_get_pins(void)
502 static const char txbuf[2] = { 2, 4, };
504 struct i2c_msg msg[2] = {
506 .addr = dm6446evm_msp->addr,
509 .buf = (void __force *)txbuf,
512 .addr = dm6446evm_msp->addr,
523 /* Command 4 == get input state, returns port 2 and port3 data
524 * S Addr W [A] len=2 [A] cmd=4 [A]
525 * RS Addr R [A] [len=4] A [cmd=4] A [port2] A [port3] N P
527 status = i2c_transfer(dm6446evm_msp->adapter, msg, 2);
531 dev_dbg(&dm6446evm_msp->dev,
532 "PINS: %02x %02x %02x %02x\n",
533 buf[0], buf[1], buf[2], buf[3]);
535 return (buf[3] << 8) | buf[2];
538 static int dm6444evm_mmc_get_cd(int module)
540 int status = dm6444evm_msp430_get_pins();
542 return (status < 0) ? status : !(status & BIT(1));
545 static int dm6444evm_mmc_get_ro(int module)
547 int status = dm6444evm_msp430_get_pins();
549 return (status < 0) ? status : status & BIT(6 + 8);
552 static struct davinci_mmc_config dm6446evm_mmc_config = {
553 .get_cd = dm6444evm_mmc_get_cd,
554 .get_ro = dm6444evm_mmc_get_ro,
556 .version = MMC_CTLR_VERSION_1
559 static struct i2c_board_info __initdata i2c_info[] = {
561 I2C_BOARD_INFO("dm6446evm_msp", 0x23),
564 I2C_BOARD_INFO("pcf8574", 0x38),
565 .platform_data = &pcf_data_u2,
568 I2C_BOARD_INFO("pcf8574", 0x39),
569 .platform_data = &pcf_data_u18,
572 I2C_BOARD_INFO("pcf8574", 0x3a),
573 .platform_data = &pcf_data_u35,
576 I2C_BOARD_INFO("24c256", 0x50),
577 .platform_data = &eeprom_info,
580 * - tvl320aic33 audio codec (0x1b)
581 * - tvp5146 video decoder (0x5d)
585 /* The msp430 uses a slow bitbanged I2C implementation (ergo 20 KHz),
586 * which requires 100 usec of idle bus after i2c writes sent to it.
588 static struct davinci_i2c_platform_data i2c_pdata = {
589 .bus_freq = 20 /* kHz */,
590 .bus_delay = 100 /* usec */,
593 static void __init evm_init_i2c(void)
595 davinci_init_i2c(&i2c_pdata);
596 i2c_add_driver(&dm6446evm_msp_driver);
597 i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
600 static struct platform_device *davinci_evm_devices[] __initdata = {
605 static struct davinci_uart_config uart_config __initdata = {
606 .enabled_uarts = (1 << 0),
610 davinci_evm_map_io(void)
612 davinci_map_common_io();
616 static int davinci_phy_fixup(struct phy_device *phydev)
618 unsigned int control;
619 /* CRITICAL: Fix for increasing PHY signal drive strength for
620 * TX lockup issue. On DaVinci EVM, the Intel LXT971 PHY
621 * signal strength was low causing TX to fail randomly. The
622 * fix is to Set bit 11 (Increased MII drive strength) of PHY
623 * register 26 (Digital Config register) on this phy. */
624 control = phy_read(phydev, 26);
625 phy_write(phydev, 26, (control | 0x800));
629 #if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
630 defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
636 #if defined(CONFIG_MTD_PHYSMAP) || \
637 defined(CONFIG_MTD_PHYSMAP_MODULE)
643 #if defined(CONFIG_MTD_NAND_DAVINCI) || \
644 defined(CONFIG_MTD_NAND_DAVINCI_MODULE)
650 static __init void davinci_evm_init(void)
652 struct clk *aemif_clk;
654 aemif_clk = clk_get(NULL, "aemif");
655 clk_enable(aemif_clk);
658 if (HAS_NAND || HAS_NOR)
659 pr_warning("WARNING: both IDE and Flash are "
660 "enabled, but they share AEMIF pins.\n"
661 "\tDisable IDE for NAND/NOR support.\n");
662 davinci_cfg_reg(DM644X_HPIEN_DISABLE);
663 davinci_cfg_reg(DM644X_ATAEN);
664 davinci_cfg_reg(DM644X_HDIREN);
665 platform_device_register(&ide_dev);
666 } else if (HAS_NAND || HAS_NOR) {
667 davinci_cfg_reg(DM644X_HPIEN_DISABLE);
668 davinci_cfg_reg(DM644X_ATAEN_DISABLE);
670 /* only one device will be jumpered and detected */
672 platform_device_register(&davinci_evm_nandflash_device);
673 evm_leds[7].default_trigger = "nand-disk";
675 pr_warning("WARNING: both NAND and NOR flash "
676 "are enabled; disable one of them.\n");
678 platform_device_register(&davinci_evm_norflash_device);
681 platform_add_devices(davinci_evm_devices,
682 ARRAY_SIZE(davinci_evm_devices));
685 davinci_setup_mmc(0, &dm6446evm_mmc_config);
687 davinci_serial_init(&uart_config);
689 dm644x_init_emac(&dm644x_evm_emac_pdata);
691 /* Register the fixup for PHY on DaVinci */
692 phy_register_fixup_for_uid(LXT971_PHY_ID, LXT971_PHY_MASK,
697 static __init void davinci_evm_irq_init(void)
702 MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM")
703 /* Maintainer: MontaVista Software <source@mvista.com> */
705 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
706 .boot_params = (DAVINCI_DDR_BASE + 0x100),
707 .map_io = davinci_evm_map_io,
708 .init_irq = davinci_evm_irq_init,
709 .timer = &davinci_timer,
710 .init_machine = davinci_evm_init,